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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: rockchip: add rk3128 soc dtsi
Add basic rk3128 support.
Features:
Quad-core ARM Cortex-A7MP Core processor
Clock & reset unit
Power management unit
Interrupt controller
DMAC
6x 64 bits Timers
4x PWMs
1x 32 bits watchdog
Internal memory:
Internal BootRom
Internal SRAM 8KB
External memory:
Dynamic Memory Interface (DDR3/DDR3L/LPDDR2)
Nand Flash Interface
eMMC Interface
SD/MMC Interface
Connectivity:
SDIO interface
SPI Controller
3x UART controller
4x I2C controllers
4x groups of GPIO (GPIO0~GPIO3), 32 GPIOs per group
USB Host2.0
USB OTG2.0
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/b7bac0b3-3c91-1026-d435-6b5e9d6492f3@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Johan Jonker
and committed by
Heiko Stuebner
a0201bff
ea02e211
+916
+916
arch/arm/boot/dts/rk3128.dtsi
+916
arch/arm/boot/dts/rk3128.dtsi
···
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/clock/rk3128-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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compatible = "rockchip,rk3128";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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};
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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};
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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arm,cpu-registers-not-fw-configured;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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pmu: syscon@100a0000 {
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compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
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reg = <0x100a0000 0x1000>;
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};
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gic: interrupt-controller@10139000 {
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compatible = "arm,cortex-a7-gic";
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reg = <0x10139000 0x1000>,
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<0x1013a000 0x1000>,
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<0x1013c000 0x2000>,
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<0x1013e000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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usb_otg: usb@10180000 {
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compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG>;
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clock-names = "otg";
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dr_mode = "otg";
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phys = <&usb2phy_otg>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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usb_host_ehci: usb@101c0000 {
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compatible = "generic-ehci";
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reg = <0x101c0000 0x20000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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usb_host_ohci: usb@101e0000 {
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compatible = "generic-ohci";
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reg = <0x101e0000 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb2phy_host>;
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phy-names = "usb";
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status = "disabled";
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};
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sdmmc: mmc@10214000 {
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compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x10214000 0x4000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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dmas = <&pdma 10>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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max-frequency = <150000000>;
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resets = <&cru SRST_SDMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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sdio: mmc@10218000 {
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compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x10218000 0x4000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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dmas = <&pdma 11>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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max-frequency = <150000000>;
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resets = <&cru SRST_SDIO>;
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reset-names = "reset";
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status = "disabled";
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};
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emmc: mmc@1021c000 {
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compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x1021c000 0x4000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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dmas = <&pdma 12>;
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dma-names = "rx-tx";
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fifo-depth = <256>;
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max-frequency = <150000000>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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nfc: nand-controller@10500000 {
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compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
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reg = <0x10500000 0x4000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
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clock-names = "ahb", "nfc";
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pinctrl-names = "default";
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pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
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&flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3128-cru";
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reg = <0x20000000 0x1000>;
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clocks = <&xin24m>;
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clock-names = "xin24m";
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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+
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grf: syscon@20008000 {
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compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
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reg = <0x20008000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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usb2phy: usb2phy@17c {
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compatible = "rockchip,rk3128-usb2phy";
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reg = <0x017c 0x0c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy";
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#clock-cells = <0>;
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status = "disabled";
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+
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usb2phy_host: host-port {
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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+
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usb2phy_otg: otg-port {
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-bvalid", "otg-id",
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"linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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timer0: timer@20044000 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x20044000 0x20>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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timer1: timer@20044020 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x20044020 0x20>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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timer2: timer@20044040 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x20044040 0x20>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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timer3: timer@20044060 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x20044060 0x20>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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timer4: timer@20044080 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x20044080 0x20>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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timer5: timer@200440a0 {
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compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
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reg = <0x200440a0 0x20>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&xin24m>;
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clock-names = "pclk", "timer";
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};
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+
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watchdog: watchdog@2004c000 {
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compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
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reg = <0x2004c000 0x100>;
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+
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_WDT>;
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status = "disabled";
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};
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+
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pwm0: pwm@20050000 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050000 0x10>;
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clocks = <&cru PCLK_PWM>;
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+
pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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+
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pwm1: pwm@20050010 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050010 0x10>;
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clocks = <&cru PCLK_PWM>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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+
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pwm2: pwm@20050020 {
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
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reg = <0x20050020 0x10>;
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clocks = <&cru PCLK_PWM>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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+
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pwm3: pwm@20050030 {
319
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compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
320
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reg = <0x20050030 0x10>;
321
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clocks = <&cru PCLK_PWM>;
322
+
pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
324
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#pwm-cells = <3>;
325
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status = "disabled";
326
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};
327
+
328
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i2c1: i2c@20056000 {
329
+
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
330
+
reg = <0x20056000 0x1000>;
331
+
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
332
+
clock-names = "i2c";
333
+
clocks = <&cru PCLK_I2C1>;
334
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pinctrl-names = "default";
335
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pinctrl-0 = <&i2c1_xfer>;
336
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#address-cells = <1>;
337
+
#size-cells = <0>;
338
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status = "disabled";
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};
340
+
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i2c2: i2c@2005a000 {
342
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compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
343
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reg = <0x2005a000 0x1000>;
344
+
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
345
+
clock-names = "i2c";
346
+
clocks = <&cru PCLK_I2C2>;
347
+
pinctrl-names = "default";
348
+
pinctrl-0 = <&i2c2_xfer>;
349
+
#address-cells = <1>;
350
+
#size-cells = <0>;
351
+
status = "disabled";
352
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};
353
+
354
+
i2c3: i2c@2005e000 {
355
+
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
356
+
reg = <0x2005e000 0x1000>;
357
+
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
358
+
clock-names = "i2c";
359
+
clocks = <&cru PCLK_I2C3>;
360
+
pinctrl-names = "default";
361
+
pinctrl-0 = <&i2c3_xfer>;
362
+
#address-cells = <1>;
363
+
#size-cells = <0>;
364
+
status = "disabled";
365
+
};
366
+
367
+
uart0: serial@20060000 {
368
+
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
369
+
reg = <0x20060000 0x100>;
370
+
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
371
+
clock-frequency = <24000000>;
372
+
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
373
+
clock-names = "baudclk", "apb_pclk";
374
+
dmas = <&pdma 2>, <&pdma 3>;
375
+
dma-names = "tx", "rx";
376
+
pinctrl-names = "default";
377
+
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
378
+
reg-io-width = <4>;
379
+
reg-shift = <2>;
380
+
status = "disabled";
381
+
};
382
+
383
+
uart1: serial@20064000 {
384
+
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
385
+
reg = <0x20064000 0x100>;
386
+
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
387
+
clock-frequency = <24000000>;
388
+
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
389
+
clock-names = "baudclk", "apb_pclk";
390
+
dmas = <&pdma 4>, <&pdma 5>;
391
+
dma-names = "tx", "rx";
392
+
pinctrl-names = "default";
393
+
pinctrl-0 = <&uart1_xfer>;
394
+
reg-io-width = <4>;
395
+
reg-shift = <2>;
396
+
status = "disabled";
397
+
};
398
+
399
+
uart2: serial@20068000 {
400
+
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
401
+
reg = <0x20068000 0x100>;
402
+
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
403
+
clock-frequency = <24000000>;
404
+
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
405
+
clock-names = "baudclk", "apb_pclk";
406
+
dmas = <&pdma 6>, <&pdma 7>;
407
+
dma-names = "tx", "rx";
408
+
pinctrl-names = "default";
409
+
pinctrl-0 = <&uart2_xfer>;
410
+
reg-io-width = <4>;
411
+
reg-shift = <2>;
412
+
status = "disabled";
413
+
};
414
+
415
+
saradc: saradc@2006c000 {
416
+
compatible = "rockchip,saradc";
417
+
reg = <0x2006c000 0x100>;
418
+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
419
+
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
420
+
clock-names = "saradc", "apb_pclk";
421
+
resets = <&cru SRST_SARADC>;
422
+
reset-names = "saradc-apb";
423
+
#io-channel-cells = <1>;
424
+
status = "disabled";
425
+
};
426
+
427
+
i2c0: i2c@20072000 {
428
+
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
429
+
reg = <20072000 0x1000>;
430
+
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
431
+
clock-names = "i2c";
432
+
clocks = <&cru PCLK_I2C0>;
433
+
pinctrl-names = "default";
434
+
pinctrl-0 = <&i2c0_xfer>;
435
+
#address-cells = <1>;
436
+
#size-cells = <0>;
437
+
status = "disabled";
438
+
};
439
+
440
+
spi0: spi@20074000 {
441
+
compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
442
+
reg = <0x20074000 0x1000>;
443
+
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
444
+
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
445
+
clock-names = "spiclk", "apb_pclk";
446
+
dmas = <&pdma 8>, <&pdma 9>;
447
+
dma-names = "tx", "rx";
448
+
pinctrl-names = "default";
449
+
pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
450
+
#address-cells = <1>;
451
+
#size-cells = <0>;
452
+
status = "disabled";
453
+
};
454
+
455
+
pdma: dma-controller@20078000 {
456
+
compatible = "arm,pl330", "arm,primecell";
457
+
reg = <0x20078000 0x4000>;
458
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
459
+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
460
+
arm,pl330-broken-no-flushp;
461
+
clocks = <&cru ACLK_DMAC>;
462
+
clock-names = "apb_pclk";
463
+
#dma-cells = <1>;
464
+
};
465
+
466
+
pinctrl: pinctrl {
467
+
compatible = "rockchip,rk3128-pinctrl";
468
+
rockchip,grf = <&grf>;
469
+
#address-cells = <1>;
470
+
#size-cells = <1>;
471
+
ranges;
472
+
473
+
gpio0: gpio@2007c000 {
474
+
compatible = "rockchip,gpio-bank";
475
+
reg = <0x2007c000 0x100>;
476
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
477
+
clocks = <&cru PCLK_GPIO0>;
478
+
gpio-controller;
479
+
#gpio-cells = <2>;
480
+
interrupt-controller;
481
+
#interrupt-cells = <2>;
482
+
};
483
+
484
+
gpio1: gpio@20080000 {
485
+
compatible = "rockchip,gpio-bank";
486
+
reg = <0x20080000 0x100>;
487
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
488
+
clocks = <&cru PCLK_GPIO1>;
489
+
gpio-controller;
490
+
#gpio-cells = <2>;
491
+
interrupt-controller;
492
+
#interrupt-cells = <2>;
493
+
};
494
+
495
+
gpio2: gpio@20084000 {
496
+
compatible = "rockchip,gpio-bank";
497
+
reg = <0x20084000 0x100>;
498
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
499
+
clocks = <&cru PCLK_GPIO2>;
500
+
gpio-controller;
501
+
#gpio-cells = <2>;
502
+
interrupt-controller;
503
+
#interrupt-cells = <2>;
504
+
};
505
+
506
+
gpio3: gpio@20088000 {
507
+
compatible = "rockchip,gpio-bank";
508
+
reg = <0x20088000 0x100>;
509
+
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
510
+
clocks = <&cru PCLK_GPIO3>;
511
+
gpio-controller;
512
+
#gpio-cells = <2>;
513
+
interrupt-controller;
514
+
#interrupt-cells = <2>;
515
+
};
516
+
517
+
pcfg_pull_default: pcfg-pull-default {
518
+
bias-pull-pin-default;
519
+
};
520
+
521
+
pcfg_pull_none: pcfg-pull-none {
522
+
bias-disable;
523
+
};
524
+
525
+
emmc {
526
+
emmc_clk: emmc-clk {
527
+
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
528
+
};
529
+
530
+
emmc_cmd: emmc-cmd {
531
+
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
532
+
};
533
+
534
+
emmc_cmd1: emmc-cmd1 {
535
+
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
536
+
};
537
+
538
+
emmc_pwr: emmc-pwr {
539
+
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
540
+
};
541
+
542
+
emmc_bus1: emmc-bus1 {
543
+
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
544
+
};
545
+
546
+
emmc_bus4: emmc-bus4 {
547
+
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
548
+
<1 RK_PD1 2 &pcfg_pull_default>,
549
+
<1 RK_PD2 2 &pcfg_pull_default>,
550
+
<1 RK_PD3 2 &pcfg_pull_default>;
551
+
};
552
+
553
+
emmc_bus8: emmc-bus8 {
554
+
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
555
+
<1 RK_PD1 2 &pcfg_pull_default>,
556
+
<1 RK_PD2 2 &pcfg_pull_default>,
557
+
<1 RK_PD3 2 &pcfg_pull_default>,
558
+
<1 RK_PD4 2 &pcfg_pull_default>,
559
+
<1 RK_PD5 2 &pcfg_pull_default>,
560
+
<1 RK_PD6 2 &pcfg_pull_default>,
561
+
<1 RK_PD7 2 &pcfg_pull_default>;
562
+
};
563
+
};
564
+
565
+
gmac {
566
+
rgmii_pins: rgmii-pins {
567
+
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
568
+
<2 RK_PB1 3 &pcfg_pull_default>,
569
+
<2 RK_PB3 3 &pcfg_pull_default>,
570
+
<2 RK_PB4 3 &pcfg_pull_default>,
571
+
<2 RK_PB5 3 &pcfg_pull_default>,
572
+
<2 RK_PB6 3 &pcfg_pull_default>,
573
+
<2 RK_PC0 3 &pcfg_pull_default>,
574
+
<2 RK_PC1 3 &pcfg_pull_default>,
575
+
<2 RK_PC2 3 &pcfg_pull_default>,
576
+
<2 RK_PC3 3 &pcfg_pull_default>,
577
+
<2 RK_PD1 3 &pcfg_pull_default>,
578
+
<2 RK_PC4 4 &pcfg_pull_default>,
579
+
<2 RK_PC5 4 &pcfg_pull_default>,
580
+
<2 RK_PC6 4 &pcfg_pull_default>,
581
+
<2 RK_PC7 4 &pcfg_pull_default>;
582
+
};
583
+
584
+
rmii_pins: rmii-pins {
585
+
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
586
+
<2 RK_PB4 3 &pcfg_pull_default>,
587
+
<2 RK_PB5 3 &pcfg_pull_default>,
588
+
<2 RK_PB6 3 &pcfg_pull_default>,
589
+
<2 RK_PB7 3 &pcfg_pull_default>,
590
+
<2 RK_PC0 3 &pcfg_pull_default>,
591
+
<2 RK_PC1 3 &pcfg_pull_default>,
592
+
<2 RK_PC2 3 &pcfg_pull_default>,
593
+
<2 RK_PC3 3 &pcfg_pull_default>,
594
+
<2 RK_PD1 3 &pcfg_pull_default>;
595
+
};
596
+
};
597
+
598
+
hdmi {
599
+
hdmii2c_xfer: hdmii2c-xfer {
600
+
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
601
+
<0 RK_PA7 2 &pcfg_pull_none>;
602
+
};
603
+
604
+
hdmi_hpd: hdmi-hpd {
605
+
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
606
+
};
607
+
608
+
hdmi_cec: hdmi-cec {
609
+
rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
610
+
};
611
+
};
612
+
613
+
i2c0 {
614
+
i2c0_xfer: i2c0-xfer {
615
+
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
616
+
<0 RK_PA1 1 &pcfg_pull_none>;
617
+
};
618
+
};
619
+
620
+
i2c1 {
621
+
i2c1_xfer: i2c1-xfer {
622
+
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
623
+
<0 RK_PA3 1 &pcfg_pull_none>;
624
+
};
625
+
};
626
+
627
+
i2c2 {
628
+
i2c2_xfer: i2c2-xfer {
629
+
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
630
+
<2 RK_PC5 3 &pcfg_pull_none>;
631
+
};
632
+
};
633
+
634
+
i2c3 {
635
+
i2c3_xfer: i2c3-xfer {
636
+
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
637
+
<0 RK_PA7 1 &pcfg_pull_none>;
638
+
};
639
+
};
640
+
641
+
i2s {
642
+
i2s_bus: i2s-bus {
643
+
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
644
+
<0 RK_PB1 1 &pcfg_pull_none>,
645
+
<0 RK_PB3 1 &pcfg_pull_none>,
646
+
<0 RK_PB4 1 &pcfg_pull_none>,
647
+
<0 RK_PB5 1 &pcfg_pull_none>,
648
+
<0 RK_PB6 1 &pcfg_pull_none>;
649
+
};
650
+
651
+
i2s1_bus: i2s1-bus {
652
+
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
653
+
<1 RK_PA1 1 &pcfg_pull_none>,
654
+
<1 RK_PA2 1 &pcfg_pull_none>,
655
+
<1 RK_PA3 1 &pcfg_pull_none>,
656
+
<1 RK_PA4 1 &pcfg_pull_none>,
657
+
<1 RK_PA5 1 &pcfg_pull_none>;
658
+
};
659
+
};
660
+
661
+
lcdc {
662
+
lcdc_dclk: lcdc-dclk {
663
+
rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
664
+
};
665
+
666
+
lcdc_den: lcdc-den {
667
+
rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
668
+
};
669
+
670
+
lcdc_hsync: lcdc-hsync {
671
+
rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
672
+
};
673
+
674
+
lcdc_vsync: lcdc-vsync {
675
+
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
676
+
};
677
+
678
+
lcdc_rgb24: lcdc-rgb24 {
679
+
rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
680
+
<2 RK_PB5 1 &pcfg_pull_none>,
681
+
<2 RK_PB6 1 &pcfg_pull_none>,
682
+
<2 RK_PB7 1 &pcfg_pull_none>,
683
+
<2 RK_PC0 1 &pcfg_pull_none>,
684
+
<2 RK_PC1 1 &pcfg_pull_none>,
685
+
<2 RK_PC2 1 &pcfg_pull_none>,
686
+
<2 RK_PC3 1 &pcfg_pull_none>,
687
+
<2 RK_PC4 1 &pcfg_pull_none>,
688
+
<2 RK_PC5 1 &pcfg_pull_none>,
689
+
<2 RK_PC6 1 &pcfg_pull_none>,
690
+
<2 RK_PC7 1 &pcfg_pull_none>,
691
+
<2 RK_PD0 1 &pcfg_pull_none>,
692
+
<2 RK_PD1 1 &pcfg_pull_none>;
693
+
};
694
+
};
695
+
696
+
nfc {
697
+
flash_ale:flash-ale {
698
+
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
699
+
};
700
+
701
+
flash_cle:flash-cle {
702
+
rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
703
+
};
704
+
705
+
flash_wrn:flash-wrn {
706
+
rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
707
+
};
708
+
709
+
flash_rdn:flash-rdn {
710
+
rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
711
+
};
712
+
713
+
flash_rdy:flash-rdy {
714
+
rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
715
+
};
716
+
717
+
flash_cs0:flash-cs0 {
718
+
rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
719
+
};
720
+
721
+
flash_dqs:flash-dqs {
722
+
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
723
+
};
724
+
725
+
flash_bus8: flash-bus8 {
726
+
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
727
+
<1 RK_PD1 1 &pcfg_pull_none>,
728
+
<1 RK_PD2 1 &pcfg_pull_none>,
729
+
<1 RK_PD3 1 &pcfg_pull_none>,
730
+
<1 RK_PD4 1 &pcfg_pull_none>,
731
+
<1 RK_PD5 1 &pcfg_pull_none>,
732
+
<1 RK_PD6 1 &pcfg_pull_none>,
733
+
<1 RK_PD7 1 &pcfg_pull_none>;
734
+
};
735
+
};
736
+
737
+
pwm0 {
738
+
pwm0_pin: pwm0-pin {
739
+
rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
740
+
};
741
+
};
742
+
743
+
pwm1 {
744
+
pwm1_pin: pwm1-pin {
745
+
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
746
+
};
747
+
};
748
+
749
+
pwm2 {
750
+
pwm2_pin: pwm2-pin {
751
+
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
752
+
};
753
+
};
754
+
755
+
pwm3 {
756
+
pwm3_pin: pwm3-pin {
757
+
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
758
+
};
759
+
};
760
+
761
+
sdio {
762
+
sdio_clk: sdio-clk {
763
+
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
764
+
};
765
+
766
+
sdio_cmd: sdio-cmd {
767
+
rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
768
+
};
769
+
770
+
sdio_pwren: sdio-pwren {
771
+
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
772
+
};
773
+
774
+
sdio_bus4: sdio-bus4 {
775
+
rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
776
+
<1 RK_PA2 2 &pcfg_pull_default>,
777
+
<1 RK_PA4 2 &pcfg_pull_default>,
778
+
<1 RK_PA5 2 &pcfg_pull_default>;
779
+
};
780
+
};
781
+
782
+
sdmmc {
783
+
sdmmc_clk: sdmmc-clk {
784
+
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
785
+
};
786
+
787
+
sdmmc_cmd: sdmmc-cmd {
788
+
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
789
+
};
790
+
791
+
sdmmc_wp: sdmmc-wp {
792
+
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
793
+
};
794
+
795
+
sdmmc_pwren: sdmmc-pwren {
796
+
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
797
+
};
798
+
799
+
sdmmc_bus4: sdmmc-bus4 {
800
+
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
801
+
<1 RK_PC3 1 &pcfg_pull_default>,
802
+
<1 RK_PC4 1 &pcfg_pull_default>,
803
+
<1 RK_PC5 1 &pcfg_pull_default>;
804
+
};
805
+
};
806
+
807
+
spdif {
808
+
spdif_tx: spdif-tx {
809
+
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
810
+
};
811
+
};
812
+
813
+
spi0 {
814
+
spi0_clk: spi0-clk {
815
+
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
816
+
};
817
+
818
+
spi0_cs0: spi0-cs0 {
819
+
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
820
+
};
821
+
822
+
spi0_tx: spi0-tx {
823
+
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
824
+
};
825
+
826
+
spi0_rx: spi0-rx {
827
+
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
828
+
};
829
+
830
+
spi0_cs1: spi0-cs1 {
831
+
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
832
+
};
833
+
834
+
spi1_clk: spi1-clk {
835
+
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
836
+
};
837
+
838
+
spi1_cs0: spi1-cs0 {
839
+
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
840
+
};
841
+
842
+
spi1_tx: spi1-tx {
843
+
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
844
+
};
845
+
846
+
spi1_rx: spi1-rx {
847
+
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
848
+
};
849
+
850
+
spi1_cs1: spi1-cs1 {
851
+
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
852
+
};
853
+
854
+
spi2_clk: spi2-clk {
855
+
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
856
+
};
857
+
858
+
spi2_cs0: spi2-cs0 {
859
+
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
860
+
};
861
+
862
+
spi2_tx: spi2-tx {
863
+
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
864
+
};
865
+
866
+
spi2_rx: spi2-rx {
867
+
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
868
+
};
869
+
};
870
+
871
+
uart0 {
872
+
uart0_xfer: uart0-xfer {
873
+
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
874
+
<2 RK_PD3 2 &pcfg_pull_none>;
875
+
};
876
+
877
+
uart0_cts: uart0-cts {
878
+
rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
879
+
};
880
+
881
+
uart0_rts: uart0-rts {
882
+
rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
883
+
};
884
+
};
885
+
886
+
uart1 {
887
+
uart1_xfer: uart1-xfer {
888
+
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
889
+
<1 RK_PB2 2 &pcfg_pull_default>;
890
+
};
891
+
892
+
uart1_cts: uart1-cts {
893
+
rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
894
+
};
895
+
896
+
uart1_rts: uart1-rts {
897
+
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
898
+
};
899
+
};
900
+
901
+
uart2 {
902
+
uart2_xfer: uart2-xfer {
903
+
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
904
+
<1 RK_PC3 2 &pcfg_pull_none>;
905
+
};
906
+
907
+
uart2_cts: uart2-cts {
908
+
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
909
+
};
910
+
911
+
uart2_rts: uart2-rts {
912
+
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
913
+
};
914
+
};
915
+
};
916
+
};