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phy: rockchip: Add naneng combo phy support for RK3588

Add support for RK3588 combo phy

This is based on prior work from XiaoDong Huang and
Peter Geis fixing this issue specifically for Rockchip 356x.

Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Lucas Tanure and committed by
Vinod Koul a03c4427 c3becf9c

+184
+184
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
··· 63 63 #define PHYREG18 0x44 64 64 #define PHYREG18_PLL_LOOP 0x32 65 65 66 + #define PHYREG27 0x6C 67 + #define PHYREG27_RX_TRIM_RK3588 0x4C 68 + 66 69 #define PHYREG32 0x7C 67 70 #define PHYREG32_SSC_MASK GENMASK(7, 4) 68 71 #define PHYREG32_SSC_DIR_SHIFT 4 ··· 117 114 struct combphy_reg con2_for_sata; 118 115 struct combphy_reg con3_for_sata; 119 116 struct combphy_reg pipe_con0_for_sata; 117 + struct combphy_reg pipe_con1_for_sata; 120 118 struct combphy_reg pipe_xpcs_phy_ready; 119 + struct combphy_reg pipe_pcie1l0_sel; 120 + struct combphy_reg pipe_pcie1l1_sel; 121 121 }; 122 122 123 123 struct rockchip_combphy_cfg { ··· 565 559 .combphy_cfg = rk3568_combphy_cfg, 566 560 }; 567 561 562 + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 563 + { 564 + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 565 + unsigned long rate; 566 + u32 val; 567 + 568 + switch (priv->type) { 569 + case PHY_TYPE_PCIE: 570 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 571 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 572 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 573 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 574 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); 575 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); 576 + break; 577 + case PHY_TYPE_USB3: 578 + /* Set SSC downward spread spectrum */ 579 + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, 580 + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, 581 + PHYREG32); 582 + 583 + /* Enable adaptive CTLE for USB3.0 Rx. */ 584 + val = readl(priv->mmio + PHYREG15); 585 + val |= PHYREG15_CTLE_EN; 586 + writel(val, priv->mmio + PHYREG15); 587 + 588 + /* Set PLL KVCO fine tuning signals. */ 589 + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, 590 + PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, 591 + PHYREG33); 592 + 593 + /* Enable controlling random jitter. */ 594 + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); 595 + 596 + /* Set PLL input clock divider 1/2. */ 597 + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, 598 + PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, 599 + PHYREG6); 600 + 601 + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); 602 + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); 603 + 604 + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 605 + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 606 + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 607 + break; 608 + case PHY_TYPE_SATA: 609 + /* Enable adaptive CTLE for SATA Rx. */ 610 + val = readl(priv->mmio + PHYREG15); 611 + val |= PHYREG15_CTLE_EN; 612 + writel(val, priv->mmio + PHYREG15); 613 + /* 614 + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 615 + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 616 + */ 617 + val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; 618 + val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; 619 + writel(val, priv->mmio + PHYREG7); 620 + 621 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 622 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 623 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 624 + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 625 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 626 + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); 627 + break; 628 + case PHY_TYPE_SGMII: 629 + case PHY_TYPE_QSGMII: 630 + default: 631 + dev_err(priv->dev, "incompatible PHY type\n"); 632 + return -EINVAL; 633 + } 634 + 635 + rate = clk_get_rate(priv->refclk); 636 + 637 + switch (rate) { 638 + case REF_CLOCK_24MHz: 639 + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 640 + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 641 + val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; 642 + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, 643 + val, PHYREG15); 644 + 645 + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); 646 + } 647 + break; 648 + 649 + case REF_CLOCK_25MHz: 650 + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 651 + break; 652 + case REF_CLOCK_100MHz: 653 + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 654 + if (priv->type == PHY_TYPE_PCIE) { 655 + /* PLL KVCO fine tuning. */ 656 + val = 4 << PHYREG33_PLL_KVCO_SHIFT; 657 + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, 658 + val, PHYREG33); 659 + 660 + /* Enable controlling random jitter. */ 661 + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); 662 + 663 + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ 664 + writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); 665 + 666 + /* Set up su_trim: */ 667 + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); 668 + } else if (priv->type == PHY_TYPE_SATA) { 669 + /* downward spread spectrum +500ppm */ 670 + val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; 671 + val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; 672 + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); 673 + } 674 + break; 675 + default: 676 + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); 677 + return -EINVAL; 678 + } 679 + 680 + if (priv->ext_refclk) { 681 + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 682 + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 683 + val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; 684 + val |= PHYREG13_CKRCV_AMP0; 685 + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); 686 + 687 + val = readl(priv->mmio + PHYREG14); 688 + val |= PHYREG14_CKRCV_AMP1; 689 + writel(val, priv->mmio + PHYREG14); 690 + } 691 + } 692 + 693 + if (priv->enable_ssc) { 694 + val = readl(priv->mmio + PHYREG8); 695 + val |= PHYREG8_SSC_EN; 696 + writel(val, priv->mmio + PHYREG8); 697 + } 698 + 699 + return 0; 700 + } 701 + 702 + static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 703 + /* pipe-phy-grf */ 704 + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 705 + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 706 + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 707 + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 708 + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 709 + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 710 + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 711 + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 712 + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 713 + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 714 + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 715 + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 716 + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 717 + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 718 + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 719 + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 720 + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, 721 + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, 722 + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, 723 + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, 724 + /* pipe-grf */ 725 + .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, 726 + .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, 727 + .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, 728 + .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, 729 + }; 730 + 731 + static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { 732 + .grfcfg = &rk3588_combphy_grfcfgs, 733 + .combphy_cfg = rk3588_combphy_cfg, 734 + }; 735 + 568 736 static const struct of_device_id rockchip_combphy_of_match[] = { 569 737 { 570 738 .compatible = "rockchip,rk3568-naneng-combphy", 571 739 .data = &rk3568_combphy_cfgs, 740 + }, 741 + { 742 + .compatible = "rockchip,rk3588-naneng-combphy", 743 + .data = &rk3588_combphy_cfgs, 572 744 }, 573 745 { }, 574 746 };