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spi: tegra114: Preserve SPI mode bits in def_command1_reg

The COMMAND1 register bits [29:28] set the SPI mode, which controls
the clock idle level. When a transfer ends, tegra_spi_transfer_end()
writes def_command1_reg back to restore the default state, but this
register value currently lacks the mode bits. This results in the
clock always being configured as idle low, breaking devices that
need it high.

Fix this by storing the mode bits in def_command1_reg during setup,
to prevent this field from always being cleared.

Fixes: f333a331adfa ("spi/tegra114: add spi driver")
Signed-off-by: Vishwaroop A <va@nvidia.com>
Link: https://patch.msgid.link/20260204141212.1540382-1-va@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Vishwaroop A and committed by
Mark Brown a0a75b40 41d9a679

+3
+3
drivers/spi/spi-tegra114.c
··· 978 978 if (spi_get_csgpiod(spi, 0)) 979 979 gpiod_set_value(spi_get_csgpiod(spi, 0), 0); 980 980 981 + /* Update default register to include CS polarity and SPI mode */ 981 982 val = tspi->def_command1_reg; 982 983 if (spi->mode & SPI_CS_HIGH) 983 984 val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); 984 985 else 985 986 val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); 987 + val &= ~SPI_CONTROL_MODE_MASK; 988 + val |= SPI_MODE_SEL(spi->mode & 0x3); 986 989 tspi->def_command1_reg = val; 987 990 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); 988 991 spin_unlock_irqrestore(&tspi->lock, flags);