tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-12-20' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"rc2 fixes for the week, mostly xe, with amdgpu as usual. Then a
smattering of small fixes across the core/tests/panel and amdxdna.

I expect things will be quiet for rc3/4 as teams take a break, and I'm
travelling but will keep an eye on things.

core:
- fix gem handle leak on DRM_IOCTL_GEM_CHANGE_HANDLE

tests:
- add EDEADLK handling

amdgpu:
- Fix no_console_suspend handling
- DCN 3.5.x seamless boot fixes
- DP audio fix
- Fix race in GPU recovery
- SMU 14 OD fix

amdkfd:
- Event fix

xe:
- Limit num_syncs to prevent oversized kernel allocations
- Disallow 0 OA property values
- Disallow 0 EU stall property values
- Fix kobject leak
- Workaround
- Loop variable reference fix
- Fix a CONFIG corner-case incorrect number of argument
- Skip reason prefix while emitting array
- VF migration fix
- Fix context in mei interrupt top half
- Don't include the CCS metadata in the dma-buf sg-table
- VF queueing recovery work fix
- Increase TDF timeout
- GT reset registers vs scheduler ordering fix
- Adjust long-running workload timeslices
- Always set OA_OAGLBCTXCTRL_COUNTER_RESUME
- Fix a return value
- Drop preempt-fences when destroying imported dma-bufs
- Use usleep_range for accurate long-running workload timeslicing

amdxdna:
- don't load virtualized

panel:
- fix visionox-rm69299 Kconfig dependency
- sony-td4353-jdi probing fix"

* tag 'drm-fixes-2025-12-20' of https://gitlab.freedesktop.org/drm/kernel: (34 commits)
drm/xe: Use usleep_range for accurate long-running workload timeslicing
drm/xe: Drop preempt-fences when destroying imported dma-bufs.
drm/xe/eustall: Disallow 0 EU stall property values
drm/xe/oa: Disallow 0 OA property values
drm/xe/xe_sriov_vfio: Fix return value in xe_sriov_vfio_migration_supported()
drm/xe/oa: Always set OAG_OAGLBCTXCTRL_COUNTER_RESUME
drm/xe: Adjust long-running workload timeslices to reasonable values
drm/xe/oa: Limit num_syncs to prevent oversized allocations
drm/xe: Limit num_syncs to prevent oversized allocations
drm/amdkfd: Fix improper NULL termination of queue restore SMI event string
drm/amd/pm: restore SCLK settings after S0ix resume
drm/amdgpu: fix a job->pasid access race in gpu recovery
drm/amd/display: Fix DP no audio issue
drm/amd/display: Fix scratch registers offsets for DCN351
drm/amd/display: Fix scratch registers offsets for DCN35
drm/amd: Resume the device in thaw() callback when console suspend is disabled
drm/panel: visionox-rm69299: Depend on BACKLIGHT_CLASS_DEVICE
accel/amdxdna: Block running under a hypervisor
drm/panel: sony-td4353-jdi: Enable prepare_prev_first
drm/xe: Restore engine registers before restarting schedulers after GT reset
...

Linus Torvalds a0bdd554 fa084c35

+331 -74
+6
drivers/accel/amdxdna/aie2_pci.c
··· 17 17 #include <linux/iopoll.h> 18 18 #include <linux/pci.h> 19 19 #include <linux/xarray.h> 20 + #include <asm/hypervisor.h> 20 21 21 22 #include "aie2_msg_priv.h" 22 23 #include "aie2_pci.h" ··· 508 507 const struct firmware *fw; 509 508 unsigned long bars = 0; 510 509 int i, nvec, ret; 510 + 511 + if (!hypervisor_is_type(X86_HYPER_NATIVE)) { 512 + XDNA_ERR(xdna, "Running under hypervisor not supported"); 513 + return -EINVAL; 514 + } 511 515 512 516 ndev = drmm_kzalloc(&xdna->ddev, sizeof(*ndev), GFP_KERNEL); 513 517 if (!ndev)
+8 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 6613 6613 struct amdgpu_hive_info *hive = NULL; 6614 6614 int r = 0; 6615 6615 bool need_emergency_restart = false; 6616 + /* save the pasid here as the job may be freed before the end of the reset */ 6617 + int pasid = job ? job->pasid : -EINVAL; 6616 6618 6617 6619 /* 6618 6620 * If it reaches here because of hang/timeout and a RAS error is ··· 6715 6713 if (!r) { 6716 6714 struct amdgpu_task_info *ti = NULL; 6717 6715 6718 - if (job) 6719 - ti = amdgpu_vm_get_task_info_pasid(adev, job->pasid); 6716 + /* 6717 + * The job may already be freed at this point via the sched tdr workqueue so 6718 + * use the cached pasid. 6719 + */ 6720 + if (pasid >= 0) 6721 + ti = amdgpu_vm_get_task_info_pasid(adev, pasid); 6720 6722 6721 6723 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, 6722 6724 ti ? &ti->task : NULL);
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 33 33 #include <drm/drm_vblank.h> 34 34 35 35 #include <linux/cc_platform.h> 36 + #include <linux/console.h> 36 37 #include <linux/dynamic_debug.h> 37 38 #include <linux/module.h> 38 39 #include <linux/mmu_notifier.h> ··· 2705 2704 struct drm_device *drm_dev = dev_get_drvdata(dev); 2706 2705 2707 2706 /* do not resume device if it's normal hibernation */ 2708 - if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) 2707 + if (console_suspend_enabled && 2708 + !pm_hibernate_is_recovering() && 2709 + !pm_hibernation_mode_is_suspend()) 2709 2710 return 0; 2710 2711 2711 2712 return amdgpu_device_resume(drm_dev, true);
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
··· 312 312 { 313 313 kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_RESTORE, 314 314 KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(), pid, 315 - node->id, 0)); 315 + node->id, '0')); 316 316 } 317 317 318 318 void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm)
+4 -4
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
··· 1118 1118 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1119 1119 num_audio++; 1120 1120 } 1121 + if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) { 1122 + /*wake AZ from D3 first before access az endpoint*/ 1123 + clk_mgr->funcs->enable_pme_wa(clk_mgr); 1124 + } 1121 1125 1122 1126 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1123 - 1124 - if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) 1125 - /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1126 - clk_mgr->funcs->enable_pme_wa(clk_mgr); 1127 1127 1128 1128 link_hwss->enable_audio_packet(pipe_ctx); 1129 1129
+4 -4
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
··· 203 203 NBIO_BASE_INNER(seg) 204 204 205 205 #define NBIO_SR(reg_name)\ 206 - REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 207 - regBIF_BX2_ ## reg_name 206 + REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 207 + regBIF_BX1_ ## reg_name 208 208 209 209 #define NBIO_SR_ARR(reg_name, id)\ 210 - REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 211 - regBIF_BX2_ ## reg_name 210 + REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 211 + regBIF_BX1_ ## reg_name 212 212 213 213 #define bios_regs_init() \ 214 214 ( \
+4 -4
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
··· 183 183 NBIO_BASE_INNER(seg) 184 184 185 185 #define NBIO_SR(reg_name)\ 186 - REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 187 - regBIF_BX2_ ## reg_name 186 + REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 187 + regBIF_BX1_ ## reg_name 188 188 189 189 #define NBIO_SR_ARR(reg_name, id)\ 190 - REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \ 191 - regBIF_BX2_ ## reg_name 190 + REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \ 191 + regBIF_BX1_ ## reg_name 192 192 193 193 #define bios_regs_init() \ 194 194 ( \
+5
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
··· 1939 1939 dev_err(smu->adev->dev, "Set soft max sclk failed!"); 1940 1940 return ret; 1941 1941 } 1942 + if (smu->gfx_actual_hard_min_freq != smu->gfx_default_hard_min_freq || 1943 + smu->gfx_actual_soft_max_freq != smu->gfx_default_soft_max_freq) 1944 + smu->user_dpm_profile.user_od = true; 1945 + else 1946 + smu->user_dpm_profile.user_od = false; 1942 1947 break; 1943 1948 default: 1944 1949 return -ENOSYS;
+32 -5
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
··· 1514 1514 1515 1515 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1516 1516 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1517 - smu->gfx_actual_hard_min_freq = 0; 1518 - smu->gfx_actual_soft_max_freq = 0; 1519 - 1517 + if (smu->gfx_actual_hard_min_freq == 0) 1518 + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1519 + if (smu->gfx_actual_soft_max_freq == 0) 1520 + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1520 1521 return 0; 1521 1522 } 1522 1523 ··· 1527 1526 1528 1527 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1529 1528 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1530 - smu->gfx_actual_hard_min_freq = 0; 1531 - smu->gfx_actual_soft_max_freq = 0; 1529 + if (smu->gfx_actual_hard_min_freq == 0) 1530 + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; 1531 + if (smu->gfx_actual_soft_max_freq == 0) 1532 + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; 1532 1533 1533 1534 return 0; 1534 1535 } ··· 1668 1665 return ret; 1669 1666 } 1670 1667 1668 + static int smu_v14_0_0_restore_user_od_settings(struct smu_context *smu) 1669 + { 1670 + int ret; 1671 + 1672 + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, 1673 + smu->gfx_actual_hard_min_freq, 1674 + NULL); 1675 + if (ret) { 1676 + dev_err(smu->adev->dev, "Failed to restore hard min sclk!\n"); 1677 + return ret; 1678 + } 1679 + 1680 + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, 1681 + smu->gfx_actual_soft_max_freq, 1682 + NULL); 1683 + if (ret) { 1684 + dev_err(smu->adev->dev, "Failed to restore soft max sclk!\n"); 1685 + return ret; 1686 + } 1687 + 1688 + return 0; 1689 + } 1690 + 1671 1691 static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { 1672 1692 .check_fw_status = smu_v14_0_check_fw_status, 1673 1693 .check_fw_version = smu_v14_0_check_fw_version, ··· 1714 1688 .mode2_reset = smu_v14_0_0_mode2_reset, 1715 1689 .get_dpm_ultimate_freq = smu_v14_0_common_get_dpm_ultimate_freq, 1716 1690 .set_soft_freq_limited_range = smu_v14_0_0_set_soft_freq_limited_range, 1691 + .restore_user_od_settings = smu_v14_0_0_restore_user_od_settings, 1717 1692 .od_edit_dpm_table = smu_v14_0_od_edit_dpm_table, 1718 1693 .print_clk_levels = smu_v14_0_0_print_clk_levels, 1719 1694 .force_clk_levels = smu_v14_0_0_force_clk_levels,
+6 -2
drivers/gpu/drm/drm_gem.c
··· 969 969 if (!obj) 970 970 return -ENOENT; 971 971 972 - if (args->handle == args->new_handle) 973 - return 0; 972 + if (args->handle == args->new_handle) { 973 + ret = 0; 974 + goto out; 975 + } 974 976 975 977 mutex_lock(&file_priv->prime.lock); 976 978 ··· 1004 1002 1005 1003 out_unlock: 1006 1004 mutex_unlock(&file_priv->prime.lock); 1005 + out: 1006 + drm_gem_object_put(obj); 1007 1007 1008 1008 return ret; 1009 1009 }
+1
drivers/gpu/drm/panel/Kconfig
··· 1165 1165 tristate "Visionox RM69299" 1166 1166 depends on OF 1167 1167 depends on DRM_MIPI_DSI 1168 + depends on BACKLIGHT_CLASS_DEVICE 1168 1169 help 1169 1170 Say Y here if you want to enable support for Visionox 1170 1171 RM69299 DSI Video Mode panel.
+2
drivers/gpu/drm/panel/panel-sony-td4353-jdi.c
··· 212 212 if (ret) 213 213 return dev_err_probe(dev, ret, "Failed to get backlight\n"); 214 214 215 + ctx->panel.prepare_prev_first = true; 216 + 215 217 drm_panel_add(&ctx->panel); 216 218 217 219 ret = mipi_dsi_attach(dsi);
+35 -5
drivers/gpu/drm/tests/drm_atomic_state_test.c
··· 156 156 157 157 if (connector) { 158 158 conn_state = drm_atomic_get_connector_state(state, connector); 159 - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, conn_state); 159 + if (IS_ERR(conn_state)) 160 + return PTR_ERR(conn_state); 160 161 161 162 ret = drm_atomic_set_crtc_for_connector(conn_state, crtc); 162 - KUNIT_EXPECT_EQ(test, ret, 0); 163 + if (ret) 164 + return ret; 163 165 } 164 166 165 167 crtc_state = drm_atomic_get_crtc_state(state, crtc); 166 - KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state); 168 + if (IS_ERR(crtc_state)) 169 + return PTR_ERR(crtc_state); 167 170 168 171 ret = drm_atomic_set_mode_for_crtc(crtc_state, &drm_atomic_test_mode); 169 - KUNIT_EXPECT_EQ(test, ret, 0); 172 + if (ret) 173 + return ret; 170 174 171 175 crtc_state->enable = true; 172 176 crtc_state->active = true; 173 177 174 178 if (connector) { 175 179 ret = drm_atomic_commit(state); 176 - KUNIT_ASSERT_EQ(test, ret, 0); 180 + if (ret) 181 + return ret; 177 182 } else { 178 183 // dummy connector mask 179 184 crtc_state->connector_mask = DRM_TEST_CONN_0; ··· 211 206 drm_modeset_acquire_init(&ctx, 0); 212 207 213 208 // first modeset to enable 209 + retry_set_up: 214 210 ret = set_up_atomic_state(test, priv, old_conn, &ctx); 211 + if (ret == -EDEADLK) { 212 + ret = drm_modeset_backoff(&ctx); 213 + if (!ret) 214 + goto retry_set_up; 215 + } 215 216 KUNIT_ASSERT_EQ(test, ret, 0); 216 217 217 218 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 288 277 289 278 drm_modeset_acquire_init(&ctx, 0); 290 279 280 + retry_set_up: 291 281 ret = set_up_atomic_state(test, priv, NULL, &ctx); 282 + if (ret == -EDEADLK) { 283 + ret = drm_modeset_backoff(&ctx); 284 + if (!ret) 285 + goto retry_set_up; 286 + } 292 287 KUNIT_ASSERT_EQ(test, ret, 0); 293 288 294 289 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); 295 290 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, state); 296 291 292 + retry: 297 293 crtc_state = drm_atomic_get_crtc_state(state, priv->crtc); 294 + if (PTR_ERR(crtc_state) == -EDEADLK) { 295 + drm_atomic_state_clear(state); 296 + ret = drm_modeset_backoff(&ctx); 297 + if (!ret) 298 + goto retry; 299 + } 298 300 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, crtc_state); 299 301 300 302 crtc_state->encoder_mask = param->encoder_mask; ··· 316 292 crtc_state->mode_changed = true; 317 293 318 294 ret = drm_atomic_helper_check_modeset(drm, state); 295 + if (ret == -EDEADLK) { 296 + drm_atomic_state_clear(state); 297 + ret = drm_modeset_backoff(&ctx); 298 + if (!ret) 299 + goto retry; 300 + } 319 301 KUNIT_ASSERT_EQ(test, ret, param->expected_result); 320 302 321 303 drm_modeset_drop_locks(&ctx);
+143
drivers/gpu/drm/tests/drm_hdmi_state_helper_test.c
··· 257 257 258 258 drm_modeset_acquire_init(&ctx, 0); 259 259 260 + retry_conn_enable: 260 261 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 261 262 crtc, conn, 262 263 preferred, 263 264 &ctx); 265 + if (ret == -EDEADLK) { 266 + ret = drm_modeset_backoff(&ctx); 267 + if (!ret) 268 + goto retry_conn_enable; 269 + } 264 270 KUNIT_ASSERT_EQ(test, ret, 0); 265 271 266 272 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 332 326 333 327 drm_modeset_acquire_init(&ctx, 0); 334 328 329 + retry_conn_enable: 335 330 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 336 331 crtc, conn, 337 332 preferred, 338 333 &ctx); 334 + if (ret == -EDEADLK) { 335 + ret = drm_modeset_backoff(&ctx); 336 + if (!ret) 337 + goto retry_conn_enable; 338 + } 339 339 KUNIT_ASSERT_EQ(test, ret, 0); 340 340 341 341 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 409 397 410 398 drm_modeset_acquire_init(&ctx, 0); 411 399 400 + retry_conn_enable: 412 401 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 413 402 crtc, conn, 414 403 preferred, 415 404 &ctx); 405 + if (ret == -EDEADLK) { 406 + ret = drm_modeset_backoff(&ctx); 407 + if (!ret) 408 + goto retry_conn_enable; 409 + } 416 410 KUNIT_ASSERT_EQ(test, ret, 0); 417 411 418 412 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 475 457 KUNIT_ASSERT_NOT_NULL(test, mode); 476 458 477 459 crtc = priv->crtc; 460 + 461 + retry_conn_enable: 478 462 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 479 463 crtc, conn, 480 464 mode, 481 465 &ctx); 466 + if (ret == -EDEADLK) { 467 + ret = drm_modeset_backoff(&ctx); 468 + if (!ret) 469 + goto retry_conn_enable; 470 + } 482 471 KUNIT_ASSERT_EQ(test, ret, 0); 483 472 484 473 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 543 518 544 519 drm_modeset_acquire_init(&ctx, 0); 545 520 521 + retry_conn_enable: 546 522 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 547 523 crtc, conn, 548 524 preferred, 549 525 &ctx); 526 + if (ret == -EDEADLK) { 527 + ret = drm_modeset_backoff(&ctx); 528 + if (!ret) 529 + goto retry_conn_enable; 530 + } 550 531 KUNIT_ASSERT_EQ(test, ret, 0); 551 532 552 533 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 611 580 KUNIT_ASSERT_NOT_NULL(test, mode); 612 581 613 582 crtc = priv->crtc; 583 + 584 + retry_conn_enable: 614 585 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 615 586 crtc, conn, 616 587 mode, 617 588 &ctx); 589 + if (ret == -EDEADLK) { 590 + ret = drm_modeset_backoff(&ctx); 591 + if (!ret) 592 + goto retry_conn_enable; 593 + } 618 594 KUNIT_ASSERT_EQ(test, ret, 0); 619 595 620 596 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 681 643 682 644 drm_modeset_acquire_init(&ctx, 0); 683 645 646 + retry_conn_enable: 684 647 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 685 648 crtc, conn, 686 649 preferred, 687 650 &ctx); 651 + if (ret == -EDEADLK) { 652 + ret = drm_modeset_backoff(&ctx); 653 + if (!ret) 654 + goto retry_conn_enable; 655 + } 688 656 KUNIT_ASSERT_EQ(test, ret, 0); 689 657 690 658 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 749 705 KUNIT_ASSERT_NOT_NULL(test, mode); 750 706 751 707 crtc = priv->crtc; 708 + 709 + retry_conn_enable: 752 710 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 753 711 crtc, conn, 754 712 mode, 755 713 &ctx); 714 + if (ret == -EDEADLK) { 715 + ret = drm_modeset_backoff(&ctx); 716 + if (!ret) 717 + goto retry_conn_enable; 718 + } 756 719 KUNIT_ASSERT_EQ(test, ret, 0); 757 720 758 721 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 921 870 922 871 drm_modeset_acquire_init(&ctx, 0); 923 872 873 + retry_conn_enable: 924 874 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 925 875 crtc, conn, 926 876 preferred, 927 877 &ctx); 878 + if (ret == -EDEADLK) { 879 + ret = drm_modeset_backoff(&ctx); 880 + if (!ret) 881 + goto retry_conn_enable; 882 + } 928 883 KUNIT_ASSERT_EQ(test, ret, 0); 929 884 930 885 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 1003 946 1004 947 drm_modeset_acquire_init(&ctx, 0); 1005 948 949 + retry_conn_enable: 1006 950 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1007 951 crtc, conn, 1008 952 preferred, 1009 953 &ctx); 954 + if (ret == -EDEADLK) { 955 + ret = drm_modeset_backoff(&ctx); 956 + if (!ret) 957 + goto retry_conn_enable; 958 + } 1010 959 KUNIT_ASSERT_EQ(test, ret, 0); 1011 960 1012 961 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx); ··· 1085 1022 1086 1023 drm_modeset_acquire_init(&ctx, 0); 1087 1024 1025 + retry_conn_enable: 1088 1026 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1089 1027 crtc, conn, 1090 1028 preferred, 1091 1029 &ctx); 1030 + if (ret == -EDEADLK) { 1031 + ret = drm_modeset_backoff(&ctx); 1032 + if (!ret) 1033 + goto retry_conn_enable; 1034 + } 1092 1035 KUNIT_ASSERT_EQ(test, ret, 0); 1093 1036 1094 1037 conn_state = conn->state; ··· 1138 1069 1139 1070 drm_modeset_acquire_init(&ctx, 0); 1140 1071 1072 + retry_conn_enable: 1141 1073 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1142 1074 crtc, conn, 1143 1075 preferred, 1144 1076 &ctx); 1077 + if (ret == -EDEADLK) { 1078 + ret = drm_modeset_backoff(&ctx); 1079 + if (!ret) 1080 + goto retry_conn_enable; 1081 + } 1145 1082 KUNIT_ASSERT_EQ(test, ret, 0); 1146 1083 1147 1084 conn_state = conn->state; ··· 1193 1118 1194 1119 drm_modeset_acquire_init(&ctx, 0); 1195 1120 1121 + retry_conn_enable: 1196 1122 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1197 1123 crtc, conn, 1198 1124 preferred, 1199 1125 &ctx); 1126 + if (ret == -EDEADLK) { 1127 + ret = drm_modeset_backoff(&ctx); 1128 + if (!ret) 1129 + goto retry_conn_enable; 1130 + } 1200 1131 KUNIT_ASSERT_EQ(test, ret, 0); 1201 1132 1202 1133 conn_state = conn->state; ··· 1248 1167 1249 1168 drm_modeset_acquire_init(&ctx, 0); 1250 1169 1170 + retry_conn_enable: 1251 1171 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1252 1172 crtc, conn, 1253 1173 preferred, 1254 1174 &ctx); 1175 + if (ret == -EDEADLK) { 1176 + ret = drm_modeset_backoff(&ctx); 1177 + if (!ret) 1178 + goto retry_conn_enable; 1179 + } 1255 1180 KUNIT_ASSERT_EQ(test, ret, 0); 1256 1181 1257 1182 conn_state = conn->state; ··· 1305 1218 1306 1219 drm_modeset_acquire_init(&ctx, 0); 1307 1220 1221 + retry_conn_enable: 1308 1222 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1309 1223 crtc, conn, 1310 1224 preferred, 1311 1225 &ctx); 1226 + if (ret == -EDEADLK) { 1227 + ret = drm_modeset_backoff(&ctx); 1228 + if (!ret) 1229 + goto retry_conn_enable; 1230 + } 1312 1231 KUNIT_ASSERT_EQ(test, ret, 0); 1313 1232 1314 1233 /* You shouldn't be doing that at home. */ ··· 1385 1292 1386 1293 drm_modeset_acquire_init(&ctx, 0); 1387 1294 1295 + retry_conn_enable: 1388 1296 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1389 1297 crtc, conn, 1390 1298 preferred, 1391 1299 &ctx); 1300 + if (ret == -EDEADLK) { 1301 + ret = drm_modeset_backoff(&ctx); 1302 + if (!ret) 1303 + goto retry_conn_enable; 1304 + } 1392 1305 KUNIT_EXPECT_EQ(test, ret, 0); 1393 1306 1394 1307 conn_state = conn->state; ··· 1539 1440 1540 1441 drm_modeset_acquire_init(&ctx, 0); 1541 1442 1443 + retry_conn_enable: 1542 1444 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1543 1445 crtc, conn, 1544 1446 preferred, 1545 1447 &ctx); 1448 + if (ret == -EDEADLK) { 1449 + ret = drm_modeset_backoff(&ctx); 1450 + if (!ret) 1451 + goto retry_conn_enable; 1452 + } 1546 1453 KUNIT_EXPECT_EQ(test, ret, 0); 1547 1454 1548 1455 conn_state = conn->state; ··· 1774 1669 drm_modeset_acquire_init(&ctx, 0); 1775 1670 1776 1671 crtc = priv->crtc; 1672 + 1673 + retry_conn_enable: 1777 1674 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1778 1675 crtc, conn, 1779 1676 mode, 1780 1677 &ctx); 1678 + if (ret == -EDEADLK) { 1679 + ret = drm_modeset_backoff(&ctx); 1680 + if (!ret) 1681 + goto retry_conn_enable; 1682 + } 1781 1683 KUNIT_EXPECT_EQ(test, ret, 0); 1782 1684 1783 1685 conn_state = conn->state; ··· 1848 1736 1849 1737 drm_modeset_acquire_init(&ctx, 0); 1850 1738 1739 + retry_conn_enable: 1851 1740 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1852 1741 crtc, conn, 1853 1742 preferred, 1854 1743 &ctx); 1744 + if (ret == -EDEADLK) { 1745 + ret = drm_modeset_backoff(&ctx); 1746 + if (!ret) 1747 + goto retry_conn_enable; 1748 + } 1855 1749 KUNIT_EXPECT_EQ(test, ret, 0); 1856 1750 1857 1751 conn_state = conn->state; ··· 1923 1805 1924 1806 drm_modeset_acquire_init(&ctx, 0); 1925 1807 1808 + retry_conn_enable: 1926 1809 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1927 1810 crtc, conn, 1928 1811 preferred, 1929 1812 &ctx); 1813 + if (ret == -EDEADLK) { 1814 + ret = drm_modeset_backoff(&ctx); 1815 + if (!ret) 1816 + goto retry_conn_enable; 1817 + } 1930 1818 KUNIT_EXPECT_EQ(test, ret, 0); 1931 1819 1932 1820 conn_state = conn->state; ··· 1989 1865 1990 1866 drm_modeset_acquire_init(&ctx, 0); 1991 1867 1868 + retry_conn_enable: 1992 1869 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 1993 1870 crtc, conn, 1994 1871 preferred, 1995 1872 &ctx); 1873 + if (ret == -EDEADLK) { 1874 + ret = drm_modeset_backoff(&ctx); 1875 + if (!ret) 1876 + goto retry_conn_enable; 1877 + } 1996 1878 KUNIT_EXPECT_EQ(test, ret, 0); 1997 1879 1998 1880 conn_state = conn->state; ··· 2057 1927 2058 1928 drm_modeset_acquire_init(&ctx, 0); 2059 1929 1930 + retry_conn_enable: 2060 1931 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 2061 1932 crtc, conn, 2062 1933 preferred, 2063 1934 &ctx); 1935 + if (ret == -EDEADLK) { 1936 + ret = drm_modeset_backoff(&ctx); 1937 + if (!ret) 1938 + goto retry_conn_enable; 1939 + } 2064 1940 KUNIT_EXPECT_EQ(test, ret, 0); 2065 1941 2066 1942 conn_state = conn->state; ··· 2106 1970 2107 1971 drm = &priv->drm; 2108 1972 crtc = priv->crtc; 1973 + 1974 + retry_conn_enable: 2109 1975 ret = drm_kunit_helper_enable_crtc_connector(test, drm, 2110 1976 crtc, conn, 2111 1977 preferred, 2112 1978 &ctx); 1979 + if (ret == -EDEADLK) { 1980 + ret = drm_modeset_backoff(&ctx); 1981 + if (!ret) 1982 + goto retry_conn_enable; 1983 + } 2113 1984 KUNIT_ASSERT_EQ(test, ret, 0); 2114 1985 2115 1986 state = drm_kunit_helper_atomic_state_alloc(test, drm, &ctx);
+4 -11
drivers/gpu/drm/xe/xe_bo.c
··· 1527 1527 * always succeed here, as long as we hold the lru lock. 1528 1528 */ 1529 1529 spin_lock(&ttm_bo->bdev->lru_lock); 1530 - locked = dma_resv_trylock(ttm_bo->base.resv); 1530 + locked = dma_resv_trylock(&ttm_bo->base._resv); 1531 1531 spin_unlock(&ttm_bo->bdev->lru_lock); 1532 1532 xe_assert(xe, locked); 1533 1533 ··· 1547 1547 bo = ttm_to_xe_bo(ttm_bo); 1548 1548 xe_assert(xe_bo_device(bo), !(bo->created && kref_read(&ttm_bo->base.refcount))); 1549 1549 1550 - /* 1551 - * Corner case where TTM fails to allocate memory and this BOs resv 1552 - * still points the VMs resv 1553 - */ 1554 - if (ttm_bo->base.resv != &ttm_bo->base._resv) 1555 - return; 1556 - 1557 1550 if (!xe_ttm_bo_lock_in_destructor(ttm_bo)) 1558 1551 return; 1559 1552 ··· 1556 1563 * TODO: Don't do this for external bos once we scrub them after 1557 1564 * unbind. 1558 1565 */ 1559 - dma_resv_for_each_fence(&cursor, ttm_bo->base.resv, 1566 + dma_resv_for_each_fence(&cursor, &ttm_bo->base._resv, 1560 1567 DMA_RESV_USAGE_BOOKKEEP, fence) { 1561 1568 if (xe_fence_is_xe_preempt(fence) && 1562 1569 !dma_fence_is_signaled(fence)) { 1563 1570 if (!replacement) 1564 1571 replacement = dma_fence_get_stub(); 1565 1572 1566 - dma_resv_replace_fences(ttm_bo->base.resv, 1573 + dma_resv_replace_fences(&ttm_bo->base._resv, 1567 1574 fence->context, 1568 1575 replacement, 1569 1576 DMA_RESV_USAGE_BOOKKEEP); ··· 1571 1578 } 1572 1579 dma_fence_put(replacement); 1573 1580 1574 - dma_resv_unlock(ttm_bo->base.resv); 1581 + dma_resv_unlock(&ttm_bo->base._resv); 1575 1582 } 1576 1583 1577 1584 static void xe_ttm_bo_delete_mem_notify(struct ttm_buffer_object *ttm_bo)
+1 -1
drivers/gpu/drm/xe/xe_device.c
··· 1056 1056 * transient and need to be flushed.. 1057 1057 */ 1058 1058 if (xe_mmio_wait32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, 1059 - 150, NULL, false)) 1059 + 300, NULL, false)) 1060 1060 xe_gt_err_once(gt, "TD flush timeout\n"); 1061 1061 1062 1062 xe_force_wake_put(gt_to_fw(gt), fw_ref);
+1 -1
drivers/gpu/drm/xe/xe_dma_buf.c
··· 124 124 case XE_PL_TT: 125 125 sgt = drm_prime_pages_to_sg(obj->dev, 126 126 bo->ttm.ttm->pages, 127 - bo->ttm.ttm->num_pages); 127 + obj->size >> PAGE_SHIFT); 128 128 if (IS_ERR(sgt)) 129 129 return sgt; 130 130
+1 -1
drivers/gpu/drm/xe/xe_eu_stall.c
··· 315 315 return -EFAULT; 316 316 317 317 if (XE_IOCTL_DBG(xe, ext.property >= ARRAY_SIZE(xe_set_eu_stall_property_funcs)) || 318 - XE_IOCTL_DBG(xe, ext.pad)) 318 + XE_IOCTL_DBG(xe, !ext.property) || XE_IOCTL_DBG(xe, ext.pad)) 319 319 return -EINVAL; 320 320 321 321 idx = array_index_nospec(ext.property, ARRAY_SIZE(xe_set_eu_stall_property_funcs));
+2 -1
drivers/gpu/drm/xe/xe_exec.c
··· 132 132 133 133 if (XE_IOCTL_DBG(xe, args->extensions) || 134 134 XE_IOCTL_DBG(xe, args->pad[0] || args->pad[1] || args->pad[2]) || 135 - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) 135 + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]) || 136 + XE_IOCTL_DBG(xe, args->num_syncs > DRM_XE_MAX_SYNCS)) 136 137 return -EINVAL; 137 138 138 139 q = xe_exec_queue_lookup(xef, args->exec_queue_id);
+4 -3
drivers/gpu/drm/xe/xe_gt.c
··· 797 797 xe_gt_sriov_pf_init_hw(gt); 798 798 799 799 xe_mocs_init(gt); 800 - err = xe_uc_start(&gt->uc); 801 - if (err) 802 - return err; 803 800 804 801 for_each_hw_engine(hwe, gt, id) 805 802 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 806 803 807 804 /* Get CCS mode in sync between sw/hw */ 808 805 xe_gt_apply_ccs_mode(gt); 806 + 807 + err = xe_uc_start(&gt->uc); 808 + if (err) 809 + return err; 809 810 810 811 /* Restore GT freq to expected values */ 811 812 xe_gt_sanitize_freq(gt);
+3 -1
drivers/gpu/drm/xe/xe_gt_freq.c
··· 293 293 return -ENOMEM; 294 294 295 295 err = sysfs_create_files(gt->freq, freq_attrs); 296 - if (err) 296 + if (err) { 297 + kobject_put(gt->freq); 297 298 return err; 299 + } 298 300 299 301 err = devm_add_action_or_reset(xe->drm.dev, freq_fini, gt->freq); 300 302 if (err)
+8
drivers/gpu/drm/xe/xe_gt_idle.c
··· 5 5 6 6 #include <drm/drm_managed.h> 7 7 8 + #include <generated/xe_wa_oob.h> 8 9 #include "xe_force_wake.h" 9 10 #include "xe_device.h" 10 11 #include "xe_gt.h" ··· 17 16 #include "xe_mmio.h" 18 17 #include "xe_pm.h" 19 18 #include "xe_sriov.h" 19 + #include "xe_wa.h" 20 20 21 21 /** 22 22 * DOC: Xe GT Idle ··· 146 144 xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25); 147 145 xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25); 148 146 } 147 + 148 + if (XE_GT_WA(gt, 14020316580)) 149 + gtidle->powergate_enable &= ~(VDN_HCP_POWERGATE_ENABLE(0) | 150 + VDN_MFXVDENC_POWERGATE_ENABLE(0) | 151 + VDN_HCP_POWERGATE_ENABLE(2) | 152 + VDN_MFXVDENC_POWERGATE_ENABLE(2)); 149 153 150 154 xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable); 151 155 xe_force_wake_put(gt_to_fw(gt), fw_ref);
+1 -1
drivers/gpu/drm/xe/xe_gt_sriov_vf.c
··· 733 733 734 734 spin_lock(&gt->sriov.vf.migration.lock); 735 735 736 - if (!gt->sriov.vf.migration.recovery_queued || 736 + if (!gt->sriov.vf.migration.recovery_queued && 737 737 !gt->sriov.vf.migration.recovery_teardown) { 738 738 gt->sriov.vf.migration.recovery_queued = true; 739 739 WRITE_ONCE(gt->sriov.vf.migration.recovery_inprogress, true);
+1 -1
drivers/gpu/drm/xe/xe_gt_throttle.c
··· 140 140 struct throttle_attribute *other_ta = kobj_attribute_to_throttle(kattr); 141 141 142 142 if (other_ta->mask != U32_MAX && reasons & other_ta->mask) 143 - ret += sysfs_emit_at(buff, ret, "%s ", (*pother)->name); 143 + ret += sysfs_emit_at(buff, ret, "%s ", (*pother)->name + strlen("reason_")); 144 144 } 145 145 146 146 if (drm_WARN_ONCE(&xe->drm, !ret, "Unknown reason: %#x\n", reasons))
+28 -7
drivers/gpu/drm/xe/xe_guc_submit.c
··· 717 717 return xe_gt_recovery_pending(guc_to_gt(guc)); 718 718 } 719 719 720 + static inline void relaxed_ms_sleep(unsigned int delay_ms) 721 + { 722 + unsigned long min_us, max_us; 723 + 724 + if (!delay_ms) 725 + return; 726 + 727 + if (delay_ms > 20) { 728 + msleep(delay_ms); 729 + return; 730 + } 731 + 732 + min_us = mul_u32_u32(delay_ms, 1000); 733 + max_us = min_us + 500; 734 + 735 + usleep_range(min_us, max_us); 736 + } 737 + 720 738 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) 721 739 { 722 740 struct xe_guc *guc = exec_queue_to_guc(q); 723 741 struct xe_device *xe = guc_to_xe(guc); 724 742 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 725 - unsigned int sleep_period_ms = 1; 743 + unsigned int sleep_period_ms = 1, sleep_total_ms = 0; 726 744 727 745 #define AVAILABLE_SPACE \ 728 746 CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) 729 747 if (wqi_size > AVAILABLE_SPACE && !vf_recovery(guc)) { 730 748 try_again: 731 749 q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); 732 - if (wqi_size > AVAILABLE_SPACE) { 733 - if (sleep_period_ms == 1024) { 750 + if (wqi_size > AVAILABLE_SPACE && !vf_recovery(guc)) { 751 + if (sleep_total_ms > 2000) { 734 752 xe_gt_reset_async(q->gt); 735 753 return -ENODEV; 736 754 } 737 755 738 756 msleep(sleep_period_ms); 739 - sleep_period_ms <<= 1; 757 + sleep_total_ms += sleep_period_ms; 758 + if (sleep_period_ms < 64) 759 + sleep_period_ms <<= 1; 740 760 goto try_again; 741 761 } 742 762 } ··· 1605 1585 since_resume_ms; 1606 1586 1607 1587 if (wait_ms > 0 && q->guc->resume_time) 1608 - msleep(wait_ms); 1588 + relaxed_ms_sleep(wait_ms); 1609 1589 1610 1590 set_exec_queue_suspended(q); 1611 1591 disable_scheduling(q, false); ··· 2273 2253 struct xe_exec_queue *q) 2274 2254 { 2275 2255 struct xe_gpu_scheduler *sched = &q->guc->sched; 2276 - struct xe_sched_job *job = NULL; 2256 + struct xe_sched_job *job = NULL, *__job; 2277 2257 bool restore_replay = false; 2278 2258 2279 - list_for_each_entry(job, &sched->base.pending_list, drm.list) { 2259 + list_for_each_entry(__job, &sched->base.pending_list, drm.list) { 2260 + job = __job; 2280 2261 restore_replay |= job->restore_replay; 2281 2262 if (restore_replay) { 2282 2263 xe_gt_dbg(guc_to_gt(guc), "Replay JOB - guc_id=%d, seqno=%d",
+2 -2
drivers/gpu/drm/xe/xe_heci_gsc.c
··· 223 223 if (xe->heci_gsc.irq < 0) 224 224 return; 225 225 226 - ret = generic_handle_irq(xe->heci_gsc.irq); 226 + ret = generic_handle_irq_safe(xe->heci_gsc.irq); 227 227 if (ret) 228 228 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret); 229 229 } ··· 243 243 if (xe->heci_gsc.irq < 0) 244 244 return; 245 245 246 - ret = generic_handle_irq(xe->heci_gsc.irq); 246 + ret = generic_handle_irq_safe(xe->heci_gsc.irq); 247 247 if (ret) 248 248 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret); 249 249 }
+8 -4
drivers/gpu/drm/xe/xe_oa.c
··· 1105 1105 oag_buf_size_select(stream) | 1106 1106 oag_configure_mmio_trigger(stream, true)); 1107 1107 1108 - xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ? 1109 - (OAG_OAGLBCTXCTRL_COUNTER_RESUME | 1108 + xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl, 1109 + OAG_OAGLBCTXCTRL_COUNTER_RESUME | 1110 + (stream->periodic ? 1110 1111 OAG_OAGLBCTXCTRL_TIMER_ENABLE | 1111 1112 REG_FIELD_PREP(OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK, 1112 - stream->period_exponent)) : 0); 1113 + stream->period_exponent) : 0)); 1113 1114 1114 1115 /* 1115 1116 * Initialize Super Queue Internal Cnt Register ··· 1255 1254 static int xe_oa_set_prop_num_syncs(struct xe_oa *oa, u64 value, 1256 1255 struct xe_oa_open_param *param) 1257 1256 { 1257 + if (XE_IOCTL_DBG(oa->xe, value > DRM_XE_MAX_SYNCS)) 1258 + return -EINVAL; 1259 + 1258 1260 param->num_syncs = value; 1259 1261 return 0; 1260 1262 } ··· 1347 1343 ARRAY_SIZE(xe_oa_set_property_funcs_config)); 1348 1344 1349 1345 if (XE_IOCTL_DBG(oa->xe, ext.property >= ARRAY_SIZE(xe_oa_set_property_funcs_open)) || 1350 - XE_IOCTL_DBG(oa->xe, ext.pad)) 1346 + XE_IOCTL_DBG(oa->xe, !ext.property) || XE_IOCTL_DBG(oa->xe, ext.pad)) 1351 1347 return -EINVAL; 1352 1348 1353 1349 idx = array_index_nospec(ext.property, ARRAY_SIZE(xe_oa_set_property_funcs_open));
+1 -1
drivers/gpu/drm/xe/xe_sriov_vfio.c
··· 21 21 bool xe_sriov_vfio_migration_supported(struct xe_device *xe) 22 22 { 23 23 if (!IS_SRIOV_PF(xe)) 24 - return -EPERM; 24 + return false; 25 25 26 26 return xe_sriov_pf_migration_supported(xe); 27 27 }
+1 -1
drivers/gpu/drm/xe/xe_svm.h
··· 214 214 { 215 215 #if IS_ENABLED(CONFIG_DRM_GPUSVM) 216 216 return drm_gpusvm_init(&vm->svm.gpusvm, "Xe SVM (simple)", &vm->xe->drm, 217 - NULL, NULL, 0, 0, 0, NULL, NULL, 0); 217 + NULL, 0, 0, 0, NULL, NULL, 0); 218 218 #else 219 219 return 0; 220 220 #endif
+7 -1
drivers/gpu/drm/xe/xe_vm.c
··· 1508 1508 INIT_WORK(&vm->destroy_work, vm_destroy_work_func); 1509 1509 1510 1510 INIT_LIST_HEAD(&vm->preempt.exec_queues); 1511 - vm->preempt.min_run_period_ms = 10; /* FIXME: Wire up to uAPI */ 1511 + if (flags & XE_VM_FLAG_FAULT_MODE) 1512 + vm->preempt.min_run_period_ms = 0; 1513 + else 1514 + vm->preempt.min_run_period_ms = 5; 1512 1515 1513 1516 for_each_tile(tile, xe, id) 1514 1517 xe_range_fence_tree_init(&vm->rftree[id]); ··· 3325 3322 return -EINVAL; 3326 3323 3327 3324 if (XE_IOCTL_DBG(xe, args->extensions)) 3325 + return -EINVAL; 3326 + 3327 + if (XE_IOCTL_DBG(xe, args->num_syncs > DRM_XE_MAX_SYNCS)) 3328 3328 return -EINVAL; 3329 3329 3330 3330 if (args->num_binds > 1) {
+1 -1
drivers/gpu/drm/xe/xe_vm_types.h
··· 263 263 * @min_run_period_ms: The minimum run period before preempting 264 264 * an engine again 265 265 */ 266 - s64 min_run_period_ms; 266 + unsigned int min_run_period_ms; 267 267 /** @exec_queues: list of exec queues attached to this VM */ 268 268 struct list_head exec_queues; 269 269 /** @num_exec_queues: number exec queues attached to this VM */
-8
drivers/gpu/drm/xe/xe_wa.c
··· 270 270 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)), 271 271 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE), 272 272 }, 273 - { XE_RTP_NAME("14020316580"), 274 - XE_RTP_RULES(MEDIA_VERSION(1301)), 275 - XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE, 276 - VDN_HCP_POWERGATE_ENABLE(0) | 277 - VDN_MFXVDENC_POWERGATE_ENABLE(0) | 278 - VDN_HCP_POWERGATE_ENABLE(2) | 279 - VDN_MFXVDENC_POWERGATE_ENABLE(2))), 280 - }, 281 273 { XE_RTP_NAME("14019449301"), 282 274 XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)), 283 275 XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
+1
drivers/gpu/drm/xe/xe_wa_oob.rules
··· 76 76 77 77 15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER) 78 78 16026007364 MEDIA_VERSION(3000) 79 + 14020316580 MEDIA_VERSION(1301)
+1
include/uapi/drm/xe_drm.h
··· 1463 1463 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1464 1464 __u32 exec_queue_id; 1465 1465 1466 + #define DRM_XE_MAX_SYNCS 1024 1466 1467 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1467 1468 __u32 num_syncs; 1468 1469