Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2026-03-21' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Regular weekly pull request, from sunny San Diego. Usual suspects in
xe/i915/amdgpu with small fixes all over, then some minor fixes across
a few other drivers. It's probably a bit on the heavy side, but most
of the fix seem well contained,
core:
- drm_dev_unplug UAF fix
pagemap:
- lock handling fix
xe:
- A number of teardown fixes
- Skip over non-leaf PTE for PRL generation
- Fix an uninitialized variable
- Fix a missing runtime PM reference
i915/display:
- Fix #15771: Screen corruption and stuttering on P14s w/ 3K display
- Fix for PSR entry setup frames count on rejected commit
- Fix OOPS if firmware is not loaded and suspend is attempted
- Fix unlikely NULL deref due to DC6 on probe
amdgpu:
- Fix gamma 2.2 colorop TFs
- BO list fix
- LTO fix
- DC FP fix
- DisplayID handling fix
- DCN 2.01 fix
- MMHUB boundary fixes
- ISP fix
- TLB fence fix
- Hainan pm fix
radeon:
- Hainan pm fix
vmwgfx:
- memory leak fix
- doc warning fix
imagination:
- deadlock fix
- interrupt handling fixes
dw-hdmi-qp:
- multi channel audio fix"
* tag 'drm-fixes-2026-03-21' of https://gitlab.freedesktop.org/drm/kernel: (40 commits)
drm/xe: Fix missing runtime PM reference in ccs_mode_store
drm/xe: Open-code GGTT MMIO access protection
drm/xe/lrc: Fix uninitialized new_ts when capturing context timestamp
drm/xe/oa: Allow reading after disabling OA stream
drm/xe: Skip over non leaf pte for PRL generation
drm/xe/guc: Ensure CT state transitions via STOP before DISABLED
drm/xe: Trigger queue cleanup if not in wedged mode 2
drm/xe: Forcefully tear down exec queues in GuC submit fini
drm/xe: Always kill exec queues in xe_guc_submit_pause_abort
drm/xe/guc: Fail immediately on GuC load error
drm/i915/gt: Check set_default_submission() before deferencing
drm/radeon: apply state adjust rules to some additional HAINAN vairants
drm/amdgpu: apply state adjust rules to some additional HAINAN vairants
drm/amdgpu: rework how we handle TLB fences
drm/bridge: dw-hdmi-qp: fix multi-channel audio output
drm: Fix use-after-free on framebuffers and property blobs when calling drm_dev_unplug
drm/amdgpu: Fix ISP segfault issue in kernel v7.0
drm/amdgpu/gmc9.0: add bounds checking for cid
drm/amdgpu/mmhub4.2.0: add bounds checking for cid
drm/amdgpu/mmhub4.1.0: add bounds checking for cid
...
+325
-167
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c
···
36
36
37
37
#define AMDGPU_BO_LIST_MAX_PRIORITY 32u
38
38
#define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1)
39
+
#define AMDGPU_BO_LIST_MAX_ENTRIES (128 * 1024)
39
40
40
41
static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu)
41
42
{
···
188
187
const uint32_t bo_info_size = in->bo_info_size;
189
188
const uint32_t bo_number = in->bo_number;
190
189
struct drm_amdgpu_bo_list_entry *info;
190
+
191
+
if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES)
192
+
return -EINVAL;
191
193
192
194
/* copy the handle array from userspace to a kernel buffer */
193
195
if (likely(info_size == bo_info_size)) {
+6
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+6
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1069
1069
}
1070
1070
1071
1071
/* Prepare a TLB flush fence to be attached to PTs */
1072
-
if (!params->unlocked) {
1072
+
/* The check for need_tlb_fence should be dropped once we
1073
+
* sort out the issues with KIQ/MES TLB invalidation timeouts.
1074
+
*/
1075
+
if (!params->unlocked && vm->need_tlb_fence) {
1073
1076
amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
1074
1077
1075
1078
/* Makes sure no PD/PT is freed before the flush */
···
2605
2602
ttm_lru_bulk_move_init(&vm->lru_bulk_move);
2606
2603
2607
2604
vm->is_compute_context = false;
2605
+
vm->need_tlb_fence = amdgpu_userq_enabled(&adev->ddev);
2608
2606
2609
2607
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2610
2608
AMDGPU_VM_USE_CPU_FOR_GFX);
···
2743
2739
dma_fence_put(vm->last_update);
2744
2740
vm->last_update = dma_fence_get_stub();
2745
2741
vm->is_compute_context = true;
2742
+
vm->need_tlb_fence = true;
2746
2743
2747
2744
unreserve_bo:
2748
2745
amdgpu_bo_unreserve(vm->root.bo);
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
···
441
441
struct ttm_lru_bulk_move lru_bulk_move;
442
442
/* Flag to indicate if VM is used for compute */
443
443
bool is_compute_context;
444
+
/* Flag to indicate if VM needs a TLB fence (KFD or KGD) */
445
+
bool need_tlb_fence;
444
446
445
447
/* Memory partition number, -1 means any partition */
446
448
int8_t mem_id;
+14
-7
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+14
-7
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
662
662
} else {
663
663
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
664
664
case IP_VERSION(9, 0, 0):
665
-
mmhub_cid = mmhub_client_ids_vega10[cid][rw];
665
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega10) ?
666
+
mmhub_client_ids_vega10[cid][rw] : NULL;
666
667
break;
667
668
case IP_VERSION(9, 3, 0):
668
-
mmhub_cid = mmhub_client_ids_vega12[cid][rw];
669
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega12) ?
670
+
mmhub_client_ids_vega12[cid][rw] : NULL;
669
671
break;
670
672
case IP_VERSION(9, 4, 0):
671
-
mmhub_cid = mmhub_client_ids_vega20[cid][rw];
673
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vega20) ?
674
+
mmhub_client_ids_vega20[cid][rw] : NULL;
672
675
break;
673
676
case IP_VERSION(9, 4, 1):
674
-
mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
677
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_arcturus) ?
678
+
mmhub_client_ids_arcturus[cid][rw] : NULL;
675
679
break;
676
680
case IP_VERSION(9, 1, 0):
677
681
case IP_VERSION(9, 2, 0):
678
-
mmhub_cid = mmhub_client_ids_raven[cid][rw];
682
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_raven) ?
683
+
mmhub_client_ids_raven[cid][rw] : NULL;
679
684
break;
680
685
case IP_VERSION(1, 5, 0):
681
686
case IP_VERSION(2, 4, 0):
682
-
mmhub_cid = mmhub_client_ids_renoir[cid][rw];
687
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_renoir) ?
688
+
mmhub_client_ids_renoir[cid][rw] : NULL;
683
689
break;
684
690
case IP_VERSION(1, 8, 0):
685
691
case IP_VERSION(9, 4, 2):
686
-
mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
692
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_aldebaran) ?
693
+
mmhub_client_ids_aldebaran[cid][rw] : NULL;
687
694
break;
688
695
default:
689
696
mmhub_cid = NULL;
+2
-2
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
+2
-2
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
···
129
129
if (!pdev)
130
130
return -EINVAL;
131
131
132
-
if (!dev->type->name) {
132
+
if (!dev->type || !dev->type->name) {
133
133
drm_dbg(&adev->ddev, "Invalid device type to add\n");
134
134
goto exit;
135
135
}
···
165
165
if (!pdev)
166
166
return -EINVAL;
167
167
168
-
if (!dev->type->name) {
168
+
if (!dev->type || !dev->type->name) {
169
169
drm_dbg(&adev->ddev, "Invalid device type to remove\n");
170
170
goto exit;
171
171
}
+6
-3
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+6
-3
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
···
154
154
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
155
155
case IP_VERSION(2, 0, 0):
156
156
case IP_VERSION(2, 0, 2):
157
-
mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
157
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_navi1x) ?
158
+
mmhub_client_ids_navi1x[cid][rw] : NULL;
158
159
break;
159
160
case IP_VERSION(2, 1, 0):
160
161
case IP_VERSION(2, 1, 1):
161
-
mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
162
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_sienna_cichlid) ?
163
+
mmhub_client_ids_sienna_cichlid[cid][rw] : NULL;
162
164
break;
163
165
case IP_VERSION(2, 1, 2):
164
-
mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
166
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_beige_goby) ?
167
+
mmhub_client_ids_beige_goby[cid][rw] : NULL;
165
168
break;
166
169
default:
167
170
mmhub_cid = NULL;
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
···
94
94
case IP_VERSION(2, 3, 0):
95
95
case IP_VERSION(2, 4, 0):
96
96
case IP_VERSION(2, 4, 1):
97
-
mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
97
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_vangogh) ?
98
+
mmhub_client_ids_vangogh[cid][rw] : NULL;
98
99
break;
99
100
default:
100
101
mmhub_cid = NULL;
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
···
110
110
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
111
111
case IP_VERSION(3, 0, 0):
112
112
case IP_VERSION(3, 0, 1):
113
-
mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw];
113
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_0) ?
114
+
mmhub_client_ids_v3_0_0[cid][rw] : NULL;
114
115
break;
115
116
default:
116
117
mmhub_cid = NULL;
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
···
117
117
118
118
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
119
119
case IP_VERSION(3, 0, 1):
120
-
mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
120
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_1) ?
121
+
mmhub_client_ids_v3_0_1[cid][rw] : NULL;
121
122
break;
122
123
default:
123
124
mmhub_cid = NULL;
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
···
108
108
"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
109
109
status);
110
110
111
-
mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw];
111
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_0_2) ?
112
+
mmhub_client_ids_v3_0_2[cid][rw] : NULL;
112
113
dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
113
114
mmhub_cid ? mmhub_cid : "unknown", cid);
114
115
dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c
···
102
102
status);
103
103
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
104
104
case IP_VERSION(4, 1, 0):
105
-
mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw];
105
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_1_0) ?
106
+
mmhub_client_ids_v4_1_0[cid][rw] : NULL;
106
107
break;
107
108
default:
108
109
mmhub_cid = NULL;
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
+2
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c
···
688
688
status);
689
689
switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
690
690
case IP_VERSION(4, 2, 0):
691
-
mmhub_cid = mmhub_client_ids_v4_2_0[cid][rw];
691
+
mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v4_2_0) ?
692
+
mmhub_client_ids_v4_2_0[cid][rw] : NULL;
692
693
break;
693
694
default:
694
695
mmhub_cid = NULL;
+3
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+3
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
2554
2554
fw_meta_info_params.fw_inst_const = adev->dm.dmub_fw->data +
2555
2555
le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2556
2556
PSP_HEADER_BYTES_256;
2557
-
fw_meta_info_params.fw_bss_data = region_params.bss_data_size ? adev->dm.dmub_fw->data +
2557
+
fw_meta_info_params.fw_bss_data = fw_meta_info_params.bss_data_size ? adev->dm.dmub_fw->data +
2558
2558
le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2559
2559
le32_to_cpu(hdr->inst_const_bytes) : NULL;
2560
2560
fw_meta_info_params.custom_psp_footer_size = 0;
···
13119
13119
u16 min_vfreq;
13120
13120
u16 max_vfreq;
13121
13121
13122
-
if (edid == NULL || edid->extensions == 0)
13122
+
if (!edid || !edid->extensions)
13123
13123
return;
13124
13124
13125
13125
/* Find DisplayID extension */
···
13129
13129
break;
13130
13130
}
13131
13131
13132
-
if (edid_ext == NULL)
13132
+
if (i == edid->extensions)
13133
13133
return;
13134
13134
13135
13135
while (j < EDID_LENGTH) {
+3
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+3
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
···
37
37
BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
38
38
BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
39
39
BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
40
-
BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
40
+
BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
41
41
42
42
const u64 amdgpu_dm_supported_shaper_tfs =
43
43
BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF) |
44
44
BIT(DRM_COLOROP_1D_CURVE_PQ_125_INV_EOTF) |
45
45
BIT(DRM_COLOROP_1D_CURVE_BT2020_OETF) |
46
-
BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
46
+
BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
47
47
48
48
const u64 amdgpu_dm_supported_blnd_tfs =
49
49
BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) |
50
50
BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) |
51
51
BIT(DRM_COLOROP_1D_CURVE_BT2020_INV_OETF) |
52
-
BIT(DRM_COLOROP_1D_CURVE_GAMMA22_INV);
52
+
BIT(DRM_COLOROP_1D_CURVE_GAMMA22);
53
53
54
54
#define MAX_COLOR_PIPELINE_OPS 10
55
55
+4
-4
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+4
-4
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
···
255
255
BREAK_TO_DEBUGGER();
256
256
return NULL;
257
257
}
258
+
if (ctx->dce_version == DCN_VERSION_2_01) {
259
+
dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
260
+
return &clk_mgr->base;
261
+
}
258
262
if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
259
263
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
260
264
return &clk_mgr->base;
···
269
265
}
270
266
if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
271
267
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
272
-
return &clk_mgr->base;
273
-
}
274
-
if (ctx->dce_version == DCN_VERSION_2_01) {
275
-
dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
276
268
return &clk_mgr->base;
277
269
}
278
270
dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+3
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+3
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
···
1785
1785
1786
1786
dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1787
1787
1788
+
DC_FP_START();
1788
1789
dcn32_override_min_req_memclk(dc, context);
1790
+
DC_FP_END();
1791
+
1789
1792
dcn32_override_min_req_dcfclk(dc, context);
1790
1793
1791
1794
BW_VAL_TRACE_END_WATERMARKS();
+3
-1
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+3
-1
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
···
3454
3454
if (adev->asic_type == CHIP_HAINAN) {
3455
3455
if ((adev->pdev->revision == 0x81) ||
3456
3456
(adev->pdev->revision == 0xC3) ||
3457
+
(adev->pdev->device == 0x6660) ||
3457
3458
(adev->pdev->device == 0x6664) ||
3458
3459
(adev->pdev->device == 0x6665) ||
3459
-
(adev->pdev->device == 0x6667)) {
3460
+
(adev->pdev->device == 0x6667) ||
3461
+
(adev->pdev->device == 0x666F)) {
3460
3462
max_sclk = 75000;
3461
3463
}
3462
3464
if ((adev->pdev->revision == 0xC3) ||
+1
-1
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
+1
-1
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
···
848
848
849
849
regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);
850
850
regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);
851
-
regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1);
851
+
regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[7], 1);
852
852
853
853
/* Enable ACR, AUDI, AMD */
854
854
dw_hdmi_qp_mod(hdmi,
+4
-1
drivers/gpu/drm/drm_file.c
+4
-1
drivers/gpu/drm/drm_file.c
···
233
233
void drm_file_free(struct drm_file *file)
234
234
{
235
235
struct drm_device *dev;
236
+
int idx;
236
237
237
238
if (!file)
238
239
return;
···
250
249
251
250
drm_events_release(file);
252
251
253
-
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
252
+
if (drm_core_check_feature(dev, DRIVER_MODESET) &&
253
+
drm_dev_enter(dev, &idx)) {
254
254
drm_fb_release(file);
255
255
drm_property_destroy_user_blobs(dev, file);
256
+
drm_dev_exit(idx);
256
257
}
257
258
258
259
if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+6
-3
drivers/gpu/drm/drm_mode_config.c
+6
-3
drivers/gpu/drm/drm_mode_config.c
···
577
577
*/
578
578
WARN_ON(!list_empty(&dev->mode_config.fb_list));
579
579
list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) {
580
-
struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]");
580
+
if (list_empty(&fb->filp_head) || drm_framebuffer_read_refcount(fb) > 1) {
581
+
struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]");
581
582
582
-
drm_printf(&p, "framebuffer[%u]:\n", fb->base.id);
583
-
drm_framebuffer_print_info(&p, 1, fb);
583
+
drm_printf(&p, "framebuffer[%u]:\n", fb->base.id);
584
+
drm_framebuffer_print_info(&p, 1, fb);
585
+
}
586
+
list_del_init(&fb->filp_head);
584
587
drm_framebuffer_free(&fb->base.refcount);
585
588
}
586
589
+5
-9
drivers/gpu/drm/drm_pagemap_util.c
+5
-9
drivers/gpu/drm/drm_pagemap_util.c
···
65
65
drm_dbg(cache->shrinker->drm, "Destroying dpagemap cache.\n");
66
66
spin_lock(&cache->lock);
67
67
dpagemap = cache->dpagemap;
68
-
if (!dpagemap) {
69
-
spin_unlock(&cache->lock);
70
-
goto out;
71
-
}
68
+
cache->dpagemap = NULL;
69
+
if (dpagemap && !drm_pagemap_shrinker_cancel(dpagemap))
70
+
dpagemap = NULL;
71
+
spin_unlock(&cache->lock);
72
72
73
-
if (drm_pagemap_shrinker_cancel(dpagemap)) {
74
-
cache->dpagemap = NULL;
75
-
spin_unlock(&cache->lock);
73
+
if (dpagemap)
76
74
drm_pagemap_destroy(dpagemap, false);
77
-
}
78
75
79
-
out:
80
76
mutex_destroy(&cache->lookup_mutex);
81
77
kfree(cache);
82
78
}
+1
-1
drivers/gpu/drm/i915/display/intel_display_power_well.c
+1
-1
drivers/gpu/drm/i915/display/intel_display_power_well.c
···
806
806
power_domains->dc_state, val & mask);
807
807
808
808
enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
809
-
dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
809
+
dc6_was_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;
810
810
if (!dc6_was_enabled && enable_dc6)
811
811
intel_dmc_update_dc6_allowed_count(display, true);
812
812
+1
drivers/gpu/drm/i915/display/intel_display_types.h
+1
drivers/gpu/drm/i915/display/intel_display_types.h
+1
-2
drivers/gpu/drm/i915/display/intel_dmc.c
+1
-2
drivers/gpu/drm/i915/display/intel_dmc.c
···
1599
1599
return false;
1600
1600
1601
1601
mutex_lock(&power_domains->lock);
1602
-
dc6_enabled = intel_de_read(display, DC_STATE_EN) &
1603
-
DC_STATE_EN_UPTO_DC6;
1602
+
dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6;
1604
1603
if (dc6_enabled)
1605
1604
intel_dmc_update_dc6_allowed_count(display, false);
1606
1605
+5
-2
drivers/gpu/drm/i915/display/intel_psr.c
+5
-2
drivers/gpu/drm/i915/display/intel_psr.c
···
1717
1717
entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode);
1718
1718
1719
1719
if (entry_setup_frames >= 0) {
1720
-
intel_dp->psr.entry_setup_frames = entry_setup_frames;
1720
+
crtc_state->entry_setup_frames = entry_setup_frames;
1721
1721
} else {
1722
1722
crtc_state->no_psr_reason = "PSR setup timing not met";
1723
1723
drm_dbg_kms(display->drm,
···
1815
1815
{
1816
1816
struct intel_display *display = to_intel_display(intel_dp);
1817
1817
1818
-
return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 &&
1818
+
return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
1819
1819
!crtc_state->has_sel_update);
1820
1820
}
1821
1821
···
2189
2189
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
2190
2190
intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;
2191
2191
intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;
2192
+
intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
2192
2193
2193
2194
if (!psr_interrupt_error_check(intel_dp))
2194
2195
return;
···
3110
3109
* - Display WA #1136: skl, bxt
3111
3110
*/
3112
3111
if (intel_crtc_needs_modeset(new_crtc_state) ||
3112
+
new_crtc_state->update_m_n ||
3113
+
new_crtc_state->update_lrr ||
3113
3114
!new_crtc_state->has_psr ||
3114
3115
!new_crtc_state->active_planes ||
3115
3116
new_crtc_state->has_sel_update != psr->sel_update_enabled ||
+2
-1
drivers/gpu/drm/i915/gt/intel_engine_cs.c
+2
-1
drivers/gpu/drm/i915/gt/intel_engine_cs.c
-17
drivers/gpu/drm/imagination/pvr_device.c
-17
drivers/gpu/drm/imagination/pvr_device.c
···
225
225
}
226
226
227
227
if (pvr_dev->has_safety_events) {
228
-
int err;
229
-
230
-
/*
231
-
* Ensure the GPU is powered on since some safety events (such
232
-
* as ECC faults) can happen outside of job submissions, which
233
-
* are otherwise the only time a power reference is held.
234
-
*/
235
-
err = pvr_power_get(pvr_dev);
236
-
if (err) {
237
-
drm_err_ratelimited(drm_dev,
238
-
"%s: could not take power reference (%d)\n",
239
-
__func__, err);
240
-
return ret;
241
-
}
242
-
243
228
while (pvr_device_safety_irq_pending(pvr_dev)) {
244
229
pvr_device_safety_irq_clear(pvr_dev);
245
230
pvr_device_handle_safety_events(pvr_dev);
246
231
247
232
ret = IRQ_HANDLED;
248
233
}
249
-
250
-
pvr_power_put(pvr_dev);
251
234
}
252
235
253
236
return ret;
+39
-12
drivers/gpu/drm/imagination/pvr_power.c
+39
-12
drivers/gpu/drm/imagination/pvr_power.c
···
90
90
}
91
91
92
92
static int
93
-
pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset)
93
+
pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend)
94
94
{
95
-
if (!hard_reset) {
96
-
int err;
95
+
int err;
97
96
97
+
if (!hard_reset) {
98
98
cancel_delayed_work_sync(&pvr_dev->watchdog.work);
99
99
100
100
err = pvr_power_request_idle(pvr_dev);
···
106
106
return err;
107
107
}
108
108
109
-
return pvr_fw_stop(pvr_dev);
109
+
if (rpm_suspend) {
110
+
/* This also waits for late processing of GPU or firmware IRQs in other cores */
111
+
disable_irq(pvr_dev->irq);
112
+
}
113
+
114
+
err = pvr_fw_stop(pvr_dev);
115
+
if (err && rpm_suspend)
116
+
enable_irq(pvr_dev->irq);
117
+
118
+
return err;
110
119
}
111
120
112
121
static int
113
-
pvr_power_fw_enable(struct pvr_device *pvr_dev)
122
+
pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume)
114
123
{
115
124
int err;
116
125
126
+
if (rpm_resume)
127
+
enable_irq(pvr_dev->irq);
128
+
117
129
err = pvr_fw_start(pvr_dev);
118
130
if (err)
119
-
return err;
131
+
goto out;
120
132
121
133
err = pvr_wait_for_fw_boot(pvr_dev);
122
134
if (err) {
123
135
drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n");
124
136
pvr_fw_stop(pvr_dev);
125
-
return err;
137
+
goto out;
126
138
}
127
139
128
140
queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work,
129
141
msecs_to_jiffies(WATCHDOG_TIME_MS));
130
142
131
143
return 0;
144
+
145
+
out:
146
+
if (rpm_resume)
147
+
disable_irq(pvr_dev->irq);
148
+
149
+
return err;
132
150
}
133
151
134
152
bool
···
379
361
return -EIO;
380
362
381
363
if (pvr_dev->fw_dev.booted) {
382
-
err = pvr_power_fw_disable(pvr_dev, false);
364
+
err = pvr_power_fw_disable(pvr_dev, false, true);
383
365
if (err)
384
366
goto err_drm_dev_exit;
385
367
}
···
409
391
goto err_drm_dev_exit;
410
392
411
393
if (pvr_dev->fw_dev.booted) {
412
-
err = pvr_power_fw_enable(pvr_dev);
394
+
err = pvr_power_fw_enable(pvr_dev, true);
413
395
if (err)
414
396
goto err_power_off;
415
397
}
···
528
510
}
529
511
530
512
/* Disable IRQs for the duration of the reset. */
531
-
disable_irq(pvr_dev->irq);
513
+
if (hard_reset) {
514
+
disable_irq(pvr_dev->irq);
515
+
} else {
516
+
/*
517
+
* Soft reset is triggered as a response to a FW command to the Host and is
518
+
* processed from the threaded IRQ handler. This code cannot (nor needs to)
519
+
* wait for any IRQ processing to complete.
520
+
*/
521
+
disable_irq_nosync(pvr_dev->irq);
522
+
}
532
523
533
524
do {
534
525
if (hard_reset) {
···
545
518
queues_disabled = true;
546
519
}
547
520
548
-
err = pvr_power_fw_disable(pvr_dev, hard_reset);
521
+
err = pvr_power_fw_disable(pvr_dev, hard_reset, false);
549
522
if (!err) {
550
523
if (hard_reset) {
551
524
pvr_dev->fw_dev.booted = false;
···
568
541
569
542
pvr_fw_irq_clear(pvr_dev);
570
543
571
-
err = pvr_power_fw_enable(pvr_dev);
544
+
err = pvr_power_fw_enable(pvr_dev, false);
572
545
}
573
546
574
547
if (err && hard_reset)
+3
-1
drivers/gpu/drm/radeon/si_dpm.c
+3
-1
drivers/gpu/drm/radeon/si_dpm.c
···
2915
2915
if (rdev->family == CHIP_HAINAN) {
2916
2916
if ((rdev->pdev->revision == 0x81) ||
2917
2917
(rdev->pdev->revision == 0xC3) ||
2918
+
(rdev->pdev->device == 0x6660) ||
2918
2919
(rdev->pdev->device == 0x6664) ||
2919
2920
(rdev->pdev->device == 0x6665) ||
2920
-
(rdev->pdev->device == 0x6667)) {
2921
+
(rdev->pdev->device == 0x6667) ||
2922
+
(rdev->pdev->device == 0x666F)) {
2921
2923
max_sclk = 75000;
2922
2924
}
2923
2925
if ((rdev->pdev->revision == 0xC3) ||
+57
-36
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+57
-36
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
···
96
96
97
97
struct vmw_res_func;
98
98
99
+
struct vmw_bo;
100
+
struct vmw_bo;
101
+
struct vmw_resource_dirty;
102
+
99
103
/**
100
-
* struct vmw-resource - base class for hardware resources
104
+
* struct vmw_resource - base class for hardware resources
101
105
*
102
106
* @kref: For refcounting.
103
107
* @dev_priv: Pointer to the device private for this resource. Immutable.
104
108
* @id: Device id. Protected by @dev_priv::resource_lock.
109
+
* @used_prio: Priority for this resource.
105
110
* @guest_memory_size: Guest memory buffer size. Immutable.
106
111
* @res_dirty: Resource contains data not yet in the guest memory buffer.
107
112
* Protected by resource reserved.
···
122
117
* pin-count greater than zero. It is not on the resource LRU lists and its
123
118
* guest memory buffer is pinned. Hence it can't be evicted.
124
119
* @func: Method vtable for this resource. Immutable.
125
-
* @mob_node; Node for the MOB guest memory rbtree. Protected by
120
+
* @mob_node: Node for the MOB guest memory rbtree. Protected by
126
121
* @guest_memory_bo reserved.
127
122
* @lru_head: List head for the LRU list. Protected by @dev_priv::resource_lock.
128
123
* @binding_head: List head for the context binding list. Protected by
129
124
* the @dev_priv::binding_mutex
125
+
* @dirty: resource's dirty tracker
130
126
* @res_free: The resource destructor.
131
127
* @hw_destroy: Callback to destroy the resource on the device, as part of
132
128
* resource destruction.
133
129
*/
134
-
struct vmw_bo;
135
-
struct vmw_bo;
136
-
struct vmw_resource_dirty;
137
130
struct vmw_resource {
138
131
struct kref kref;
139
132
struct vmw_private *dev_priv;
···
199
196
* @quality_level: Quality level.
200
197
* @autogen_filter: Filter for automatically generated mipmaps.
201
198
* @array_size: Number of array elements for a 1D/2D texture. For cubemap
202
-
texture number of faces * array_size. This should be 0 for pre
203
-
SM4 device.
199
+
* texture number of faces * array_size. This should be 0 for pre
200
+
* SM4 device.
204
201
* @buffer_byte_stride: Buffer byte stride.
205
202
* @num_sizes: Size of @sizes. For GB surface this should always be 1.
206
203
* @base_size: Surface dimension.
···
268
265
struct vmw_res_cache_entry {
269
266
uint32_t handle;
270
267
struct vmw_resource *res;
268
+
/* private: */
271
269
void *private;
270
+
/* public: */
272
271
unsigned short valid_handle;
273
272
unsigned short valid;
274
273
};
275
274
276
275
/**
277
276
* enum vmw_dma_map_mode - indicate how to perform TTM page dma mappings.
277
+
* @vmw_dma_alloc_coherent: Use TTM coherent pages
278
+
* @vmw_dma_map_populate: Unmap from DMA just after unpopulate
279
+
* @vmw_dma_map_bind: Unmap from DMA just before unbind
278
280
*/
279
281
enum vmw_dma_map_mode {
280
-
vmw_dma_alloc_coherent, /* Use TTM coherent pages */
281
-
vmw_dma_map_populate, /* Unmap from DMA just after unpopulate */
282
-
vmw_dma_map_bind, /* Unmap from DMA just before unbind */
282
+
vmw_dma_alloc_coherent,
283
+
vmw_dma_map_populate,
284
+
vmw_dma_map_bind,
285
+
/* private: */
283
286
vmw_dma_map_max
284
287
};
285
288
···
293
284
* struct vmw_sg_table - Scatter/gather table for binding, with additional
294
285
* device-specific information.
295
286
*
287
+
* @mode: which page mapping mode to use
288
+
* @pages: Array of page pointers to the pages.
289
+
* @addrs: DMA addresses to the pages if coherent pages are used.
296
290
* @sgt: Pointer to a struct sg_table with binding information
297
-
* @num_regions: Number of regions with device-address contiguous pages
291
+
* @num_pages: Number of @pages
298
292
*/
299
293
struct vmw_sg_table {
300
294
enum vmw_dma_map_mode mode;
···
365
353
* than from user-space
366
354
* @fp: If @kernel is false, points to the file of the client. Otherwise
367
355
* NULL
356
+
* @filp: DRM state for this file
368
357
* @cmd_bounce: Command bounce buffer used for command validation before
369
358
* copying to fifo space
370
359
* @cmd_bounce_size: Current command bounce buffer size
···
742
729
bool vmwgfx_supported(struct vmw_private *vmw);
743
730
744
731
745
-
/**
732
+
/*
746
733
* GMR utilities - vmwgfx_gmr.c
747
734
*/
748
735
···
752
739
int gmr_id);
753
740
extern void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id);
754
741
755
-
/**
742
+
/*
756
743
* User handles
757
744
*/
758
745
struct vmw_user_object {
···
772
759
void vmw_user_object_unmap(struct vmw_user_object *uo);
773
760
bool vmw_user_object_is_mapped(struct vmw_user_object *uo);
774
761
775
-
/**
762
+
/*
776
763
* Resource utilities - vmwgfx_resource.c
777
764
*/
778
765
struct vmw_user_resource_conv;
···
832
819
return !RB_EMPTY_NODE(&res->mob_node);
833
820
}
834
821
835
-
/**
822
+
/*
836
823
* GEM related functionality - vmwgfx_gem.c
837
824
*/
838
825
struct vmw_bo_params;
···
846
833
struct drm_file *filp);
847
834
extern void vmw_debugfs_gem_init(struct vmw_private *vdev);
848
835
849
-
/**
836
+
/*
850
837
* Misc Ioctl functionality - vmwgfx_ioctl.c
851
838
*/
852
839
···
859
846
extern int vmw_present_readback_ioctl(struct drm_device *dev, void *data,
860
847
struct drm_file *file_priv);
861
848
862
-
/**
849
+
/*
863
850
* Fifo utilities - vmwgfx_fifo.c
864
851
*/
865
852
···
893
880
894
881
895
882
/**
896
-
* vmw_fifo_caps - Returns the capabilities of the FIFO command
883
+
* vmw_fifo_caps - Get the capabilities of the FIFO command
897
884
* queue or 0 if fifo memory isn't present.
898
885
* @dev_priv: The device private context
886
+
*
887
+
* Returns: capabilities of the FIFO command or %0 if fifo memory not present
899
888
*/
900
889
static inline uint32_t vmw_fifo_caps(const struct vmw_private *dev_priv)
901
890
{
···
908
893
909
894
910
895
/**
911
-
* vmw_is_cursor_bypass3_enabled - Returns TRUE iff Cursor Bypass 3
912
-
* is enabled in the FIFO.
896
+
* vmw_is_cursor_bypass3_enabled - check Cursor Bypass 3 enabled setting
897
+
* in the FIFO.
913
898
* @dev_priv: The device private context
899
+
*
900
+
* Returns: %true iff Cursor Bypass 3 is enabled in the FIFO
914
901
*/
915
902
static inline bool
916
903
vmw_is_cursor_bypass3_enabled(const struct vmw_private *dev_priv)
···
920
903
return (vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_CURSOR_BYPASS_3) != 0;
921
904
}
922
905
923
-
/**
906
+
/*
924
907
* TTM buffer object driver - vmwgfx_ttm_buffer.c
925
908
*/
926
909
···
944
927
*
945
928
* @viter: Pointer to the iterator to advance.
946
929
*
947
-
* Returns false if past the list of pages, true otherwise.
930
+
* Returns: false if past the list of pages, true otherwise.
948
931
*/
949
932
static inline bool vmw_piter_next(struct vmw_piter *viter)
950
933
{
···
956
939
*
957
940
* @viter: Pointer to the iterator
958
941
*
959
-
* Returns the DMA address of the page pointed to by @viter.
942
+
* Returns: the DMA address of the page pointed to by @viter.
960
943
*/
961
944
static inline dma_addr_t vmw_piter_dma_addr(struct vmw_piter *viter)
962
945
{
···
968
951
*
969
952
* @viter: Pointer to the iterator
970
953
*
971
-
* Returns the DMA address of the page pointed to by @viter.
954
+
* Returns: the DMA address of the page pointed to by @viter.
972
955
*/
973
956
static inline struct page *vmw_piter_page(struct vmw_piter *viter)
974
957
{
975
958
return viter->pages[viter->i];
976
959
}
977
960
978
-
/**
961
+
/*
979
962
* Command submission - vmwgfx_execbuf.c
980
963
*/
981
964
···
1010
993
int32_t out_fence_fd);
1011
994
bool vmw_cmd_describe(const void *buf, u32 *size, char const **cmd);
1012
995
1013
-
/**
996
+
/*
1014
997
* IRQs and wating - vmwgfx_irq.c
1015
998
*/
1016
999
···
1033
1016
bool vmw_generic_waiter_remove(struct vmw_private *dev_priv,
1034
1017
u32 flag, int *waiter_count);
1035
1018
1036
-
/**
1019
+
/*
1037
1020
* Kernel modesetting - vmwgfx_kms.c
1038
1021
*/
1039
1022
···
1065
1048
extern void vmw_resource_unpin(struct vmw_resource *res);
1066
1049
extern enum vmw_res_type vmw_res_type(const struct vmw_resource *res);
1067
1050
1068
-
/**
1051
+
/*
1069
1052
* Overlay control - vmwgfx_overlay.c
1070
1053
*/
1071
1054
···
1080
1063
int vmw_overlay_num_overlays(struct vmw_private *dev_priv);
1081
1064
int vmw_overlay_num_free_overlays(struct vmw_private *dev_priv);
1082
1065
1083
-
/**
1066
+
/*
1084
1067
* GMR Id manager
1085
1068
*/
1086
1069
1087
1070
int vmw_gmrid_man_init(struct vmw_private *dev_priv, int type);
1088
1071
void vmw_gmrid_man_fini(struct vmw_private *dev_priv, int type);
1089
1072
1090
-
/**
1073
+
/*
1091
1074
* System memory manager
1092
1075
*/
1093
1076
int vmw_sys_man_init(struct vmw_private *dev_priv);
1094
1077
void vmw_sys_man_fini(struct vmw_private *dev_priv);
1095
1078
1096
-
/**
1079
+
/*
1097
1080
* Prime - vmwgfx_prime.c
1098
1081
*/
1099
1082
···
1309
1292
* @line: The current line of the blit.
1310
1293
* @line_offset: Offset of the current line segment.
1311
1294
* @cpp: Bytes per pixel (granularity information).
1312
-
* @memcpy: Which memcpy function to use.
1295
+
* @do_cpy: Which memcpy function to use.
1313
1296
*/
1314
1297
struct vmw_diff_cpy {
1315
1298
struct drm_rect rect;
···
1397
1380
1398
1381
/**
1399
1382
* VMW_DEBUG_KMS - Debug output for kernel mode-setting
1383
+
* @fmt: format string for the args
1400
1384
*
1401
1385
* This macro is for debugging vmwgfx mode-setting code.
1402
1386
*/
1403
1387
#define VMW_DEBUG_KMS(fmt, ...) \
1404
1388
DRM_DEBUG_DRIVER(fmt, ##__VA_ARGS__)
1405
1389
1406
-
/**
1390
+
/*
1407
1391
* Inline helper functions
1408
1392
*/
1409
1393
···
1435
1417
1436
1418
/**
1437
1419
* vmw_fifo_mem_read - Perform a MMIO read from the fifo memory
1438
-
*
1420
+
* @vmw: The device private structure
1439
1421
* @fifo_reg: The fifo register to read from
1440
1422
*
1441
1423
* This function is intended to be equivalent to ioread32() on
1442
1424
* memremap'd memory, but without byteswapping.
1425
+
*
1426
+
* Returns: the value read
1443
1427
*/
1444
1428
static inline u32 vmw_fifo_mem_read(struct vmw_private *vmw, uint32 fifo_reg)
1445
1429
{
···
1451
1431
1452
1432
/**
1453
1433
* vmw_fifo_mem_write - Perform a MMIO write to volatile memory
1454
-
*
1455
-
* @addr: The fifo register to write to
1434
+
* @vmw: The device private structure
1435
+
* @fifo_reg: The fifo register to write to
1436
+
* @value: The value to write
1456
1437
*
1457
1438
* This function is intended to be equivalent to iowrite32 on
1458
1439
* memremap'd memory, but without byteswapping.
+2
-1
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+2
-1
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
771
771
ret = vmw_bo_dirty_add(bo);
772
772
if (!ret && surface && surface->res.func->dirty_alloc) {
773
773
surface->res.coherent = true;
774
-
ret = surface->res.func->dirty_alloc(&surface->res);
774
+
if (surface->res.dirty == NULL)
775
+
ret = surface->res.func->dirty_alloc(&surface->res);
775
776
}
776
777
ttm_bo_unreserve(&bo->tbo);
777
778
}
+4
-6
drivers/gpu/drm/xe/xe_ggtt.c
+4
-6
drivers/gpu/drm/xe/xe_ggtt.c
···
313
313
{
314
314
struct xe_ggtt *ggtt = arg;
315
315
316
+
scoped_guard(mutex, &ggtt->lock)
317
+
ggtt->flags &= ~XE_GGTT_FLAGS_ONLINE;
316
318
drain_workqueue(ggtt->wq);
317
319
}
318
320
···
379
377
if (err)
380
378
return err;
381
379
380
+
ggtt->flags |= XE_GGTT_FLAGS_ONLINE;
382
381
err = devm_add_action_or_reset(xe->drm.dev, dev_fini_ggtt, ggtt);
383
382
if (err)
384
383
return err;
···
413
410
static void ggtt_node_remove(struct xe_ggtt_node *node)
414
411
{
415
412
struct xe_ggtt *ggtt = node->ggtt;
416
-
struct xe_device *xe = tile_to_xe(ggtt->tile);
417
413
bool bound;
418
-
int idx;
419
-
420
-
bound = drm_dev_enter(&xe->drm, &idx);
421
414
422
415
mutex_lock(&ggtt->lock);
416
+
bound = ggtt->flags & XE_GGTT_FLAGS_ONLINE;
423
417
if (bound)
424
418
xe_ggtt_clear(ggtt, node->base.start, node->base.size);
425
419
drm_mm_remove_node(&node->base);
···
428
428
429
429
if (node->invalidate_on_remove)
430
430
xe_ggtt_invalidate(ggtt);
431
-
432
-
drm_dev_exit(idx);
433
431
434
432
free_node:
435
433
xe_ggtt_node_fini(node);
+4
-1
drivers/gpu/drm/xe/xe_ggtt_types.h
+4
-1
drivers/gpu/drm/xe/xe_ggtt_types.h
···
28
28
/** @size: Total usable size of this GGTT */
29
29
u64 size;
30
30
31
-
#define XE_GGTT_FLAGS_64K BIT(0)
31
+
#define XE_GGTT_FLAGS_64K BIT(0)
32
+
#define XE_GGTT_FLAGS_ONLINE BIT(1)
32
33
/**
33
34
* @flags: Flags for this GGTT
34
35
* Acceptable flags:
35
36
* - %XE_GGTT_FLAGS_64K - if PTE size is 64K. Otherwise, regular is 4K.
37
+
* - %XE_GGTT_FLAGS_ONLINE - is GGTT online, protected by ggtt->lock
38
+
* after init
36
39
*/
37
40
unsigned int flags;
38
41
/** @scratch: Internal object allocation used as a scratch page */
+2
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+2
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
···
12
12
#include "xe_gt_printk.h"
13
13
#include "xe_gt_sysfs.h"
14
14
#include "xe_mmio.h"
15
+
#include "xe_pm.h"
15
16
#include "xe_sriov.h"
16
17
17
18
static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
···
151
150
xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);
152
151
gt->ccs_mode = num_engines;
153
152
xe_gt_record_user_engines(gt);
153
+
guard(xe_pm_runtime)(xe);
154
154
xe_gt_reset(gt);
155
155
}
156
156
+27
-5
drivers/gpu/drm/xe/xe_guc.c
+27
-5
drivers/gpu/drm/xe/xe_guc.c
···
1124
1124
struct xe_guc_pc *guc_pc = >->uc.guc.pc;
1125
1125
u32 before_freq, act_freq, cur_freq;
1126
1126
u32 status = 0, tries = 0;
1127
+
int load_result, ret;
1127
1128
ktime_t before;
1128
1129
u64 delta_ms;
1129
-
int ret;
1130
1130
1131
1131
before_freq = xe_guc_pc_get_act_freq(guc_pc);
1132
1132
before = ktime_get();
1133
1133
1134
-
ret = poll_timeout_us(ret = guc_load_done(gt, &status, &tries), ret,
1134
+
ret = poll_timeout_us(load_result = guc_load_done(gt, &status, &tries), load_result,
1135
1135
10 * USEC_PER_MSEC,
1136
1136
GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false);
1137
1137
···
1139
1139
act_freq = xe_guc_pc_get_act_freq(guc_pc);
1140
1140
cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc);
1141
1141
1142
-
if (ret) {
1142
+
if (ret || load_result <= 0) {
1143
1143
xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n",
1144
1144
status, delta_ms, xe_guc_pc_get_act_freq(guc_pc),
1145
1145
xe_guc_pc_get_cur_freq_fw(guc_pc));
···
1347
1347
return 0;
1348
1348
}
1349
1349
1350
-
int xe_guc_suspend(struct xe_guc *guc)
1350
+
/**
1351
+
* xe_guc_softreset() - Soft reset GuC
1352
+
* @guc: The GuC object
1353
+
*
1354
+
* Send soft reset command to GuC through mmio send.
1355
+
*
1356
+
* Return: 0 if success, otherwise error code
1357
+
*/
1358
+
int xe_guc_softreset(struct xe_guc *guc)
1351
1359
{
1352
-
struct xe_gt *gt = guc_to_gt(guc);
1353
1360
u32 action[] = {
1354
1361
XE_GUC_ACTION_CLIENT_SOFT_RESET,
1355
1362
};
1356
1363
int ret;
1357
1364
1365
+
if (!xe_uc_fw_is_running(&guc->fw))
1366
+
return 0;
1367
+
1358
1368
ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action));
1369
+
if (ret)
1370
+
return ret;
1371
+
1372
+
return 0;
1373
+
}
1374
+
1375
+
int xe_guc_suspend(struct xe_guc *guc)
1376
+
{
1377
+
struct xe_gt *gt = guc_to_gt(guc);
1378
+
int ret;
1379
+
1380
+
ret = xe_guc_softreset(guc);
1359
1381
if (ret) {
1360
1382
xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret));
1361
1383
return ret;
+1
drivers/gpu/drm/xe/xe_guc.h
+1
drivers/gpu/drm/xe/xe_guc.h
···
44
44
void xe_guc_runtime_suspend(struct xe_guc *guc);
45
45
void xe_guc_runtime_resume(struct xe_guc *guc);
46
46
int xe_guc_suspend(struct xe_guc *guc);
47
+
int xe_guc_softreset(struct xe_guc *guc);
47
48
void xe_guc_notify(struct xe_guc *guc);
48
49
int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
49
50
int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
+1
drivers/gpu/drm/xe/xe_guc_ct.c
+1
drivers/gpu/drm/xe/xe_guc_ct.c
+61
-25
drivers/gpu/drm/xe/xe_guc_submit.c
+61
-25
drivers/gpu/drm/xe/xe_guc_submit.c
···
48
48
49
49
#define XE_GUC_EXEC_QUEUE_CGP_CONTEXT_ERROR_LEN 6
50
50
51
+
static int guc_submit_reset_prepare(struct xe_guc *guc);
52
+
51
53
static struct xe_guc *
52
54
exec_queue_to_guc(struct xe_exec_queue *q)
53
55
{
···
241
239
EXEC_QUEUE_STATE_BANNED));
242
240
}
243
241
244
-
static void guc_submit_fini(struct drm_device *drm, void *arg)
242
+
static void guc_submit_sw_fini(struct drm_device *drm, void *arg)
245
243
{
246
244
struct xe_guc *guc = arg;
247
245
struct xe_device *xe = guc_to_xe(guc);
···
257
255
xe_gt_assert(gt, ret);
258
256
259
257
xa_destroy(&guc->submission_state.exec_queue_lookup);
258
+
}
259
+
260
+
static void guc_submit_fini(void *arg)
261
+
{
262
+
struct xe_guc *guc = arg;
263
+
264
+
/* Forcefully kill any remaining exec queues */
265
+
xe_guc_ct_stop(&guc->ct);
266
+
guc_submit_reset_prepare(guc);
267
+
xe_guc_softreset(guc);
268
+
xe_guc_submit_stop(guc);
269
+
xe_uc_fw_sanitize(&guc->fw);
270
+
xe_guc_submit_pause_abort(guc);
260
271
}
261
272
262
273
static void guc_submit_wedged_fini(void *arg)
···
341
326
342
327
guc->submission_state.initialized = true;
343
328
344
-
return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);
329
+
err = drmm_add_action_or_reset(&xe->drm, guc_submit_sw_fini, guc);
330
+
if (err)
331
+
return err;
332
+
333
+
return devm_add_action_or_reset(xe->drm.dev, guc_submit_fini, guc);
345
334
}
346
335
347
336
/*
···
1271
1252
*/
1272
1253
void xe_guc_submit_wedge(struct xe_guc *guc)
1273
1254
{
1255
+
struct xe_device *xe = guc_to_xe(guc);
1274
1256
struct xe_gt *gt = guc_to_gt(guc);
1275
1257
struct xe_exec_queue *q;
1276
1258
unsigned long index;
···
1286
1266
if (!guc->submission_state.initialized)
1287
1267
return;
1288
1268
1289
-
err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
1290
-
guc_submit_wedged_fini, guc);
1291
-
if (err) {
1292
-
xe_gt_err(gt, "Failed to register clean-up in wedged.mode=%s; "
1293
-
"Although device is wedged.\n",
1294
-
xe_wedged_mode_to_string(XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET));
1295
-
return;
1296
-
}
1269
+
if (xe->wedged.mode == 2) {
1270
+
err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
1271
+
guc_submit_wedged_fini, guc);
1272
+
if (err) {
1273
+
xe_gt_err(gt, "Failed to register clean-up on wedged.mode=2; "
1274
+
"Although device is wedged.\n");
1275
+
return;
1276
+
}
1297
1277
1298
-
mutex_lock(&guc->submission_state.lock);
1299
-
xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1300
-
if (xe_exec_queue_get_unless_zero(q))
1301
-
set_exec_queue_wedged(q);
1302
-
mutex_unlock(&guc->submission_state.lock);
1278
+
mutex_lock(&guc->submission_state.lock);
1279
+
xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1280
+
if (xe_exec_queue_get_unless_zero(q))
1281
+
set_exec_queue_wedged(q);
1282
+
mutex_unlock(&guc->submission_state.lock);
1283
+
} else {
1284
+
/* Forcefully kill any remaining exec queues, signal fences */
1285
+
guc_submit_reset_prepare(guc);
1286
+
xe_guc_submit_stop(guc);
1287
+
xe_guc_softreset(guc);
1288
+
xe_uc_fw_sanitize(&guc->fw);
1289
+
xe_guc_submit_pause_abort(guc);
1290
+
}
1303
1291
}
1304
1292
1305
1293
static bool guc_submit_hint_wedged(struct xe_guc *guc)
···
2258
2230
static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
2259
2231
{
2260
2232
struct xe_gpu_scheduler *sched = &q->guc->sched;
2233
+
bool do_destroy = false;
2261
2234
2262
2235
/* Stop scheduling + flush any DRM scheduler operations */
2263
2236
xe_sched_submission_stop(sched);
···
2266
2237
/* Clean up lost G2H + reset engine state */
2267
2238
if (exec_queue_registered(q)) {
2268
2239
if (exec_queue_destroyed(q))
2269
-
__guc_exec_queue_destroy(guc, q);
2240
+
do_destroy = true;
2270
2241
}
2271
2242
if (q->guc->suspend_pending) {
2272
2243
set_exec_queue_suspended(q);
···
2302
2273
xe_guc_exec_queue_trigger_cleanup(q);
2303
2274
}
2304
2275
}
2276
+
2277
+
if (do_destroy)
2278
+
__guc_exec_queue_destroy(guc, q);
2305
2279
}
2306
2280
2307
-
int xe_guc_submit_reset_prepare(struct xe_guc *guc)
2281
+
static int guc_submit_reset_prepare(struct xe_guc *guc)
2308
2282
{
2309
2283
int ret;
2310
-
2311
-
if (xe_gt_WARN_ON(guc_to_gt(guc), vf_recovery(guc)))
2312
-
return 0;
2313
-
2314
-
if (!guc->submission_state.initialized)
2315
-
return 0;
2316
2284
2317
2285
/*
2318
2286
* Using an atomic here rather than submission_state.lock as this
···
2323
2297
wake_up_all(&guc->ct.wq);
2324
2298
2325
2299
return ret;
2300
+
}
2301
+
2302
+
int xe_guc_submit_reset_prepare(struct xe_guc *guc)
2303
+
{
2304
+
if (xe_gt_WARN_ON(guc_to_gt(guc), vf_recovery(guc)))
2305
+
return 0;
2306
+
2307
+
if (!guc->submission_state.initialized)
2308
+
return 0;
2309
+
2310
+
return guc_submit_reset_prepare(guc);
2326
2311
}
2327
2312
2328
2313
void xe_guc_submit_reset_wait(struct xe_guc *guc)
···
2732
2695
continue;
2733
2696
2734
2697
xe_sched_submission_start(sched);
2735
-
if (exec_queue_killed_or_banned_or_wedged(q))
2736
-
xe_guc_exec_queue_trigger_cleanup(q);
2698
+
guc_exec_queue_kill(q);
2737
2699
}
2738
2700
mutex_unlock(&guc->submission_state.lock);
2739
2701
}
+2
-2
drivers/gpu/drm/xe/xe_lrc.c
+2
-2
drivers/gpu/drm/xe/xe_lrc.c
···
2413
2413
* @lrc: Pointer to the lrc.
2414
2414
*
2415
2415
* Return latest ctx timestamp. With support for active contexts, the
2416
-
* calculation may bb slightly racy, so follow a read-again logic to ensure that
2416
+
* calculation may be slightly racy, so follow a read-again logic to ensure that
2417
2417
* the context is still active before returning the right timestamp.
2418
2418
*
2419
2419
* Returns: New ctx timestamp value
2420
2420
*/
2421
2421
u64 xe_lrc_timestamp(struct xe_lrc *lrc)
2422
2422
{
2423
-
u64 lrc_ts, reg_ts, new_ts;
2423
+
u64 lrc_ts, reg_ts, new_ts = lrc->ctx_timestamp;
2424
2424
u32 engine_id;
2425
2425
2426
2426
lrc_ts = xe_lrc_ctx_timestamp(lrc);
+5
-2
drivers/gpu/drm/xe/xe_oa.c
+5
-2
drivers/gpu/drm/xe/xe_oa.c
···
543
543
size_t offset = 0;
544
544
int ret;
545
545
546
-
/* Can't read from disabled streams */
547
-
if (!stream->enabled || !stream->sample)
546
+
if (!stream->sample)
548
547
return -EINVAL;
549
548
550
549
if (!(file->f_flags & O_NONBLOCK)) {
···
1459
1460
1460
1461
if (stream->sample)
1461
1462
hrtimer_cancel(&stream->poll_check_timer);
1463
+
1464
+
/* Update stream->oa_buffer.tail to allow any final reports to be read */
1465
+
if (xe_oa_buffer_check_unlocked(stream))
1466
+
wake_up(&stream->poll_wq);
1462
1467
}
1463
1468
1464
1469
static int xe_oa_enable_preempt_timeslice(struct xe_oa_stream *stream)
+29
-9
drivers/gpu/drm/xe/xe_pt.c
+29
-9
drivers/gpu/drm/xe/xe_pt.c
···
1655
1655
XE_WARN_ON(!level);
1656
1656
/* Check for leaf node */
1657
1657
if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
1658
-
(!xe_child->base.children || !xe_child->base.children[first])) {
1658
+
xe_child->level <= MAX_HUGEPTE_LEVEL) {
1659
1659
struct iosys_map *leaf_map = &xe_child->bo->vmap;
1660
1660
pgoff_t count = xe_pt_num_entries(addr, next, xe_child->level, walk);
1661
1661
1662
1662
for (pgoff_t i = 0; i < count; i++) {
1663
-
u64 pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);
1663
+
u64 pte;
1664
1664
int ret;
1665
+
1666
+
/*
1667
+
* If not a leaf pt, skip unless non-leaf pt is interleaved between
1668
+
* leaf ptes which causes the page walk to skip over the child leaves
1669
+
*/
1670
+
if (xe_child->base.children && xe_child->base.children[first + i]) {
1671
+
u64 pt_size = 1ULL << walk->shifts[xe_child->level];
1672
+
bool edge_pt = (i == 0 && !IS_ALIGNED(addr, pt_size)) ||
1673
+
(i == count - 1 && !IS_ALIGNED(next, pt_size));
1674
+
1675
+
if (!edge_pt) {
1676
+
xe_page_reclaim_list_abort(xe_walk->tile->primary_gt,
1677
+
xe_walk->prl,
1678
+
"PT is skipped by walk at level=%u offset=%lu",
1679
+
xe_child->level, first + i);
1680
+
break;
1681
+
}
1682
+
continue;
1683
+
}
1684
+
1685
+
pte = xe_map_rd(xe, leaf_map, (first + i) * sizeof(u64), u64);
1665
1686
1666
1687
/*
1667
1688
* In rare scenarios, pte may not be written yet due to racy conditions.
···
1695
1674
}
1696
1675
1697
1676
/* Ensure it is a defined page */
1698
-
xe_tile_assert(xe_walk->tile,
1699
-
xe_child->level == 0 ||
1700
-
(pte & (XE_PTE_PS64 | XE_PDE_PS_2M | XE_PDPE_PS_1G)));
1677
+
xe_tile_assert(xe_walk->tile, xe_child->level == 0 ||
1678
+
(pte & (XE_PDE_PS_2M | XE_PDPE_PS_1G)));
1701
1679
1702
1680
/* An entry should be added for 64KB but contigious 4K have XE_PTE_PS64 */
1703
1681
if (pte & XE_PTE_PS64)
···
1721
1701
killed = xe_pt_check_kill(addr, next, level - 1, xe_child, action, walk);
1722
1702
1723
1703
/*
1724
-
* Verify PRL is active and if entry is not a leaf pte (base.children conditions),
1725
-
* there is a potential need to invalidate the PRL if any PTE (num_live) are dropped.
1704
+
* Verify if any PTE are potentially dropped at non-leaf levels, either from being
1705
+
* killed or the page walk covers the region.
1726
1706
*/
1727
-
if (xe_walk->prl && level > 1 && xe_child->num_live &&
1728
-
xe_child->base.children && xe_child->base.children[first]) {
1707
+
if (xe_walk->prl && xe_page_reclaim_list_valid(xe_walk->prl) &&
1708
+
xe_child->level > MAX_HUGEPTE_LEVEL && xe_child->num_live) {
1729
1709
bool covered = xe_pt_covers(addr, next, xe_child->level, &xe_walk->base);
1730
1710
1731
1711
/*