Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: phy: micrel: Introduce lanphy_modify_page_reg
As the name suggests this function modifies the register in an
extended page. It has the same parameters as phy_modify_mmd.
This function was introduce because there are many places in the
code where the registers was read then the value was modified and
written back. So replace all this code with this function to make
it clear.
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://patch.msgid.link/20250818075121.1298170-3-horatiu.vultur@microchip.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Horatiu Vultur
and committed by
Paolo Abeni
a0de636e
54e974c7
+116
-115
+116
-115
drivers/net/phy/micrel.c
+116
-115
drivers/net/phy/micrel.c
···
2840
2840
return val;
2841
2841
}
2842
2842
2843
+
static int lanphy_modify_page_reg(struct phy_device *phydev, int page, u16 addr,
2844
+
u16 mask, u16 set)
2845
+
{
2846
+
int ret;
2847
+
2848
+
phy_lock_mdio_bus(phydev);
2849
+
__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2850
+
__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2851
+
__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2852
+
(page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2853
+
ret = __phy_modify_changed(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA,
2854
+
mask, set);
2855
+
phy_unlock_mdio_bus(phydev);
2856
+
2857
+
if (ret < 0)
2858
+
phydev_err(phydev, "__phy_modify_changed() failed: %pe\n",
2859
+
ERR_PTR(ret));
2860
+
2861
+
return ret;
2862
+
}
2863
+
2843
2864
static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2844
2865
{
2845
2866
u16 val = 0;
···
2949
2928
struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2950
2929
int txcfg = 0, rxcfg = 0;
2951
2930
int pkt_ts_enable;
2952
-
int tx_mod;
2953
2931
2954
2932
ptp_priv->hwts_tx_type = config->tx_type;
2955
2933
ptp_priv->rx_filter = config->rx_filter;
···
2995
2975
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2996
2976
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2997
2977
2998
-
tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2999
2978
if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
3000
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
3001
-
tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2979
+
lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2980
+
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
2981
+
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
3002
2982
} else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
3003
-
lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
3004
-
tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2983
+
lanphy_modify_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2984
+
PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
2985
+
0);
3005
2986
}
3006
2987
3007
2988
if (config->rx_filter != HWTSTAMP_FILTER_NONE)
···
3405
3384
static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,
3406
3385
int pulse_width)
3407
3386
{
3408
-
u16 val;
3409
-
3410
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3411
-
/* Set the pulse width of the event */
3412
-
val &= ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event));
3413
-
/* Make sure that the target clock will be incremented each time when
3387
+
/* Set the pulse width of the event,
3388
+
* Make sure that the target clock will be incremented each time when
3414
3389
* local time reaches or pass it
3390
+
* Set the polarity high
3415
3391
*/
3416
-
val |= LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width);
3417
-
val &= ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3418
-
/* Set the polarity high */
3419
-
val |= LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event);
3420
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3392
+
lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG,
3393
+
LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) |
3394
+
LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) |
3395
+
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) |
3396
+
LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event),
3397
+
LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) |
3398
+
LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event));
3421
3399
}
3422
3400
3423
3401
static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)
3424
3402
{
3425
-
u16 val;
3426
-
3427
3403
/* Set target to too far in the future, effectively disabling it */
3428
3404
lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0);
3429
3405
3430
3406
/* And then reload once it recheas the target */
3431
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3432
-
val |= LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event);
3433
-
lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3407
+
lanphy_modify_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG,
3408
+
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event),
3409
+
LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3434
3410
}
3435
3411
3436
3412
static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)
3437
3413
{
3438
-
u16 val;
3439
-
3440
3414
/* Disable gpio alternate function,
3441
3415
* 1: select as gpio,
3442
3416
* 0: select alt func
3443
3417
*/
3444
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3445
-
val |= LAN8814_GPIO_EN_BIT(pin);
3446
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3418
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3419
+
LAN8814_GPIO_EN_BIT(pin),
3420
+
LAN8814_GPIO_EN_BIT(pin));
3447
3421
3448
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3449
-
val &= ~LAN8814_GPIO_DIR_BIT(pin);
3450
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3422
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3423
+
LAN8814_GPIO_DIR_BIT(pin),
3424
+
0);
3451
3425
3452
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3453
-
val &= ~LAN8814_GPIO_BUF_BIT(pin);
3454
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3426
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin),
3427
+
LAN8814_GPIO_BUF_BIT(pin),
3428
+
0);
3455
3429
}
3456
3430
3457
3431
static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3458
3432
{
3459
-
int val;
3460
-
3461
3433
/* Set as gpio output */
3462
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3463
-
val |= LAN8814_GPIO_DIR_BIT(pin);
3464
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3434
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3435
+
LAN8814_GPIO_DIR_BIT(pin),
3436
+
LAN8814_GPIO_DIR_BIT(pin));
3465
3437
3466
3438
/* Enable gpio 0:for alternate function, 1:gpio */
3467
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3468
-
val &= ~LAN8814_GPIO_EN_BIT(pin);
3469
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3439
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3440
+
LAN8814_GPIO_EN_BIT(pin),
3441
+
0);
3470
3442
3471
3443
/* Set buffer type to push pull */
3472
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3473
-
val |= LAN8814_GPIO_BUF_BIT(pin);
3474
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3444
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin),
3445
+
LAN8814_GPIO_BUF_BIT(pin),
3446
+
LAN8814_GPIO_BUF_BIT(pin));
3475
3447
}
3476
3448
3477
3449
static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,
···
3579
3565
3580
3566
static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3581
3567
{
3582
-
u16 tmp;
3583
-
3584
3568
/* Set as gpio input */
3585
-
tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3586
-
tmp &= ~LAN8814_GPIO_DIR_BIT(pin);
3587
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3569
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3570
+
LAN8814_GPIO_DIR_BIT(pin),
3571
+
0);
3588
3572
3589
3573
/* Map the pin to ltc pin 0 of the capture map registers */
3590
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3591
-
tmp |= pin;
3592
-
lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3574
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO,
3575
+
pin,
3576
+
pin);
3593
3577
3594
3578
/* Enable capture on the edges of the ltc pin */
3595
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3596
3579
if (flags & PTP_RISING_EDGE)
3597
-
tmp |= PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0);
3580
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3581
+
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0),
3582
+
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0));
3598
3583
if (flags & PTP_FALLING_EDGE)
3599
-
tmp |= PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0);
3600
-
lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3584
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3585
+
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0),
3586
+
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0));
3601
3587
3602
3588
/* Enable interrupt top interrupt */
3603
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3604
-
tmp |= PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3605
-
lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3589
+
lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA,
3590
+
PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3591
+
PTP_COMMON_INT_ENA_GPIO_CAP_EN);
3606
3592
}
3607
3593
3608
3594
static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3609
3595
{
3610
-
u16 tmp;
3611
-
3612
3596
/* Set as gpio out */
3613
-
tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3614
-
tmp |= LAN8814_GPIO_DIR_BIT(pin);
3615
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3597
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin),
3598
+
LAN8814_GPIO_DIR_BIT(pin),
3599
+
LAN8814_GPIO_DIR_BIT(pin));
3616
3600
3617
3601
/* Enable alternate, 0:for alternate function, 1:gpio */
3618
-
tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3619
-
tmp &= ~LAN8814_GPIO_EN_BIT(pin);
3620
-
lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), tmp);
3602
+
lanphy_modify_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin),
3603
+
LAN8814_GPIO_EN_BIT(pin),
3604
+
0);
3621
3605
3622
3606
/* Clear the mapping of pin to registers 0 of the capture registers */
3623
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3624
-
tmp &= ~GENMASK(3, 0);
3625
-
lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3607
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO,
3608
+
GENMASK(3, 0),
3609
+
0);
3626
3610
3627
3611
/* Disable capture on both of the edges */
3628
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3629
-
tmp &= ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
3630
-
tmp &= ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
3631
-
lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3612
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_CAP_EN,
3613
+
PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
3614
+
PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
3615
+
0);
3632
3616
3633
3617
/* Disable interrupt top interrupt */
3634
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3635
-
tmp &= ~PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3636
-
lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3618
+
lanphy_modify_page_reg(phydev, 4, PTP_COMMON_INT_ENA,
3619
+
PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3620
+
0);
3637
3621
}
3638
3622
3639
3623
static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,
···
3871
3859
/* This is 0 because whatever was the input pin it was mapped it to
3872
3860
* ltc gpio pin 0
3873
3861
*/
3874
-
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_SEL);
3875
-
tmp |= PTP_GPIO_SEL_GPIO_SEL(0);
3876
-
lanphy_write_page_reg(phydev, 4, PTP_GPIO_SEL, tmp);
3862
+
lanphy_modify_page_reg(phydev, 4, PTP_GPIO_SEL,
3863
+
PTP_GPIO_SEL_GPIO_SEL(0),
3864
+
PTP_GPIO_SEL_GPIO_SEL(0));
3877
3865
3878
3866
tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS);
3879
3867
if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
···
3920
3908
3921
3909
static int lan8804_config_init(struct phy_device *phydev)
3922
3910
{
3923
-
int val;
3924
-
3925
3911
/* MDI-X setting for swap A,B transmit */
3926
-
val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3927
-
val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3928
-
val |= LAN8804_ALIGN_TX_A_B_SWAP;
3929
-
lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3912
+
lanphy_modify_page_reg(phydev, 2, LAN8804_ALIGN_SWAP,
3913
+
LAN8804_ALIGN_TX_A_B_SWAP_MASK,
3914
+
LAN8804_ALIGN_TX_A_B_SWAP);
3930
3915
3931
3916
/* Make sure that the PHY will not stop generating the clock when the
3932
3917
* link partner goes down
···
4065
4056
{
4066
4057
struct kszphy_priv *priv = phydev->priv;
4067
4058
struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4068
-
u32 temp;
4069
4059
4070
4060
if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
4071
4061
!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
···
4072
4064
4073
4065
lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
4074
4066
4075
-
temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
4076
-
temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
4077
-
lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
4067
+
lanphy_modify_page_reg(phydev, 5, PTP_TX_MOD,
4068
+
PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4069
+
PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4078
4070
4079
-
temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
4080
-
temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
4081
-
lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
4071
+
lanphy_modify_page_reg(phydev, 5, PTP_RX_MOD,
4072
+
PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4073
+
PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4082
4074
4083
4075
lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
4084
4076
lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
···
4204
4196
static int lan8814_config_init(struct phy_device *phydev)
4205
4197
{
4206
4198
struct kszphy_priv *lan8814 = phydev->priv;
4207
-
int val;
4208
4199
4209
4200
/* Reset the PHY */
4210
-
val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
4211
-
val |= LAN8814_QSGMII_SOFT_RESET_BIT;
4212
-
lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
4201
+
lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET,
4202
+
LAN8814_QSGMII_SOFT_RESET_BIT,
4203
+
LAN8814_QSGMII_SOFT_RESET_BIT);
4213
4204
4214
4205
/* Disable ANEG with QSGMII PCS Host side */
4215
-
val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
4216
-
val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
4217
-
lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
4206
+
lanphy_modify_page_reg(phydev, 4, LAN8814_QSGMII_PCS1G_ANEG_CONFIG,
4207
+
LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA,
4208
+
0);
4218
4209
4219
4210
/* MDI-X setting for swap A,B transmit */
4220
-
val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
4221
-
val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
4222
-
val |= LAN8814_ALIGN_TX_A_B_SWAP;
4223
-
lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
4211
+
lanphy_modify_page_reg(phydev, 2, LAN8814_ALIGN_SWAP,
4212
+
LAN8814_ALIGN_TX_A_B_SWAP_MASK,
4213
+
LAN8814_ALIGN_TX_A_B_SWAP);
4224
4214
4225
4215
if (lan8814->led_mode >= 0)
4226
4216
lan8814_setup_led(phydev, lan8814->led_mode);
···
4249
4243
4250
4244
static void lan8814_clear_2psp_bit(struct phy_device *phydev)
4251
4245
{
4252
-
u16 val;
4253
-
4254
4246
/* It was noticed that when traffic is passing through the PHY and the
4255
4247
* cable is removed then the LED was still one even though there is no
4256
4248
* link
4257
4249
*/
4258
-
val = lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE);
4259
-
val &= ~LAN8814_EEE_STATE_MASK2P5P;
4260
-
lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val);
4250
+
lanphy_modify_page_reg(phydev, 2, LAN8814_EEE_STATE,
4251
+
LAN8814_EEE_STATE_MASK2P5P,
4252
+
0);
4261
4253
}
4262
4254
4263
4255
static void lan8814_update_meas_time(struct phy_device *phydev)
4264
4256
{
4265
-
u16 val;
4266
-
4267
4257
/* By setting the measure time to a value of 0xb this will allow cables
4268
4258
* longer than 100m to be used. This configuration can be used
4269
4259
* regardless of the mode of operation of the PHY
4270
4260
*/
4271
-
val = lanphy_read_page_reg(phydev, 1, LAN8814_PD_CONTROLS);
4272
-
val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;
4273
-
val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;
4274
-
lanphy_write_page_reg(phydev, 1, LAN8814_PD_CONTROLS, val);
4261
+
lanphy_modify_page_reg(phydev, 1, LAN8814_PD_CONTROLS,
4262
+
LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK,
4263
+
LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL);
4275
4264
}
4276
4265
4277
4266
static int lan8814_probe(struct phy_device *phydev)