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media: dt-bindings: Document Renesas RZ/G2L CRU block
Document the CRU block found on Renesas RZ/G2L (and alike) SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
authored by
Lad Prabhakar
and committed by
Mauro Carvalho Chehab
a1800417
6c08bd7a
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Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
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Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2022 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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The CRU image processing module is a data conversion module equipped with pixel
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color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
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parallel (including ITU-R BT.656) input are provided as the image sensor interface.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-cru # RZ/G2{L,LC}
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- renesas,r9a07g054-cru # RZ/V2L
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- const: renesas,rzg2l-cru
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reg:
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maxItems: 1
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: image_conv
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- const: image_conv_err
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- const: axi_mst_err
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clocks:
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items:
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- description: CRU Main clock
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- description: CRU Register access clock
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- description: CRU image transfer clock
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clock-names:
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items:
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- const: video
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- const: apb
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- const: axi
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: CRU_PRESETN reset terminal
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- description: CRU_ARESETN reset terminal
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reset-names:
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items:
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- const: presetn
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- const: aresetn
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port node, single endpoint describing a parallel input source.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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hsync-active: true
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vsync-active: true
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bus-width: true
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data-shift: true
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Input port node, describing the Image Processing module connected to the
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CSI-2 receiver.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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additionalProperties: false
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examples:
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# Device node example with CSI-2
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cru: video@10830000 {
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compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
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reg = <0x10830000 0x400>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
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clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
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<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
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<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
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clock-names = "video", "apb", "axi";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_CRU_PRESETN>,
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<&cpg R9A07G044_CRU_ARESETN>;
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reset-names = "presetn", "aresetn";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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cru_parallel_in: endpoint@0 {
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reg = <0>;
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remote-endpoint= <&ov5642>;
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hsync-active = <1>;
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vsync-active = <1>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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cru_csi_in: endpoint@0 {
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reg = <0>;
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remote-endpoint= <&csi_cru_in>;
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};
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};
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};
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};