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dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms
The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Daniel Lezcano
and committed by
Jonathan Cameron
a19489ca
048a15b7
+63
+63
Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
+63
Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP Successive Approximation ADC
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description:
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The NXP SAR ADC provides fast and accurate analog-to-digital
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conversion using the Successive Approximation Register (SAR) method.
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It has 12-bit resolution with 8 input channels. Conversions can be
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launched in software or using hardware triggers. It supports
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continuous and one-shot modes with separate registers.
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maintainers:
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- Daniel Lezcano <daniel.lezcano@kernel.org>
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properties:
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compatible:
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oneOf:
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- const: nxp,s32g2-sar-adc
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- items:
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- const: nxp,s32g3-sar-adc
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- const: nxp,s32g2-sar-adc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 1
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dma-names:
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const: rx
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- dmas
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- dma-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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adc@401f8000 {
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compatible = "nxp,s32g2-sar-adc";
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reg = <0x401f8000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 0x41>;
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dmas = <&edma0 0 32>;
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dma-names = "rx";
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};