Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'there-are-some-cleanup-for-hns3-driver'
Jijie Shao says:
====================
There are some cleanup for hns3 driver
v3: https://lore.kernel.org/20250621083310.52c8e7ae@kernel.org
v2: https://lore.kernel.org/20250617010255.1183069-1-shaojijie@huawei.com
v1: https://lore.kernel.org/20250612021317.1487943-1-shaojijie@huawei.com
====================
Link: https://patch.msgid.link/20250623040043.857782-1-shaojijie@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+111
-110
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
···
348
348
static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw)
349
349
{
350
350
u32 head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
351
-
return head == hw->cmq.csq.next_to_use;
351
+
return head == (u32)hw->cmq.csq.next_to_use;
352
352
}
353
353
354
354
static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
+5
-5
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+5
-5
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
···
684
684
char *buf, int len)
685
685
{
686
686
char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
687
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
687
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
688
688
char *result[ARRAY_SIZE(rx_queue_info_items)];
689
689
struct hns3_nic_priv *priv = h->priv;
690
690
char content[HNS3_DBG_INFO_LEN];
···
789
789
char *buf, int len)
790
790
{
791
791
char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
792
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
792
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
793
793
char *result[ARRAY_SIZE(tx_queue_info_items)];
794
794
struct hns3_nic_priv *priv = h->priv;
795
795
char content[HNS3_DBG_INFO_LEN];
···
1034
1034
static void
1035
1035
hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
1036
1036
{
1037
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1037
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
1038
1038
unsigned long *caps = ae_dev->caps;
1039
1039
u32 i, state;
1040
1040
···
1239
1239
static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
1240
1240
enum hnae3_dbg_cmd cmd, char *buf, int len)
1241
1241
{
1242
-
const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops;
1242
+
const struct hnae3_ae_ops *ops = hns3_get_ops(dbg_data->handle);
1243
1243
const struct hns3_dbg_func *cmd_func;
1244
1244
u32 i;
1245
1245
···
1364
1364
1365
1365
int hns3_dbg_init(struct hnae3_handle *handle)
1366
1366
{
1367
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1367
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1368
1368
const char *name = pci_name(handle->pdev);
1369
1369
int ret;
1370
1370
u32 i;
+19
-19
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+19
-19
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
···
547
547
static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
548
548
struct hns3_nic_priv *priv)
549
549
{
550
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
551
550
struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
552
551
struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
552
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
553
553
struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
554
554
struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
555
555
···
960
960
961
961
void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
962
962
{
963
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
963
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
964
964
965
965
if (ops->request_update_promisc_mode)
966
966
ops->request_update_promisc_mode(handle);
···
1304
1304
static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1305
1305
{
1306
1306
struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1307
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1307
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
1308
1308
union l4_hdr_info l4;
1309
1309
1310
1310
/* device version above V3(include V3), the hardware can
···
1504
1504
* VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1505
1505
* will cause RAS error.
1506
1506
*/
1507
-
ae_dev = pci_get_drvdata(handle->pdev);
1507
+
ae_dev = hns3_get_ae_dev(handle);
1508
1508
if (unlikely(skb_vlan_tagged_multi(skb) &&
1509
1509
ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1510
1510
handle->port_base_vlan_state ==
···
1690
1690
#define HNS3_LIKELY_BD_NUM 1
1691
1691
1692
1692
struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1693
-
unsigned int frag_buf_num;
1694
-
int k, sizeoflast;
1693
+
unsigned int frag_buf_num, k;
1694
+
int sizeoflast;
1695
1695
1696
1696
if (likely(size <= HNS3_MAX_BD_SIZE)) {
1697
1697
desc->addr = cpu_to_le64(dma);
···
1863
1863
unsigned int bd_num, u8 max_non_tso_bd_num)
1864
1864
{
1865
1865
unsigned int tot_len = 0;
1866
-
int i;
1866
+
unsigned int i;
1867
1867
1868
1868
for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1869
1869
tot_len += bd_size[i];
···
1891
1891
1892
1892
void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1893
1893
{
1894
-
int i;
1894
+
u32 i;
1895
1895
1896
1896
for (i = 0; i < MAX_SKB_FRAGS; i++)
1897
1897
size[i] = skb_frag_size(&shinfo->frags[i]);
···
2207
2207
struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2208
2208
u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2209
2209
struct sg_table *sgt;
2210
-
int i, bd_num = 0;
2210
+
int bd_num = 0;
2211
2211
dma_addr_t dma;
2212
-
u32 cb_len;
2212
+
u32 cb_len, i;
2213
2213
int nents;
2214
2214
2215
2215
if (skb_has_frag_list(skb))
···
2447
2447
if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2448
2448
h->ae_algo->ops->cls_flower_active(h)) {
2449
2449
netdev_err(netdev,
2450
-
"there are offloaded TC filters active, cannot disable HW TC offload");
2450
+
"there are offloaded TC filters active, cannot disable HW TC offload\n");
2451
2451
return -EINVAL;
2452
2452
}
2453
2453
···
2544
2544
struct hnae3_handle *handle = priv->ae_handle;
2545
2545
struct rtnl_link_stats64 ring_total_stats;
2546
2546
struct hns3_enet_ring *ring;
2547
-
unsigned int idx;
2547
+
int idx;
2548
2548
2549
2549
if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2550
2550
return;
···
2770
2770
2771
2771
static int hns3_get_timeout_queue(struct net_device *ndev)
2772
2772
{
2773
-
int i;
2773
+
unsigned int i;
2774
2774
2775
2775
/* Find the stopped queue the same way the stack does */
2776
2776
for (i = 0; i < ndev->num_tx_queues; i++) {
···
2851
2851
struct hns3_nic_priv *priv = netdev_priv(ndev);
2852
2852
struct hnae3_handle *h = hns3_get_handle(ndev);
2853
2853
struct hns3_enet_ring *tx_ring;
2854
-
int timeout_queue;
2854
+
u32 timeout_queue;
2855
2855
2856
2856
timeout_queue = hns3_get_timeout_queue(ndev);
2857
2857
if (timeout_queue >= ndev->num_tx_queues) {
···
3821
3821
{
3822
3822
__be16 type = skb->protocol;
3823
3823
struct tcphdr *th;
3824
-
int depth = 0;
3824
+
u32 depth = 0;
3825
3825
3826
3826
while (eth_type_vlan(type)) {
3827
3827
struct vlan_hdr *vh;
···
4747
4747
4748
4748
static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4749
4749
{
4750
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4750
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4751
4751
struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4752
4752
struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4753
4753
···
5226
5226
static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5227
5227
enum dim_cq_period_mode mode, bool is_tx)
5228
5228
{
5229
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5229
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
5230
5230
struct hnae3_handle *handle = priv->ae_handle;
5231
5231
int i;
5232
5232
···
5264
5264
5265
5265
static void hns3_state_init(struct hnae3_handle *handle)
5266
5266
{
5267
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5267
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
5268
5268
struct net_device *netdev = handle->kinfo.netdev;
5269
5269
struct hns3_nic_priv *priv = netdev_priv(netdev);
5270
5270
···
5934
5934
static void hns3_process_hw_error(struct hnae3_handle *handle,
5935
5935
enum hnae3_hw_error_type type)
5936
5936
{
5937
-
int i;
5937
+
u32 i;
5938
5938
5939
5939
for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5940
5940
if (hns3_hw_err[i].type == type) {
+2
-2
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+2
-2
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
···
621
621
enum hnae3_reset_type rst_type;
622
622
};
623
623
624
-
static inline int ring_space(struct hns3_enet_ring *ring)
624
+
static inline u32 ring_space(struct hns3_enet_ring *ring)
625
625
{
626
626
/* This smp_load_acquire() pairs with smp_store_release() in
627
627
* hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
···
692
692
693
693
/* iterator for handling rings in ring group */
694
694
#define hns3_for_each_ring(pos, head) \
695
-
for (pos = (head).ring; (pos); pos = (pos)->next)
695
+
for ((pos) = (head).ring; (pos); (pos) = (pos)->next)
696
696
697
697
#define hns3_get_handle(ndev) \
698
698
(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
+37
-37
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+37
-37
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
···
86
86
static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en)
87
87
{
88
88
struct hnae3_handle *h = hns3_get_handle(ndev);
89
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
89
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
90
90
int ret;
91
91
92
92
if (!h->ae_algo->ops->set_loopback ||
···
171
171
* the purpose of mac or serdes selftest.
172
172
*/
173
173
handle = hns3_get_handle(ndev);
174
-
ae_dev = pci_get_drvdata(handle->pdev);
174
+
ae_dev = hns3_get_ae_dev(handle);
175
175
if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
176
176
ethh->h_dest[5] += HNS3_NIC_LB_DST_MAC_ADDR;
177
177
eth_zero_addr(ethh->h_source);
···
436
436
data[i] = HNS3_NIC_LB_TEST_UNEXECUTED;
437
437
438
438
if (hns3_nic_resetting(ndev)) {
439
-
netdev_err(ndev, "dev resetting!");
439
+
netdev_err(ndev, "dev resetting!\n");
440
440
goto failure;
441
441
}
442
442
···
489
489
static int hns3_get_sset_count(struct net_device *netdev, int stringset)
490
490
{
491
491
struct hnae3_handle *h = hns3_get_handle(netdev);
492
-
const struct hnae3_ae_ops *ops = h->ae_algo->ops;
492
+
const struct hnae3_ae_ops *ops = hns3_get_ops(h);
493
493
494
494
if (!ops->get_sset_count)
495
495
return -EOPNOTSUPP;
···
540
540
static void hns3_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
541
541
{
542
542
struct hnae3_handle *h = hns3_get_handle(netdev);
543
-
const struct hnae3_ae_ops *ops = h->ae_algo->ops;
544
-
int i;
543
+
const struct hnae3_ae_ops *ops = hns3_get_ops(h);
544
+
u32 i;
545
545
546
546
if (!ops->get_strings)
547
547
return;
···
569
569
struct hns3_nic_priv *nic_priv = handle->priv;
570
570
struct hns3_enet_ring *ring;
571
571
u8 *stat;
572
-
int i, j;
572
+
u32 i, j;
573
573
574
574
/* get stats for Tx */
575
575
for (i = 0; i < kinfo->num_tqps; i++) {
···
692
692
struct ethtool_pauseparam *param)
693
693
{
694
694
struct hnae3_handle *h = hns3_get_handle(netdev);
695
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
695
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
696
696
697
697
if (!test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps))
698
698
return;
···
706
706
struct ethtool_pauseparam *param)
707
707
{
708
708
struct hnae3_handle *h = hns3_get_handle(netdev);
709
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
709
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
710
710
711
711
if (!test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps))
712
712
return -EOPNOTSUPP;
···
725
725
static void hns3_get_ksettings(struct hnae3_handle *h,
726
726
struct ethtool_link_ksettings *cmd)
727
727
{
728
-
const struct hnae3_ae_ops *ops = h->ae_algo->ops;
728
+
const struct hnae3_ae_ops *ops = hns3_get_ops(h);
729
729
730
730
/* 1.auto_neg & speed & duplex from cmd */
731
731
if (ops->get_ksettings_an_result)
···
751
751
struct ethtool_link_ksettings *cmd)
752
752
{
753
753
struct hnae3_handle *h = hns3_get_handle(netdev);
754
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
754
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
755
755
const struct hnae3_ae_ops *ops;
756
756
u8 module_type;
757
757
u8 media_type;
···
794
794
break;
795
795
default:
796
796
797
-
netdev_warn(netdev, "Unknown media type");
797
+
netdev_warn(netdev, "Unknown media type\n");
798
798
return 0;
799
799
}
800
800
···
814
814
const struct ethtool_link_ksettings *cmd)
815
815
{
816
816
struct hnae3_handle *handle = hns3_get_handle(netdev);
817
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
817
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
818
818
u8 module_type = HNAE3_MODULE_TYPE_UNKNOWN;
819
819
u8 media_type = HNAE3_MEDIA_TYPE_UNKNOWN;
820
820
u32 lane_num;
···
842
842
if (cmd->base.duplex == DUPLEX_HALF &&
843
843
media_type != HNAE3_MEDIA_TYPE_COPPER) {
844
844
netdev_err(netdev,
845
-
"only copper port supports half duplex!");
845
+
"only copper port supports half duplex!\n");
846
846
return -EINVAL;
847
847
}
848
848
···
861
861
const struct ethtool_link_ksettings *cmd)
862
862
{
863
863
struct hnae3_handle *handle = hns3_get_handle(netdev);
864
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
865
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
864
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
865
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
866
866
int ret;
867
867
868
868
/* Chip don't support this mode. */
···
932
932
static u32 hns3_get_rss_indir_size(struct net_device *netdev)
933
933
{
934
934
struct hnae3_handle *h = hns3_get_handle(netdev);
935
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
935
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
936
936
937
937
return ae_dev->dev_specs.rss_ind_tbl_size;
938
938
}
···
954
954
struct netlink_ext_ack *extack)
955
955
{
956
956
struct hnae3_handle *h = hns3_get_handle(netdev);
957
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
957
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
958
958
959
959
if (!h->ae_algo->ops->set_rss)
960
960
return -EOPNOTSUPP;
···
1030
1030
{
1031
1031
enum hnae3_reset_type rst_type = HNAE3_NONE_RESET;
1032
1032
struct hnae3_handle *h = hns3_get_handle(netdev);
1033
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1034
-
const struct hnae3_ae_ops *ops = h->ae_algo->ops;
1033
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
1034
+
const struct hnae3_ae_ops *ops = hns3_get_ops(h);
1035
1035
const struct hns3_reset_type_map *rst_type_map;
1036
1036
enum ethtool_reset_flags rst_flags;
1037
1037
u32 i, size;
···
1195
1195
{
1196
1196
struct hns3_nic_priv *priv = netdev_priv(netdev);
1197
1197
struct hnae3_handle *h = hns3_get_handle(netdev);
1198
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1198
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(h);
1199
1199
u32 old_state = test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
1200
1200
1201
1201
if (!test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps) && tx_push)
···
1313
1313
static int hns3_nway_reset(struct net_device *netdev)
1314
1314
{
1315
1315
struct hnae3_handle *handle = hns3_get_handle(netdev);
1316
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1316
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1317
1317
struct phy_device *phy = netdev->phydev;
1318
1318
int autoneg;
1319
1319
···
1321
1321
return 0;
1322
1322
1323
1323
if (hns3_nic_resetting(netdev)) {
1324
-
netdev_err(netdev, "dev resetting!");
1324
+
netdev_err(netdev, "dev resetting!\n");
1325
1325
return -EBUSY;
1326
1326
}
1327
1327
···
1390
1390
struct ethtool_coalesce *cmd)
1391
1391
{
1392
1392
struct hnae3_handle *handle = hns3_get_handle(netdev);
1393
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1393
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1394
1394
u32 rx_gl, tx_gl;
1395
1395
1396
1396
if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {
···
1462
1462
struct ethtool_coalesce *cmd)
1463
1463
{
1464
1464
struct hnae3_handle *handle = hns3_get_handle(netdev);
1465
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1465
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1466
1466
1467
1467
if ((cmd->tx_max_coalesced_frames || cmd->rx_max_coalesced_frames) &&
1468
1468
!ae_dev->dev_specs.int_ql_max) {
···
1486
1486
struct kernel_ethtool_coalesce *kernel_coal)
1487
1487
{
1488
1488
struct hnae3_handle *handle = hns3_get_handle(netdev);
1489
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1489
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1490
1490
1491
1491
if ((kernel_coal->use_cqe_mode_tx || kernel_coal->use_cqe_mode_rx) &&
1492
1492
!hnae3_ae_dev_cq_supported(ae_dev)) {
···
1662
1662
struct ethtool_fec_stats *fec_stats)
1663
1663
{
1664
1664
struct hnae3_handle *handle = hns3_get_handle(netdev);
1665
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1666
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1665
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1666
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1667
1667
1668
1668
if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || !ops->get_fec_stats)
1669
1669
return;
···
1713
1713
struct ethtool_fecparam *fec)
1714
1714
{
1715
1715
struct hnae3_handle *handle = hns3_get_handle(netdev);
1716
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1717
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1716
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1717
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1718
1718
u8 fec_ability;
1719
1719
u8 fec_mode;
1720
1720
···
1738
1738
struct ethtool_fecparam *fec)
1739
1739
{
1740
1740
struct hnae3_handle *handle = hns3_get_handle(netdev);
1741
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1742
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1741
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1742
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1743
1743
u32 fec_mode;
1744
1744
1745
1745
if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps))
···
1760
1760
#define HNS3_SFF_8636_V1_3 0x03
1761
1761
1762
1762
struct hnae3_handle *handle = hns3_get_handle(netdev);
1763
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1764
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1763
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1764
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1765
1765
struct hns3_sfp_type sfp_type;
1766
1766
int ret;
1767
1767
···
1810
1810
struct ethtool_eeprom *ee, u8 *data)
1811
1811
{
1812
1812
struct hnae3_handle *handle = hns3_get_handle(netdev);
1813
-
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1814
-
const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1813
+
struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
1814
+
const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
1815
1815
1816
1816
if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
1817
1817
!ops->get_module_eeprom)
···
1937
1937
int i, ret = 0;
1938
1938
1939
1939
if (hns3_nic_resetting(netdev) || !priv->ring) {
1940
-
netdev_err(netdev, "failed to set tunable value, dev resetting!");
1940
+
netdev_err(netdev, "failed to set tunable value, dev resetting!\n");
1941
1941
return -EBUSY;
1942
1942
}
1943
1943
+7
-8
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+7
-8
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
···
830
830
{
831
831
const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
832
832
const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg;
833
+
u32 index, entry, i, cnt, min_num;
833
834
struct hclge_desc *desc_src;
834
-
u32 index, entry, i, cnt;
835
-
int bd_num, min_num, ret;
836
835
struct hclge_desc *desc;
836
+
int bd_num, ret;
837
837
838
838
ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
839
839
if (ret)
···
885
885
const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg;
886
886
const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
887
887
struct hclge_desc *desc_src;
888
-
int bd_num, min_num, ret;
888
+
int bd_num, min_num, ret, i;
889
889
struct hclge_desc *desc;
890
-
u32 entry, i;
890
+
u32 entry;
891
891
892
892
ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
893
893
if (ret)
···
1279
1279
{
1280
1280
const struct hclge_dbg_reg_type_info *reg_info;
1281
1281
int pos = 0, ret = 0;
1282
-
int i;
1282
+
u32 i;
1283
1283
1284
1284
for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) {
1285
1285
reg_info = &hclge_dbg_reg_info[i];
···
2110
2110
for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) {
2111
2111
hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD,
2112
2112
true);
2113
-
req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data;
2113
+
req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)desc.data;
2114
2114
req0->index = cpu_to_le16(i);
2115
2115
2116
2116
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
···
2648
2648
struct hclge_mac_node *mac_node, *tmp;
2649
2649
struct hclge_vport *vport;
2650
2650
struct list_head *list;
2651
-
u32 func_id;
2651
+
u32 func_id, i;
2652
2652
int pos = 0;
2653
-
int i;
2654
2653
2655
2654
for (i = 0; i < ARRAY_SIZE(mac_list_items); i++)
2656
2655
result[i] = &data_str[i][0];
+17
-17
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+17
-17
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
···
582
582
int size, u64 *data)
583
583
{
584
584
u64 *buf = data;
585
-
u32 i;
585
+
int i;
586
586
587
587
for (i = 0; i < size; i++) {
588
588
if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
···
599
599
const struct hclge_comm_stats_str strs[],
600
600
int size, u8 **data)
601
601
{
602
-
u32 i;
602
+
int i;
603
603
604
604
if (stringset != ETH_SS_STATS)
605
605
return;
···
2358
2358
for (i = 0; i < 2; i++) {
2359
2359
hclge_cmd_setup_basic_desc(&desc[i],
2360
2360
HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2361
-
req = (struct hclge_rx_com_thrd *)&desc[i].data;
2361
+
req = (struct hclge_rx_com_thrd *)desc[i].data;
2362
2362
2363
2363
/* The first descriptor set the NEXT bit to 1 */
2364
2364
if (i == 0)
···
2624
2624
int ret;
2625
2625
2626
2626
duplex = hclge_check_speed_dup(duplex, speed);
2627
-
if (!mac->support_autoneg && mac->speed == speed &&
2627
+
if (!mac->support_autoneg && mac->speed == (u32)speed &&
2628
2628
mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0))
2629
2629
return 0;
2630
2630
···
2652
2652
if (ret)
2653
2653
return ret;
2654
2654
2655
-
hdev->hw.mac.req_speed = speed;
2655
+
hdev->hw.mac.req_speed = (u32)speed;
2656
2656
hdev->hw.mac.req_duplex = duplex;
2657
2657
2658
2658
return 0;
···
3446
3446
static int hclge_update_port_info(struct hclge_dev *hdev)
3447
3447
{
3448
3448
struct hclge_mac *mac = &hdev->hw.mac;
3449
-
int speed;
3449
+
u32 speed;
3450
3450
int ret;
3451
3451
3452
3452
/* get the port info from SFP cmd if not copper port */
···
6989
6989
struct hclge_dev *hdev = vport->back;
6990
6990
struct hclge_fd_rule *rule;
6991
6991
struct hlist_node *node2;
6992
-
int cnt = 0;
6992
+
u32 cnt = 0;
6993
6993
6994
6994
if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6995
6995
return -EOPNOTSUPP;
···
8223
8223
word_num = vfid / 32;
8224
8224
bit_num = vfid % 32;
8225
8225
if (clr)
8226
-
desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8226
+
desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num));
8227
8227
else
8228
8228
desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
8229
8229
} else {
8230
8230
word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
8231
8231
bit_num = vfid % 32;
8232
8232
if (clr)
8233
-
desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8233
+
desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num));
8234
8234
else
8235
8235
desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
8236
8236
}
···
9292
9292
static int init_mgr_tbl(struct hclge_dev *hdev)
9293
9293
{
9294
9294
int ret;
9295
-
int i;
9295
+
u32 i;
9296
9296
9297
9297
for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9298
9298
ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
···
10713
10713
max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10714
10714
mutex_lock(&hdev->vport_lock);
10715
10715
/* VF's mps must fit within hdev->mps */
10716
-
if (vport->vport_id && max_frm_size > hdev->mps) {
10716
+
if (vport->vport_id && (u32)max_frm_size > hdev->mps) {
10717
10717
mutex_unlock(&hdev->vport_lock);
10718
10718
return -EINVAL;
10719
10719
} else if (vport->vport_id) {
···
10724
10724
10725
10725
/* PF's mps must be greater then VF's mps */
10726
10726
for (i = 1; i < hdev->num_alloc_vport; i++)
10727
-
if (max_frm_size < hdev->vport[i].mps) {
10727
+
if ((u32)max_frm_size < hdev->vport[i].mps) {
10728
10728
dev_err(&hdev->pdev->dev,
10729
10729
"failed to set pf mtu for less than vport %d, mps = %u.\n",
10730
10730
i, hdev->vport[i].mps);
···
11214
11214
{
11215
11215
struct hnae3_client *client = vport->nic.client;
11216
11216
struct hclge_dev *hdev = ae_dev->priv;
11217
-
int rst_cnt = hdev->rst_stats.reset_cnt;
11217
+
u32 rst_cnt = hdev->rst_stats.reset_cnt;
11218
11218
int ret;
11219
11219
11220
11220
ret = client->ops->init_instance(&vport->nic);
···
11258
11258
{
11259
11259
struct hclge_dev *hdev = ae_dev->priv;
11260
11260
struct hnae3_client *client;
11261
-
int rst_cnt;
11261
+
u32 rst_cnt;
11262
11262
int ret;
11263
11263
11264
11264
if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
···
11423
11423
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11424
11424
if (ret) {
11425
11425
dev_err(&pdev->dev,
11426
-
"can't set consistent PCI DMA");
11426
+
"can't set consistent PCI DMA\n");
11427
11427
goto err_disable_device;
11428
11428
}
11429
11429
dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
···
12088
12088
int min_tx_rate, int max_tx_rate)
12089
12089
{
12090
12090
if (min_tx_rate != 0 ||
12091
-
max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) {
12091
+
max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) {
12092
12092
dev_err(&hdev->pdev->dev,
12093
12093
"min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
12094
12094
min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
···
12113
12113
if (!vport)
12114
12114
return -EINVAL;
12115
12115
12116
-
if (!force && max_tx_rate == vport->vf_info.max_tx_rate)
12116
+
if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate)
12117
12117
return 0;
12118
12118
12119
12119
ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
+4
-3
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+4
-3
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
···
749
749
#define HCLGE_RSS_MBX_RESP_LEN 8
750
750
struct hclge_dev *hdev = vport->back;
751
751
struct hclge_comm_rss_cfg *rss_cfg;
752
+
int rss_hash_key_size;
752
753
u8 index;
753
754
754
755
index = mbx_req->msg.data[0];
755
756
rss_cfg = &hdev->rss_cfg;
757
+
rss_hash_key_size = sizeof(rss_cfg->rss_hash_key);
756
758
757
759
/* Check the query index of rss_hash_key from VF, make sure no
758
760
* more than the size of rss_hash_key.
759
761
*/
760
-
if (((index + 1) * HCLGE_RSS_MBX_RESP_LEN) >
761
-
sizeof(rss_cfg->rss_hash_key)) {
762
+
if (((index + 1) * HCLGE_RSS_MBX_RESP_LEN) > rss_hash_key_size) {
762
763
dev_warn(&hdev->pdev->dev,
763
764
"failed to get the rss hash key, the index(%u) invalid !\n",
764
765
index);
···
801
800
802
801
static bool hclge_cmd_crq_empty(struct hclge_hw *hw)
803
802
{
804
-
u32 tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
803
+
int tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
805
804
806
805
return tail == hw->hw.cmq.crq.next_to_use;
807
806
}
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
···
25
25
#define HCLGE_PTP_TIME_SEC_H_MASK GENMASK(15, 0)
26
26
#define HCLGE_PTP_TIME_SEC_L_REG 0x54
27
27
#define HCLGE_PTP_TIME_NSEC_REG 0x58
28
-
#define HCLGE_PTP_TIME_NSEC_MASK GENMASK(29, 0)
28
+
#define HCLGE_PTP_TIME_NSEC_MASK 0x3fffffffLL
29
29
#define HCLGE_PTP_TIME_NSEC_NEG BIT(31)
30
30
#define HCLGE_PTP_TIME_SYNC_REG 0x5C
31
31
#define HCLGE_PTP_TIME_SYNC_EN BIT(0)
+2
-2
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+2
-2
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
···
2465
2465
struct hnae3_client *client)
2466
2466
{
2467
2467
struct hclgevf_dev *hdev = ae_dev->priv;
2468
-
int rst_cnt = hdev->rst_stats.rst_cnt;
2468
+
u32 rst_cnt = hdev->rst_stats.rst_cnt;
2469
2469
int ret;
2470
2470
2471
2471
ret = client->ops->init_instance(&hdev->nic);
···
2625
2625
2626
2626
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2627
2627
if (ret) {
2628
-
dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2628
+
dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting\n");
2629
2629
goto err_disable_device;
2630
2630
}
2631
2631
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+1
-1
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+14
-13
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c
+14
-13
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_regs.c
···
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struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
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struct hnae3_queue *tqp;
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-
int i, j, reg_um;
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+
int i, j, reg_num;
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u32 *reg = data;
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*version = hdev->fw_version;
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reg += hclgevf_reg_get_header(reg);
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/* fetching per-VF registers values from VF PCIe register space */
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reg_um = ARRAY_SIZE(cmdq_reg_addr_list);
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reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_um, reg);
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-
for (i = 0; i < reg_um; i++)
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+
reg_num = ARRAY_SIZE(cmdq_reg_addr_list);
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+
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_CMDQ, reg_num, reg);
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+
for (i = 0; i < reg_num; i++)
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*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
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-
reg_um = ARRAY_SIZE(common_reg_addr_list);
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-
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_um, reg);
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-
for (i = 0; i < reg_um; i++)
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+
reg_num = ARRAY_SIZE(common_reg_addr_list);
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+
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_COMMON, reg_num, reg);
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+
for (i = 0; i < reg_num; i++)
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*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
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-
reg_um = ARRAY_SIZE(ring_reg_addr_list);
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+
reg_num = ARRAY_SIZE(ring_reg_addr_list);
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for (j = 0; j < hdev->num_tqps; j++) {
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-
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_um, reg);
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+
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_RING, reg_num, reg);
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tqp = &hdev->htqp[j].q;
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-
for (i = 0; i < reg_um; i++)
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+
for (i = 0; i < reg_num; i++)
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*reg++ = readl_relaxed(tqp->io_base -
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HCLGEVF_TQP_REG_OFFSET +
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ring_reg_addr_list[i]);
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}
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-
reg_um = ARRAY_SIZE(tqp_intr_reg_addr_list);
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+
reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);
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for (j = 0; j < hdev->num_msi_used - 1; j++) {
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-
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_TQP_INTR, reg_um, reg);
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-
for (i = 0; i < reg_um; i++)
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+
reg += hclgevf_reg_get_tlv(HCLGEVF_REG_TAG_TQP_INTR,
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+
reg_num, reg);
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+
for (i = 0; i < reg_num; i++)
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*reg++ = hclgevf_read_dev(&hdev->hw,
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tqp_intr_reg_addr_list[i] +
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HCLGEVF_RING_INT_REG_OFFSET * j);