Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

+2

Documentation/devicetree/bindings/arm/amlogic.txt

··· 40 40 - "hardkernel,odroid-c2" (Meson gxbb) 41 41 - "amlogic,p200" (Meson gxbb) 42 42 - "amlogic,p201" (Meson gxbb) 43 + - "wetek,hub" (Meson gxbb) 44 + - "wetek,play2" (Meson gxbb) 43 45 - "amlogic,p212" (Meson gxl s905x) 44 46 - "amlogic,p230" (Meson gxl s905d) 45 47 - "amlogic,p231" (Meson gxl s905d)

+1

Documentation/devicetree/bindings/vendor-prefixes.txt

··· 332 332 vivante Vivante Corporation 333 333 voipac Voipac Technologies s.r.o. 334 334 wd Western Digital Corp. 335 + wetek WeTek Electronics, limited. 335 336 wexler Wexler 336 337 winbond Winbond Electronics corp. 337 338 wlf Wolfson Microelectronics

+6 -6

arch/arm/configs/moxart_defconfig

··· 18 18 # CONFIG_LBDAF is not set 19 19 # CONFIG_BLK_DEV_BSG is not set 20 20 # CONFIG_IOSCHED_DEADLINE is not set 21 - CONFIG_ARCH_MULTI_V4T=y 21 + CONFIG_ARCH_MULTI_V4=y 22 22 # CONFIG_ARCH_MULTI_V7 is not set 23 - CONFIG_KEYBOARD_GPIO_POLLED=y 24 23 CONFIG_ARCH_MOXART=y 25 24 CONFIG_MACH_UC7112LX=y 26 25 CONFIG_PREEMPT=y ··· 93 94 CONFIG_SERIAL_8250_SHARE_IRQ=y 94 95 CONFIG_SERIAL_OF_PLATFORM=y 95 96 # CONFIG_HW_RANDOM is not set 96 - CONFIG_DEBUG_GPIO=y 97 - CONFIG_GPIO_SYSFS=y 98 97 CONFIG_GPIO_MOXART=y 99 - CONFIG_POWER_SUPPLY=y 100 98 CONFIG_POWER_RESET=y 101 99 CONFIG_POWER_RESET_GPIO=y 100 + CONFIG_POWER_SUPPLY=y 102 101 # CONFIG_HWMON is not set 103 102 CONFIG_WATCHDOG=y 104 103 CONFIG_WATCHDOG_CORE=y ··· 104 107 CONFIG_MOXART_WDT=y 105 108 # CONFIG_USB_SUPPORT is not set 106 109 CONFIG_MMC=y 107 - CONFIG_MMC_SDHCI_MOXART=y 110 + CONFIG_MMC_SDHCI=y 111 + CONFIG_MMC_SDHCI_PLTFM=y 112 + CONFIG_MMC_MOXART=y 108 113 CONFIG_NEW_LEDS=y 109 114 CONFIG_LEDS_CLASS=y 110 115 CONFIG_LEDS_GPIO=y 116 + CONFIG_LEDS_TRIGGERS=y 111 117 CONFIG_LEDS_TRIGGER_TIMER=y 112 118 CONFIG_LEDS_TRIGGER_ONESHOT=y 113 119 CONFIG_LEDS_TRIGGER_HEARTBEAT=y

-3

arch/arm/mach-ux500/Makefile

··· 5 5 obj-y := pm.o 6 6 obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o 7 7 obj-$(CONFIG_SMP) += platsmp.o 8 - obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 9 8 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o 10 - 11 - CFLAGS_hotplug.o += -march=armv7-a

-2

arch/arm/mach-ux500/cpu-db8500.c

··· 31 31 #include <asm/mach/map.h> 32 32 #include <asm/mach/arch.h> 33 33 34 - #include "setup.h" 35 - 36 34 #include "db8500-regs.h" 37 35 38 36 static int __init ux500_l2x0_unlock(void)

-37

arch/arm/mach-ux500/hotplug.c

··· 1 - /* 2 - * Copyright (C) STMicroelectronics 2009 3 - * Copyright (C) ST-Ericsson SA 2010 4 - * 5 - * License Terms: GNU General Public License v2 6 - * Based on ARM realview platform 7 - * 8 - * Author: Sundar Iyer <sundar.iyer@stericsson.com> 9 - * 10 - */ 11 - #include <linux/kernel.h> 12 - #include <linux/errno.h> 13 - #include <linux/smp.h> 14 - 15 - #include <asm/smp_plat.h> 16 - 17 - #include "setup.h" 18 - 19 - /* 20 - * platform-specific code to shutdown a CPU 21 - * 22 - * Called with IRQs disabled 23 - */ 24 - void ux500_cpu_die(unsigned int cpu) 25 - { 26 - /* directly enter low power state, skipping secure registers */ 27 - for (;;) { 28 - __asm__ __volatile__("dsb\n\t" "wfi\n\t" 29 - : : : "memory"); 30 - if (pen_release == cpu_logical_map(cpu)) { 31 - /* 32 - * OK, proper wakeup, we're done 33 - */ 34 - break; 35 - } 36 - } 37 - }

+7 -2

arch/arm/mach-ux500/platsmp.c

··· 23 23 #include <asm/smp_plat.h> 24 24 #include <asm/smp_scu.h> 25 25 26 - #include "setup.h" 27 - 28 26 #include "db8500-regs.h" 29 27 30 28 /* Magic triggers in backup RAM */ ··· 87 89 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 88 90 return 0; 89 91 } 92 + 93 + #ifdef CONFIG_HOTPLUG_CPU 94 + void ux500_cpu_die(unsigned int cpu) 95 + { 96 + wfi(); 97 + } 98 + #endif 90 99 91 100 static const struct smp_operations ux500_smp_ops __initconst = { 92 101 .smp_prepare_cpus = ux500_smp_prepare_cpus,

-16

arch/arm/mach-ux500/setup.h

··· 1 - /* 2 - * Copyright (C) 2009 ST-Ericsson. 3 - * 4 - * This program is free software; you can redistribute it and/or modify 5 - * it under the terms of the GNU General Public License version 2 as 6 - * published by the Free Software Foundation. 7 - * 8 - * These symbols are needed for board-specific files to call their 9 - * own cpu-specific files 10 - */ 11 - #ifndef __ASM_ARCH_SETUP_H 12 - #define __ASM_ARCH_SETUP_H 13 - 14 - extern void ux500_cpu_die(unsigned int cpu); 15 - 16 - #endif /* __ASM_ARCH_SETUP_H */

+5 -3

arch/arm64/boot/dts/amlogic/Makefile

··· 5 5 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb 6 6 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb 7 7 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb 8 + dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb 9 + dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb 8 10 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb 9 11 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb 10 12 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb 11 - dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb 12 - dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb 13 - dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb 13 + dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb 14 + dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb 15 + dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb 14 16 dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb 15 17 16 18 always := $(dtb-y)

+68

arch/arm64/boot/dts/amlogic/meson-gx.dtsi

··· 83 83 reg = <0x0 0x0>; 84 84 enable-method = "psci"; 85 85 next-level-cache = <&l2>; 86 + clocks = <&scpi_dvfs 0>; 86 87 }; 87 88 88 89 cpu1: cpu@1 { ··· 92 91 reg = <0x0 0x1>; 93 92 enable-method = "psci"; 94 93 next-level-cache = <&l2>; 94 + clocks = <&scpi_dvfs 0>; 95 95 }; 96 96 97 97 cpu2: cpu@2 { ··· 101 99 reg = <0x0 0x2>; 102 100 enable-method = "psci"; 103 101 next-level-cache = <&l2>; 102 + clocks = <&scpi_dvfs 0>; 104 103 }; 105 104 106 105 cpu3: cpu@3 { ··· 110 107 reg = <0x0 0x3>; 111 108 enable-method = "psci"; 112 109 next-level-cache = <&l2>; 110 + clocks = <&scpi_dvfs 0>; 113 111 }; 114 112 115 113 l2: l2-cache0 { ··· 175 171 }; 176 172 }; 177 173 174 + scpi { 175 + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 176 + mboxes = <&mailbox 1 &mailbox 2>; 177 + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 178 + 179 + scpi_clocks: clocks { 180 + compatible = "arm,scpi-clocks"; 181 + 182 + scpi_dvfs: scpi_clocks@0 { 183 + compatible = "arm,scpi-dvfs-clocks"; 184 + #clock-cells = <1>; 185 + clock-indices = <0>; 186 + clock-output-names = "vcpu"; 187 + }; 188 + }; 189 + 190 + scpi_sensors: sensors { 191 + compatible = "arm,scpi-sensors"; 192 + #thermal-sensor-cells = <1>; 193 + }; 194 + }; 195 + 178 196 soc { 179 197 compatible = "simple-bus"; 180 198 #address-cells = <2>; ··· 255 229 status = "disabled"; 256 230 }; 257 231 232 + saradc: adc@8680 { 233 + compatible = "amlogic,meson-saradc"; 234 + reg = <0x0 0x8680 0x0 0x34>; 235 + #io-channel-cells = <1>; 236 + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 237 + status = "disabled"; 238 + }; 239 + 258 240 pwm_ef: pwm@86c0 { 259 241 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 260 242 reg = <0x0 0x086c0 0x0 0x10>; ··· 316 282 #address-cells = <0>; 317 283 }; 318 284 285 + sram: sram@c8000000 { 286 + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; 287 + reg = <0x0 0xc8000000 0x0 0x14000>; 288 + 289 + #address-cells = <1>; 290 + #size-cells = <1>; 291 + ranges = <0 0x0 0xc8000000 0x14000>; 292 + 293 + cpu_scp_lpri: scp-shmem@0 { 294 + compatible = "amlogic,meson-gxbb-scp-shmem"; 295 + reg = <0x13000 0x400>; 296 + }; 297 + 298 + cpu_scp_hpri: scp-shmem@200 { 299 + compatible = "amlogic,meson-gxbb-scp-shmem"; 300 + reg = <0x13400 0x400>; 301 + }; 302 + }; 303 + 319 304 aobus: aobus@c8100000 { 320 305 compatible = "simple-bus"; 321 306 reg = <0x0 0xc8100000 0x0 0x100000>; ··· 347 294 reg = <0x0 0x004c0 0x0 0x14>; 348 295 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 349 296 clocks = <&xtal>; 297 + status = "disabled"; 298 + }; 299 + 300 + uart_AO_B: serial@4e0 { 301 + compatible = "amlogic,meson-uart"; 302 + reg = <0x0 0x004e0 0x0 0x14>; 303 + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 304 + clocks = <&xtal>; 305 + status = "disabled"; 306 + }; 307 + 308 + pwm_AO_ab: pwm@550 { 309 + compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 310 + reg = <0x0 0x00550 0x0 0x10>; 311 + #pwm-cells = <3>; 350 312 status = "disabled"; 351 313 }; 352 314

+50

arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts

··· 45 45 /dts-v1/; 46 46 47 47 #include "meson-gxbb-p20x.dtsi" 48 + #include <dt-bindings/input/input.h> 48 49 49 50 / { 50 51 compatible = "amlogic,p200", "amlogic,meson-gxbb"; 51 52 model = "Amlogic Meson GXBB P200 Development Board"; 53 + 54 + avdd18_usb_adc: regulator-avdd18_usb_adc { 55 + compatible = "regulator-fixed"; 56 + regulator-name = "AVDD18_USB_ADC"; 57 + regulator-min-microvolt = <1800000>; 58 + regulator-max-microvolt = <1800000>; 59 + }; 60 + 61 + adc_keys { 62 + compatible = "adc-keys"; 63 + io-channels = <&saradc 0>; 64 + io-channel-names = "buttons"; 65 + keyup-threshold-microvolt = <1800000>; 66 + 67 + button-home { 68 + label = "Home"; 69 + linux,code = <KEY_HOME>; 70 + press-threshold-microvolt = <900000>; /* 50% */ 71 + }; 72 + 73 + button-esc { 74 + label = "Esc"; 75 + linux,code = <KEY_ESC>; 76 + press-threshold-microvolt = <684000>; /* 38% */ 77 + }; 78 + 79 + button-up { 80 + label = "Volume Up"; 81 + linux,code = <KEY_VOLUMEUP>; 82 + press-threshold-microvolt = <468000>; /* 26% */ 83 + }; 84 + 85 + button-down { 86 + label = "Volume Down"; 87 + linux,code = <KEY_VOLUMEDOWN>; 88 + press-threshold-microvolt = <252000>; /* 14% */ 89 + }; 90 + 91 + button-menu { 92 + label = "Menu"; 93 + linux,code = <KEY_MENU>; 94 + press-threshold-microvolt = <0>; /* 0% */ 95 + }; 96 + }; 52 97 }; 53 98 54 99 &i2c_B { 55 100 status = "okay"; 56 101 pinctrl-0 = <&i2c_b_pins>; 57 102 pinctrl-names = "default"; 103 + }; 104 + 105 + &saradc { 106 + status = "okay"; 107 + vref-supply = <&avdd18_usb_adc>; 58 108 };

+11

arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi

··· 53 53 stdout-path = "serial0:115200n8"; 54 54 }; 55 55 56 + leds { 57 + compatible = "gpio-leds"; 58 + 59 + blue { 60 + label = "vega-s95:blue:on"; 61 + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; 62 + default-state = "on"; 63 + panic-indicator; 64 + }; 65 + }; 66 + 56 67 usb_vbus: regulator-usb0-vbus { 57 68 compatible = "regulator-fixed"; 58 69

+66

arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts

··· 1 + /* 2 + * Copyright (c) 2016 BayLibre, Inc. 3 + * Author: Neil Armstrong <narmstrong@baylibre.com> 4 + * 5 + * This file is dual-licensed: you can use it either under the terms 6 + * of the GPL or the X11 license, at your option. Note that this dual 7 + * licensing only applies to this file, and not this project as a 8 + * whole. 9 + * 10 + * a) This library is free software; you can redistribute it and/or 11 + * modify it under the terms of the GNU General Public License as 12 + * published by the Free Software Foundation; either version 2 of the 13 + * License, or (at your option) any later version. 14 + * 15 + * This library is distributed in the hope that it will be useful, 16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 + * GNU General Public License for more details. 19 + * 20 + * Or, alternatively, 21 + * 22 + * b) Permission is hereby granted, free of charge, to any person 23 + * obtaining a copy of this software and associated documentation 24 + * files (the "Software"), to deal in the Software without 25 + * restriction, including without limitation the rights to use, 26 + * copy, modify, merge, publish, distribute, sublicense, and/or 27 + * sell copies of the Software, and to permit persons to whom the 28 + * Software is furnished to do so, subject to the following 29 + * conditions: 30 + * 31 + * The above copyright notice and this permission notice shall be 32 + * included in all copies or substantial portions of the Software. 33 + * 34 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 + * OTHER DEALINGS IN THE SOFTWARE. 42 + */ 43 + 44 + /dts-v1/; 45 + 46 + #include "meson-gxbb-p20x.dtsi" 47 + 48 + / { 49 + compatible = "wetek,hub", "amlogic,meson-gxbb"; 50 + model = "WeTek Hub"; 51 + 52 + leds { 53 + compatible = "gpio-leds"; 54 + 55 + system { 56 + label = "wetek-play:system-status"; 57 + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; 58 + default-state = "on"; 59 + panic-indicator; 60 + }; 61 + }; 62 + 63 + cvbs-connector { 64 + status = "disabled"; 65 + }; 66 + };

+94

arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts

··· 1 + /* 2 + * Copyright (c) 2016 BayLibre, Inc. 3 + * Author: Neil Armstrong <narmstrong@baylibre.com> 4 + * 5 + * This file is dual-licensed: you can use it either under the terms 6 + * of the GPL or the X11 license, at your option. Note that this dual 7 + * licensing only applies to this file, and not this project as a 8 + * whole. 9 + * 10 + * a) This library is free software; you can redistribute it and/or 11 + * modify it under the terms of the GNU General Public License as 12 + * published by the Free Software Foundation; either version 2 of the 13 + * License, or (at your option) any later version. 14 + * 15 + * This library is distributed in the hope that it will be useful, 16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 + * GNU General Public License for more details. 19 + * 20 + * Or, alternatively, 21 + * 22 + * b) Permission is hereby granted, free of charge, to any person 23 + * obtaining a copy of this software and associated documentation 24 + * files (the "Software"), to deal in the Software without 25 + * restriction, including without limitation the rights to use, 26 + * copy, modify, merge, publish, distribute, sublicense, and/or 27 + * sell copies of the Software, and to permit persons to whom the 28 + * Software is furnished to do so, subject to the following 29 + * conditions: 30 + * 31 + * The above copyright notice and this permission notice shall be 32 + * included in all copies or substantial portions of the Software. 33 + * 34 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 + * OTHER DEALINGS IN THE SOFTWARE. 42 + */ 43 + 44 + /dts-v1/; 45 + 46 + #include "meson-gxbb-p20x.dtsi" 47 + #include <dt-bindings/input/input.h> 48 + 49 + / { 50 + compatible = "wetek,play2", "amlogic,meson-gxbb"; 51 + model = "WeTek Play 2"; 52 + 53 + leds { 54 + compatible = "gpio-leds"; 55 + 56 + system { 57 + label = "wetek-play:system-status"; 58 + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; 59 + default-state = "on"; 60 + panic-indicator; 61 + }; 62 + 63 + wifi { 64 + label = "wetek-play:wifi-status"; 65 + gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; 66 + default-state = "off"; 67 + }; 68 + 69 + ethernet { 70 + label = "wetek-play:ethernet-status"; 71 + gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; 72 + default-state = "off"; 73 + }; 74 + }; 75 + 76 + gpio-keys-polled { 77 + compatible = "gpio-keys-polled"; 78 + #address-cells = <1>; 79 + #size-cells = <0>; 80 + poll-interval = <100>; 81 + 82 + button@0 { 83 + label = "reset"; 84 + linux,code = <KEY_RESTART>; 85 + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; 86 + }; 87 + }; 88 + }; 89 + 90 + &i2c_A { 91 + status = "okay"; 92 + pinctrl-0 = <&i2c_a_pins>; 93 + pinctrl-names = "default"; 94 + };

+71 -57

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

··· 50 50 / { 51 51 compatible = "amlogic,meson-gxbb"; 52 52 53 - scpi { 54 - compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 55 - mboxes = <&mailbox 1 &mailbox 2>; 56 - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 57 - 58 - scpi_clocks: clocks { 59 - compatible = "arm,scpi-clocks"; 60 - 61 - scpi_dvfs: scpi_clocks@0 { 62 - compatible = "arm,scpi-dvfs-clocks"; 63 - #clock-cells = <1>; 64 - clock-indices = <0>; 65 - clock-output-names = "vcpu"; 66 - }; 67 - }; 68 - 69 - scpi_sensors: sensors { 70 - compatible = "arm,scpi-sensors"; 71 - #thermal-sensor-cells = <1>; 72 - }; 73 - }; 74 - 75 53 soc { 76 54 usb0_phy: phy@c0000000 { 77 55 compatible = "amlogic,meson-gxbb-usb2-phy"; ··· 69 91 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 70 92 clock-names = "usb_general", "usb"; 71 93 status = "disabled"; 72 - }; 73 - 74 - sram: sram@c8000000 { 75 - compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; 76 - reg = <0x0 0xc8000000 0x0 0x14000>; 77 - 78 - #address-cells = <1>; 79 - #size-cells = <1>; 80 - ranges = <0 0x0 0xc8000000 0x14000>; 81 - 82 - cpu_scp_lpri: scp-shmem@0 { 83 - compatible = "amlogic,meson-gxbb-scp-shmem"; 84 - reg = <0x13000 0x400>; 85 - }; 86 - 87 - cpu_scp_hpri: scp-shmem@200 { 88 - compatible = "amlogic,meson-gxbb-scp-shmem"; 89 - reg = <0x13400 0x400>; 90 - }; 91 94 }; 92 95 93 96 usb0: usb@c9000000 { ··· 95 136 status = "disabled"; 96 137 }; 97 138 }; 98 - }; 99 - 100 - &cpu0 { 101 - clocks = <&scpi_dvfs 0>; 102 - }; 103 - 104 - &cpu1 { 105 - clocks = <&scpi_dvfs 0>; 106 - }; 107 - 108 - &cpu2 { 109 - clocks = <&scpi_dvfs 0>; 110 - }; 111 - 112 - &cpu3 { 113 - clocks = <&scpi_dvfs 0>; 114 139 }; 115 140 116 141 &cbus { ··· 135 192 mux { 136 193 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 137 194 function = "uart_ao"; 195 + }; 196 + }; 197 + 198 + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 199 + mux { 200 + groups = "uart_cts_ao_a", 201 + "uart_rts_ao_a"; 202 + function = "uart_ao"; 203 + }; 204 + }; 205 + 206 + uart_ao_b_pins: uart_ao_b { 207 + mux { 208 + groups = "uart_tx_ao_b", "uart_rx_ao_b"; 209 + function = "uart_ao_b"; 210 + }; 211 + }; 212 + 213 + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 214 + mux { 215 + groups = "uart_cts_ao_b", 216 + "uart_rts_ao_b"; 217 + function = "uart_ao_b"; 138 218 }; 139 219 }; 140 220 ··· 306 340 }; 307 341 }; 308 342 343 + uart_a_cts_rts_pins: uart_a_cts_rts { 344 + mux { 345 + groups = "uart_cts_a", 346 + "uart_rts_a"; 347 + function = "uart_a"; 348 + }; 349 + }; 350 + 309 351 uart_b_pins: uart_b { 310 352 mux { 311 353 groups = "uart_tx_b", ··· 322 348 }; 323 349 }; 324 350 351 + uart_b_cts_rts_pins: uart_b_cts_rts { 352 + mux { 353 + groups = "uart_cts_b", 354 + "uart_rts_b"; 355 + function = "uart_b"; 356 + }; 357 + }; 358 + 325 359 uart_c_pins: uart_c { 326 360 mux { 327 361 groups = "uart_tx_c", 328 362 "uart_rx_c"; 363 + function = "uart_c"; 364 + }; 365 + }; 366 + 367 + uart_c_cts_rts_pins: uart_c_cts_rts { 368 + mux { 369 + groups = "uart_cts_c", 370 + "uart_rts_c"; 329 371 function = "uart_c"; 330 372 }; 331 373 }; ··· 453 463 function = "pwm_f_y"; 454 464 }; 455 465 }; 466 + 467 + hdmi_hpd_pins: hdmi_hpd { 468 + mux { 469 + groups = "hdmi_hpd"; 470 + function = "hdmi_hpd"; 471 + }; 472 + }; 473 + 474 + hdmi_i2c_pins: hdmi_i2c { 475 + mux { 476 + groups = "hdmi_sda", "hdmi_scl"; 477 + function = "hdmi_i2c"; 478 + }; 479 + }; 456 480 }; 457 481 }; 458 482 ··· 488 484 489 485 &i2c_C { 490 486 clocks = <&clkc CLKID_I2C>; 487 + }; 488 + 489 + &saradc { 490 + compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 491 + clocks = <&xtal>, 492 + <&clkc CLKID_SAR_ADC>, 493 + <&clkc CLKID_SANA>, 494 + <&clkc CLKID_SAR_ADC_CLK>, 495 + <&clkc CLKID_SAR_ADC_SEL>; 496 + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 491 497 }; 492 498 493 499 &sd_emmc_a {

arch/arm64/boot/dts/amlogic/meson-gxl-nexbox-a95x.dts arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts

+78

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

··· 88 88 }; 89 89 }; 90 90 91 + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 92 + mux { 93 + groups = "uart_cts_ao_a", 94 + "uart_rts_ao_a"; 95 + function = "uart_ao"; 96 + }; 97 + }; 98 + 99 + uart_ao_b_pins: uart_ao_b { 100 + mux { 101 + groups = "uart_tx_ao_b", "uart_rx_ao_b"; 102 + function = "uart_ao_b"; 103 + }; 104 + }; 105 + 106 + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 107 + mux { 108 + groups = "uart_cts_ao_b", 109 + "uart_rts_ao_b"; 110 + function = "uart_ao_b"; 111 + }; 112 + }; 113 + 91 114 remote_input_ao_pins: remote_input_ao { 92 115 mux { 93 116 groups = "remote_input_ao"; 94 117 function = "remote_input_ao"; 118 + }; 119 + }; 120 + 121 + pwm_ao_b_pins: pwm_ao_b { 122 + mux { 123 + groups = "pwm_ao_b"; 124 + function = "pwm_ao_b"; 95 125 }; 96 126 }; 97 127 }; ··· 193 163 }; 194 164 }; 195 165 166 + uart_a_cts_rts_pins: uart_a_cts_rts { 167 + mux { 168 + groups = "uart_cts_a", 169 + "uart_rts_a"; 170 + function = "uart_a"; 171 + }; 172 + }; 173 + 196 174 uart_b_pins: uart_b { 197 175 mux { 198 176 groups = "uart_tx_b", ··· 209 171 }; 210 172 }; 211 173 174 + uart_b_cts_rts_pins: uart_b_cts_rts { 175 + mux { 176 + groups = "uart_cts_b", 177 + "uart_rts_b"; 178 + function = "uart_b"; 179 + }; 180 + }; 181 + 212 182 uart_c_pins: uart_c { 213 183 mux { 214 184 groups = "uart_tx_c", 215 185 "uart_rx_c"; 186 + function = "uart_c"; 187 + }; 188 + }; 189 + 190 + uart_c_cts_rts_pins: uart_c_cts_rts { 191 + mux { 192 + groups = "uart_cts_c", 193 + "uart_rts_c"; 216 194 function = "uart_c"; 217 195 }; 218 196 }; ··· 283 229 function = "pwm_e"; 284 230 }; 285 231 }; 232 + 233 + hdmi_hpd_pins: hdmi_hpd { 234 + mux { 235 + groups = "hdmi_hpd"; 236 + function = "hdmi_hpd"; 237 + }; 238 + }; 239 + 240 + hdmi_i2c_pins: hdmi_i2c { 241 + mux { 242 + groups = "hdmi_sda", "hdmi_scl"; 243 + function = "hdmi_i2c"; 244 + }; 245 + }; 286 246 }; 287 247 288 248 eth-phy-mux { ··· 345 277 346 278 &i2c_C { 347 279 clocks = <&clkc CLKID_I2C>; 280 + }; 281 + 282 + &saradc { 283 + compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; 284 + clocks = <&xtal>, 285 + <&clkc CLKID_SAR_ADC>, 286 + <&clkc CLKID_SANA>, 287 + <&clkc CLKID_SAR_ADC_CLK>, 288 + <&clkc CLKID_SAR_ADC_SEL>; 289 + clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 348 290 }; 349 291 350 292 &sd_emmc_a {

arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts

arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts

+14

arch/arm64/boot/dts/amlogic/meson-gxm.dtsi

··· 85 85 reg = <0x0 0x100>; 86 86 enable-method = "psci"; 87 87 next-level-cache = <&l2>; 88 + clocks = <&scpi_dvfs 1>; 88 89 }; 89 90 90 91 cpu5: cpu@101 { ··· 94 93 reg = <0x0 0x101>; 95 94 enable-method = "psci"; 96 95 next-level-cache = <&l2>; 96 + clocks = <&scpi_dvfs 1>; 97 97 }; 98 98 99 99 cpu6: cpu@102 { ··· 103 101 reg = <0x0 0x102>; 104 102 enable-method = "psci"; 105 103 next-level-cache = <&l2>; 104 + clocks = <&scpi_dvfs 1>; 106 105 }; 107 106 108 107 cpu7: cpu@103 { ··· 112 109 reg = <0x0 0x103>; 113 110 enable-method = "psci"; 114 111 next-level-cache = <&l2>; 112 + clocks = <&scpi_dvfs 1>; 115 113 }; 116 114 }; 115 + }; 116 + 117 + &saradc { 118 + compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; 119 + }; 120 + 121 + &scpi_dvfs { 122 + clock-indices = <0 1>; 123 + clock-output-names = "vbig", "vlittle"; 117 124 }; 118 125 119 126 &vpu { 120 127 compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; 121 128 }; 129 +

+7 -6

arch/arm64/boot/dts/arm/juno-base.dtsi

··· 372 372 }; 373 373 }; 374 374 375 - coresight-replicator { 376 - /* 377 - * Non-configurable replicators don't show up on the 378 - * AMBA bus. As such no need to add "arm,primecell". 379 - */ 380 - compatible = "arm,coresight-replicator"; 375 + replicator@20120000 { 376 + compatible = "qcom,coresight-replicator1x", "arm,primecell"; 377 + reg = <0 0x20120000 0 0x1000>; 378 + 379 + clocks = <&soc_smc50mhz>; 380 + clock-names = "apb_pclk"; 381 + power-domains = <&scpi_devpd 0>; 381 382 382 383 ports { 383 384 #address-cells = <1>;

-12

arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi

··· 217 217 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; 218 218 }; 219 219 220 - &cmu_disp { 221 - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, 222 - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, 223 - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, 224 - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; 225 - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, 226 - <0>, 227 - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 228 - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; 229 - assigned-clock-rates = <0>, <400000000>; 230 - }; 231 - 232 220 &cmu_fsys { 233 221 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, 234 222 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,

+34

arch/arm64/boot/dts/exynos/exynos5433-tm2.dts

··· 18 18 compatible = "samsung,tm2", "samsung,exynos5433"; 19 19 }; 20 20 21 + &cmu_disp { 22 + /* 23 + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned 24 + * clocks properties for DISP CMU for each board to keep them together 25 + * for easier review and maintenance. 26 + */ 27 + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, 28 + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, 29 + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, 30 + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 31 + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, 32 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 33 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, 34 + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, 35 + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, 36 + <&cmu_disp CLK_MOUT_DISP_PLL>, 37 + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, 38 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, 39 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; 40 + assigned-clock-parents = <0>, <0>, 41 + <&cmu_mif CLK_ACLK_DISP_333>, 42 + <&cmu_mif CLK_SCLK_DSIM0_DISP>, 43 + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 44 + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 45 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 46 + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, 47 + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, 48 + <&cmu_disp CLK_FOUT_DISP_PLL>, 49 + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, 50 + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 51 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; 52 + assigned-clock-rates = <250000000>, <400000000>; 53 + }; 54 + 21 55 &hsi2c_9 { 22 56 status = "okay"; 23 57

+34

arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts

··· 18 18 compatible = "samsung,tm2e", "samsung,exynos5433"; 19 19 }; 20 20 21 + &cmu_disp { 22 + /* 23 + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned 24 + * clocks properties for DISP CMU for each board to keep them together 25 + * for easier review and maintenance. 26 + */ 27 + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, 28 + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, 29 + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, 30 + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 31 + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, 32 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 33 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, 34 + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, 35 + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, 36 + <&cmu_disp CLK_MOUT_DISP_PLL>, 37 + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, 38 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, 39 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; 40 + assigned-clock-parents = <0>, <0>, 41 + <&cmu_mif CLK_ACLK_DISP_333>, 42 + <&cmu_mif CLK_SCLK_DSIM0_DISP>, 43 + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 44 + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 45 + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 46 + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, 47 + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, 48 + <&cmu_disp CLK_FOUT_DISP_PLL>, 49 + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, 50 + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 51 + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; 52 + assigned-clock-rates = <278000000>, <400000000>; 53 + }; 54 + 21 55 &ldo31_reg { 22 56 regulator-name = "TSP_VDD_1.8V_AP"; 23 57 regulator-min-microvolt = <1800000>;

+47 -2

arch/arm64/boot/dts/exynos/exynos7-espresso.dts

··· 13 13 #include "exynos7.dtsi" 14 14 #include <dt-bindings/interrupt-controller/irq.h> 15 15 #include <dt-bindings/clock/samsung,s2mps11.h> 16 + #include <dt-bindings/gpio/gpio.h> 16 17 17 18 / { 18 19 model = "Samsung Exynos7 Espresso board based on EXYNOS7"; ··· 33 32 device_type = "memory"; 34 33 reg = <0x0 0x40000000 0x0 0xC0000000>; 35 34 }; 35 + 36 + usb30_vbus_reg: regulator-usb30 { 37 + compatible = "regulator-fixed"; 38 + regulator-name = "VBUS_5V"; 39 + regulator-min-microvolt = <5000000>; 40 + regulator-max-microvolt = <5000000>; 41 + gpio = <&gph1 1 GPIO_ACTIVE_HIGH>; 42 + pinctrl-names = "default"; 43 + pinctrl-0 = <&usb30_vbus_en>; 44 + enable-active-high; 45 + }; 46 + 47 + usb3drd_boost_5v: regulator-usb3drd-boost { 48 + compatible = "regulator-fixed"; 49 + regulator-name = "VUSB_VBUS_5V"; 50 + regulator-min-microvolt = <5000000>; 51 + regulator-max-microvolt = <5000000>; 52 + gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>; 53 + pinctrl-names = "default"; 54 + pinctrl-0 = <&usb3drd_boost_en>; 55 + enable-active-high; 56 + }; 57 + 36 58 }; 37 59 38 60 &fin_pll { ··· 352 328 &pinctrl_alive { 353 329 pmic_irq: pmic-irq { 354 330 samsung,pins = "gpa0-2"; 355 - samsung,pin-pud = <3>; 356 - samsung,pin-drv = <3>; 331 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 332 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 357 333 }; 358 334 }; 359 335 ··· 388 364 vmmc-supply = <&ldo17_reg>; 389 365 vqmmc-supply = <&ldo2_reg>; 390 366 disable-wp; 367 + }; 368 + 369 + &pinctrl_bus1 { 370 + usb30_vbus_en: usb30-vbus-en { 371 + samsung,pins = "gph1-1"; 372 + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; 373 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 374 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 375 + }; 376 + 377 + usb3drd_boost_en: usb3drd-boost-en { 378 + samsung,pins = "gpf4-1"; 379 + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; 380 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 381 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 382 + }; 383 + }; 384 + 385 + &usbdrd_phy { 386 + vbus-supply = <&usb30_vbus_reg>; 387 + vbus-boost-supply = <&usb3drd_boost_5v>; 391 388 };

+152 -150

arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi

··· 12 12 * published by the Free Software Foundation. 13 13 */ 14 14 15 + #include <dt-bindings/pinctrl/samsung.h> 16 + 15 17 &pinctrl_alive { 16 18 gpa0: gpa0 { 17 19 gpio-controller; ··· 189 187 190 188 hs_i2c10_bus: hs-i2c10-bus { 191 189 samsung,pins = "gpb0-1", "gpb0-0"; 192 - samsung,pin-function = <2>; 193 - samsung,pin-pud = <3>; 194 - samsung,pin-drv = <0>; 190 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 191 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 192 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 195 193 }; 196 194 197 195 hs_i2c11_bus: hs-i2c11-bus { 198 196 samsung,pins = "gpb0-3", "gpb0-2"; 199 - samsung,pin-function = <2>; 200 - samsung,pin-pud = <3>; 201 - samsung,pin-drv = <0>; 197 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 198 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 199 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 202 200 }; 203 201 204 202 hs_i2c2_bus: hs-i2c2-bus { 205 203 samsung,pins = "gpd0-3", "gpd0-2"; 206 - samsung,pin-function = <3>; 207 - samsung,pin-pud = <3>; 208 - samsung,pin-drv = <0>; 204 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 205 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 206 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 209 207 }; 210 208 211 209 uart0_data: uart0-data { 212 210 samsung,pins = "gpd0-0", "gpd0-1"; 213 - samsung,pin-function = <2>; 214 - samsung,pin-pud = <0>; 215 - samsung,pin-drv = <0>; 211 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 212 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 213 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 216 214 }; 217 215 218 216 uart0_fctl: uart0-fctl { 219 217 samsung,pins = "gpd0-2", "gpd0-3"; 220 - samsung,pin-function = <2>; 221 - samsung,pin-pud = <0>; 222 - samsung,pin-drv = <0>; 218 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 219 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 220 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 223 221 }; 224 222 225 223 uart2_data: uart2-data { 226 224 samsung,pins = "gpd1-4", "gpd1-5"; 227 - samsung,pin-function = <2>; 228 - samsung,pin-pud = <0>; 229 - samsung,pin-drv = <0>; 225 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 226 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 227 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 230 228 }; 231 229 232 230 hs_i2c3_bus: hs-i2c3-bus { 233 231 samsung,pins = "gpd1-3", "gpd1-2"; 234 - samsung,pin-function = <3>; 235 - samsung,pin-pud = <3>; 236 - samsung,pin-drv = <0>; 232 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 233 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 234 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 237 235 }; 238 236 239 237 uart1_data: uart1-data { 240 238 samsung,pins = "gpd1-0", "gpd1-1"; 241 - samsung,pin-function = <2>; 242 - samsung,pin-pud = <0>; 243 - samsung,pin-drv = <0>; 239 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 240 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 241 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 244 242 }; 245 243 246 244 uart1_fctl: uart1-fctl { 247 245 samsung,pins = "gpd1-2", "gpd1-3"; 248 - samsung,pin-function = <2>; 249 - samsung,pin-pud = <0>; 250 - samsung,pin-drv = <0>; 246 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 247 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 248 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 251 249 }; 252 250 253 251 hs_i2c0_bus: hs-i2c0-bus { 254 252 samsung,pins = "gpd2-1", "gpd2-0"; 255 - samsung,pin-function = <2>; 256 - samsung,pin-pud = <3>; 257 - samsung,pin-drv = <0>; 253 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 254 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 255 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 258 256 }; 259 257 260 258 hs_i2c1_bus: hs-i2c1-bus { 261 259 samsung,pins = "gpd2-3", "gpd2-2"; 262 - samsung,pin-function = <2>; 263 - samsung,pin-pud = <3>; 264 - samsung,pin-drv = <0>; 260 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 261 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 262 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 265 263 }; 266 264 267 265 hs_i2c9_bus: hs-i2c9-bus { 268 266 samsung,pins = "gpd2-7", "gpd2-6"; 269 - samsung,pin-function = <3>; 270 - samsung,pin-pud = <3>; 271 - samsung,pin-drv = <0>; 267 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 268 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 269 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 272 270 }; 273 271 274 272 pwm0_out: pwm0-out { 275 273 samsung,pins = "gpd2-4"; 276 - samsung,pin-function = <2>; 277 - samsung,pin-pud = <0>; 278 - samsung,pin-drv = <0>; 274 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 275 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 276 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 279 277 }; 280 278 281 279 pwm1_out: pwm1-out { 282 280 samsung,pins = "gpd2-5"; 283 - samsung,pin-function = <2>; 284 - samsung,pin-pud = <0>; 285 - samsung,pin-drv = <0>; 281 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 282 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 283 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 286 284 }; 287 285 288 286 pwm2_out: pwm2-out { 289 287 samsung,pins = "gpd2-6"; 290 - samsung,pin-function = <2>; 291 - samsung,pin-pud = <0>; 292 - samsung,pin-drv = <0>; 288 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 289 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 290 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 293 291 }; 294 292 295 293 pwm3_out: pwm3-out { 296 294 samsung,pins = "gpd2-7"; 297 - samsung,pin-function = <2>; 298 - samsung,pin-pud = <0>; 299 - samsung,pin-drv = <0>; 295 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 296 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 297 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 300 298 }; 301 299 302 300 hs_i2c8_bus: hs-i2c8-bus { 303 301 samsung,pins = "gpd5-3", "gpd5-2"; 304 - samsung,pin-function = <3>; 305 - samsung,pin-pud = <3>; 306 - samsung,pin-drv = <0>; 302 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 303 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 304 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 307 305 }; 308 306 309 307 uart3_data: uart3-data { 310 308 samsung,pins = "gpd5-0", "gpd5-1"; 311 - samsung,pin-function = <3>; 312 - samsung,pin-pud = <0>; 313 - samsung,pin-drv = <0>; 309 + samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 310 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 311 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 314 312 }; 315 313 316 314 spi2_bus: spi2-bus { 317 315 samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; 318 - samsung,pin-function = <2>; 319 - samsung,pin-pud = <3>; 320 - samsung,pin-drv = <0>; 316 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 317 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 318 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 321 319 }; 322 320 323 321 spi1_bus: spi1-bus { 324 322 samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; 325 - samsung,pin-function = <2>; 326 - samsung,pin-pud = <3>; 327 - samsung,pin-drv = <0>; 323 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 324 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 325 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 328 326 }; 329 327 330 328 spi0_bus: spi0-bus { 331 329 samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; 332 - samsung,pin-function = <2>; 333 - samsung,pin-pud = <3>; 334 - samsung,pin-drv = <0>; 330 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 331 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 332 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 335 333 }; 336 334 337 335 hs_i2c4_bus: hs-i2c4-bus { 338 336 samsung,pins = "gpg3-1", "gpg3-0"; 339 - samsung,pin-function = <2>; 340 - samsung,pin-pud = <3>; 341 - samsung,pin-drv = <0>; 337 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 338 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 339 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 342 340 }; 343 341 344 342 hs_i2c5_bus: hs-i2c5-bus { 345 343 samsung,pins = "gpg3-3", "gpg3-2"; 346 - samsung,pin-function = <2>; 347 - samsung,pin-pud = <3>; 348 - samsung,pin-drv = <0>; 344 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 345 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 346 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 349 347 }; 350 348 }; 351 349 ··· 360 358 361 359 hs_i2c6_bus: hs-i2c6-bus { 362 360 samsung,pins = "gpj0-1", "gpj0-0"; 363 - samsung,pin-function = <2>; 364 - samsung,pin-pud = <3>; 365 - samsung,pin-drv = <0>; 361 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 362 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 363 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 366 364 }; 367 365 }; 368 366 ··· 377 375 378 376 hs_i2c7_bus: hs-i2c7-bus { 379 377 samsung,pins = "gpj1-1", "gpj1-0"; 380 - samsung,pin-function = <2>; 381 - samsung,pin-pud = <3>; 382 - samsung,pin-drv = <0>; 378 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 379 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 380 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 383 381 }; 384 382 }; 385 383 ··· 394 392 395 393 spi3_bus: spi3-bus { 396 394 samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; 397 - samsung,pin-function = <2>; 398 - samsung,pin-pud = <3>; 399 - samsung,pin-drv = <0>; 395 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 396 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 397 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 400 398 }; 401 399 }; 402 400 ··· 411 409 412 410 spi4_bus: spi4-bus { 413 411 samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; 414 - samsung,pin-function = <2>; 415 - samsung,pin-pud = <3>; 416 - samsung,pin-drv = <0>; 412 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 413 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 414 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 417 415 }; 418 416 }; 419 417 ··· 428 426 429 427 sd2_clk: sd2-clk { 430 428 samsung,pins = "gpr4-0"; 431 - samsung,pin-function = <2>; 432 - samsung,pin-pud = <0>; 433 - samsung,pin-drv = <3>; 429 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 430 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 431 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 434 432 }; 435 433 436 434 sd2_cmd: sd2-cmd { 437 435 samsung,pins = "gpr4-1"; 438 - samsung,pin-function = <2>; 439 - samsung,pin-pud = <0>; 440 - samsung,pin-drv = <3>; 436 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 437 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 438 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 441 439 }; 442 440 443 441 sd2_cd: sd2-cd { 444 442 samsung,pins = "gpr4-2"; 445 - samsung,pin-function = <2>; 446 - samsung,pin-pud = <3>; 447 - samsung,pin-drv = <3>; 443 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 444 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 445 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 448 446 }; 449 447 450 448 sd2_bus1: sd2-bus-width1 { 451 449 samsung,pins = "gpr4-3"; 452 - samsung,pin-function = <2>; 453 - samsung,pin-pud = <3>; 454 - samsung,pin-drv = <3>; 450 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 451 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 452 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 455 453 }; 456 454 457 455 sd2_bus4: sd2-bus-width4 { 458 456 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; 459 - samsung,pin-function = <2>; 460 - samsung,pin-pud = <3>; 461 - samsung,pin-drv = <3>; 457 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 458 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 459 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 462 460 }; 463 461 }; 464 462 ··· 497 495 498 496 sd0_clk: sd0-clk { 499 497 samsung,pins = "gpr0-0"; 500 - samsung,pin-function = <2>; 501 - samsung,pin-pud = <0>; 502 - samsung,pin-drv = <4>; 498 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 499 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 500 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 503 501 }; 504 502 505 503 sd0_cmd: sd0-cmd { 506 504 samsung,pins = "gpr0-1"; 507 - samsung,pin-function = <2>; 508 - samsung,pin-pud = <3>; 509 - samsung,pin-drv = <4>; 505 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 506 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 507 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 510 508 }; 511 509 512 510 sd0_ds: sd0-ds { 513 511 samsung,pins = "gpr0-2"; 514 - samsung,pin-function = <2>; 515 - samsung,pin-pud = <1>; 516 - samsung,pin-drv = <4>; 512 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 513 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 514 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 517 515 }; 518 516 519 517 sd0_qrdy: sd0-qrdy { 520 518 samsung,pins = "gpr0-3"; 521 - samsung,pin-function = <2>; 522 - samsung,pin-pud = <1>; 523 - samsung,pin-drv = <4>; 519 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 520 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 521 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 524 522 }; 525 523 526 524 sd0_bus1: sd0-bus-width1 { 527 525 samsung,pins = "gpr1-0"; 528 - samsung,pin-function = <2>; 529 - samsung,pin-pud = <3>; 530 - samsung,pin-drv = <4>; 526 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 527 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 528 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 531 529 }; 532 530 533 531 sd0_bus4: sd0-bus-width4 { 534 532 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; 535 - samsung,pin-function = <2>; 536 - samsung,pin-pud = <3>; 537 - samsung,pin-drv = <4>; 533 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 534 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 535 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 538 536 }; 539 537 540 538 sd0_bus8: sd0-bus-width8 { 541 539 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; 542 - samsung,pin-function = <2>; 543 - samsung,pin-pud = <3>; 544 - samsung,pin-drv = <4>; 540 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 541 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 542 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>; 545 543 }; 546 544 547 545 sd1_clk: sd1-clk { 548 546 samsung,pins = "gpr2-0"; 549 - samsung,pin-function = <2>; 550 - samsung,pin-pud = <0>; 551 - samsung,pin-drv = <2>; 547 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 548 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 549 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>; 552 550 }; 553 551 554 552 sd1_cmd: sd1-cmd { 555 553 samsung,pins = "gpr2-1"; 556 - samsung,pin-function = <2>; 557 - samsung,pin-pud = <0>; 558 - samsung,pin-drv = <2>; 554 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 555 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 556 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>; 559 557 }; 560 558 561 559 sd1_ds: sd1-ds { 562 560 samsung,pins = "gpr2-2"; 563 - samsung,pin-function = <2>; 564 - samsung,pin-pud = <1>; 565 - samsung,pin-drv = <6>; 561 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 562 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 563 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>; 566 564 }; 567 565 568 566 sd1_qrdy: sd1-qrdy { 569 567 samsung,pins = "gpr2-3"; 570 - samsung,pin-function = <2>; 571 - samsung,pin-pud = <1>; 572 - samsung,pin-drv = <6>; 568 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 569 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 570 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>; 573 571 }; 574 572 575 573 sd1_int: sd1-int { 576 574 samsung,pins = "gpr2-4"; 577 - samsung,pin-function = <2>; 578 - samsung,pin-pud = <1>; 579 - samsung,pin-drv = <6>; 575 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 576 + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 577 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>; 580 578 }; 581 579 582 580 sd1_bus1: sd1-bus-width1 { 583 581 samsung,pins = "gpr3-0"; 584 - samsung,pin-function = <2>; 585 - samsung,pin-pud = <3>; 586 - samsung,pin-drv = <2>; 582 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 583 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 584 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>; 587 585 }; 588 586 589 587 sd1_bus4: sd1-bus-width4 { 590 588 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; 591 - samsung,pin-function = <2>; 592 - samsung,pin-pud = <3>; 593 - samsung,pin-drv = <2>; 589 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 590 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 591 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>; 594 592 }; 595 593 596 594 sd1_bus8: sd1-bus-width8 { 597 595 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; 598 - samsung,pin-function = <2>; 599 - samsung,pin-pud = <3>; 600 - samsung,pin-drv = <2>; 596 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 597 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 598 + samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>; 601 599 }; 602 600 }; 603 601 ··· 684 682 685 683 spi5_bus: spi5-bus { 686 684 samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; 687 - samsung,pin-function = <2>; 688 - samsung,pin-pud = <3>; 689 - samsung,pin-drv = <0>; 685 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 686 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 687 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 690 688 }; 691 689 692 690 ufs_refclk_out: ufs-refclk-out { 693 691 samsung,pins = "gpg2-4"; 694 - samsung,pin-function = <2>; 695 - samsung,pin-pud = <0>; 696 - samsung,pin-drv = <2>; 692 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 693 + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 694 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>; 697 695 }; 698 696 699 697 ufs_rst_n: ufs-rst-n { 700 698 samsung,pins = "gph1-5"; 701 - samsung,pin-function = <2>; 702 - samsung,pin-pud = <3>; 703 - samsung,pin-drv = <0>; 699 + samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 700 + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 701 + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 704 702 }; 705 703 };

+34

arch/arm64/boot/dts/exynos/exynos7.dtsi

··· 603 603 #include "exynos7-trip-points.dtsi" 604 604 }; 605 605 }; 606 + 607 + usbdrd_phy: phy@15500000 { 608 + compatible = "samsung,exynos7-usbdrd-phy"; 609 + reg = <0x15500000 0x100>; 610 + clocks = <&clock_fsys0 ACLK_USBDRD300>, 611 + <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 612 + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 613 + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 614 + <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 615 + clock-names = "phy", "ref", "phy_pipe", 616 + "phy_utmi", "itp"; 617 + samsung,pmu-syscon = <&pmu_system_controller>; 618 + #phy-cells = <1>; 619 + }; 620 + 621 + usbdrd3 { 622 + compatible = "samsung,exynos7-dwusb3"; 623 + clocks = <&clock_fsys0 ACLK_USBDRD300>, 624 + <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 625 + <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 626 + clock-names = "usbdrd30", "usbdrd30_susp_clk", 627 + "usbdrd30_axius_clk"; 628 + #address-cells = <1>; 629 + #size-cells = <1>; 630 + ranges; 631 + 632 + dwc3@15400000 { 633 + compatible = "snps,dwc3"; 634 + reg = <0x15400000 0x10000>; 635 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 636 + phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 637 + phy-names = "usb2-phy", "usb3-phy"; 638 + }; 639 + }; 606 640 }; 607 641 }; 608 642

+48

drivers/clk/meson/gxbb.c

··· 564 564 }, 565 565 }; 566 566 567 + static struct clk_mux gxbb_sar_adc_clk_sel = { 568 + .reg = (void *)HHI_SAR_CLK_CNTL, 569 + .mask = 0x3, 570 + .shift = 9, 571 + .lock = &clk_lock, 572 + .hw.init = &(struct clk_init_data){ 573 + .name = "sar_adc_clk_sel", 574 + .ops = &clk_mux_ops, 575 + /* NOTE: The datasheet doesn't list the parents for bit 10 */ 576 + .parent_names = (const char *[]){ "xtal", "clk81", }, 577 + .num_parents = 2, 578 + }, 579 + }; 580 + 581 + static struct clk_divider gxbb_sar_adc_clk_div = { 582 + .reg = (void *)HHI_SAR_CLK_CNTL, 583 + .shift = 0, 584 + .width = 8, 585 + .lock = &clk_lock, 586 + .hw.init = &(struct clk_init_data){ 587 + .name = "sar_adc_clk_div", 588 + .ops = &clk_divider_ops, 589 + .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 590 + .num_parents = 1, 591 + }, 592 + }; 593 + 594 + static struct clk_gate gxbb_sar_adc_clk = { 595 + .reg = (void *)HHI_SAR_CLK_CNTL, 596 + .bit_idx = 8, 597 + .lock = &clk_lock, 598 + .hw.init = &(struct clk_init_data){ 599 + .name = "sar_adc_clk", 600 + .ops = &clk_gate_ops, 601 + .parent_names = (const char *[]){ "sar_adc_clk_div" }, 602 + .num_parents = 1, 603 + .flags = CLK_SET_RATE_PARENT, 604 + }, 605 + }; 606 + 567 607 /* Everything Else (EE) domain gates */ 568 608 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 569 609 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); ··· 794 754 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 795 755 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 796 756 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 757 + [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 758 + [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 759 + [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 797 760 }, 798 761 .num = NR_CLKS, 799 762 }; ··· 899 856 &gxbb_emmc_a, 900 857 &gxbb_emmc_b, 901 858 &gxbb_emmc_c, 859 + &gxbb_sar_adc_clk, 902 860 }; 903 861 904 862 static int gxbb_clkc_probe(struct platform_device *pdev) ··· 931 887 /* Populate the base address for the MPEG clks */ 932 888 gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg; 933 889 gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg; 890 + 891 + /* Populate the base address for the SAR ADC clks */ 892 + gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg; 893 + gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg; 934 894 935 895 /* Populate base address for gates */ 936 896 for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)

+9 -6

drivers/clk/meson/gxbb.h

··· 191 191 #define CLKID_PERIPHS 20 192 192 #define CLKID_SPICC 21 193 193 /* CLKID_I2C */ 194 - #define CLKID_SAR_ADC 23 194 + /* #define CLKID_SAR_ADC */ 195 195 #define CLKID_SMART_CARD 24 196 196 #define CLKID_RNG0 25 197 197 #define CLKID_UART0 26 ··· 204 204 #define CLKID_ASSIST_MISC 33 205 205 /* CLKID_SPI */ 206 206 #define CLKID_I2S_SPDIF 35 207 - #define CLKID_ETH 36 207 + /* CLKID_ETH */ 208 208 #define CLKID_DEMUX 37 209 209 #define CLKID_AIU_GLUE 38 210 210 #define CLKID_IEC958 39 ··· 231 231 #define CLKID_AHB_DATA_BUS 60 232 232 #define CLKID_AHB_CTRL_BUS 61 233 233 #define CLKID_HDMI_INTR_SYNC 62 234 - #define CLKID_HDMI_PCLK 63 234 + /* CLKID_HDMI_PCLK */ 235 235 /* CLKID_USB1_DDR_BRIDGE */ 236 236 /* CLKID_USB0_DDR_BRIDGE */ 237 237 #define CLKID_MMC_PCLK 66 238 238 #define CLKID_DVIN 67 239 239 #define CLKID_UART2 68 240 - #define CLKID_SANA 69 240 + /* #define CLKID_SANA */ 241 241 #define CLKID_VPU_INTR 70 242 242 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 243 243 #define CLKID_CLK81_A53 72 ··· 245 245 #define CLKID_VCLK2_VENCI1 74 246 246 #define CLKID_VCLK2_VENCP0 75 247 247 #define CLKID_VCLK2_VENCP1 76 248 - #define CLKID_GCLK_VENCI_INT0 77 248 + /* CLKID_GCLK_VENCI_INT0 */ 249 249 #define CLKID_GCLK_VENCI_INT 78 250 250 #define CLKID_DAC_CLK 79 251 251 #define CLKID_AOCLK_GATE 80 ··· 265 265 /* CLKID_SD_EMMC_A */ 266 266 /* CLKID_SD_EMMC_B */ 267 267 /* CLKID_SD_EMMC_C */ 268 + /* CLKID_SAR_ADC_CLK */ 269 + /* CLKID_SAR_ADC_SEL */ 270 + #define CLKID_SAR_ADC_DIV 99 268 271 269 - #define NR_CLKS 97 272 + #define NR_CLKS 100 270 273 271 274 /* include the CLKIDs that have been made part of the stable DT binding */ 272 275 #include <dt-bindings/clock/gxbb-clkc.h>

+6

include/dt-bindings/clock/gxbb-clkc.h

··· 14 14 #define CLKID_MPLL2 15 15 15 #define CLKID_SPI 34 16 16 #define CLKID_I2C 22 17 + #define CLKID_SAR_ADC 23 17 18 #define CLKID_ETH 36 18 19 #define CLKID_USB0 50 19 20 #define CLKID_USB1 51 20 21 #define CLKID_USB 55 22 + #define CLKID_HDMI_PCLK 63 21 23 #define CLKID_USB1_DDR_BRIDGE 64 22 24 #define CLKID_USB0_DDR_BRIDGE 65 25 + #define CLKID_SANA 69 26 + #define CLKID_GCLK_VENCI_INT0 77 23 27 #define CLKID_AO_I2C 93 24 28 #define CLKID_SD_EMMC_A 94 25 29 #define CLKID_SD_EMMC_B 95 26 30 #define CLKID_SD_EMMC_C 96 31 + #define CLKID_SAR_ADC_CLK 97 32 + #define CLKID_SAR_ADC_SEL 98 27 33 28 34 #endif /* __GXBB_CLKC_H */

+8

include/dt-bindings/pinctrl/samsung.h

··· 68 68 #define EXYNOS_PIN_FUNC_6 6 69 69 #define EXYNOS_PIN_FUNC_F 0xf 70 70 71 + /* Drive strengths for Exynos7 FSYS1 block */ 72 + #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 73 + #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 74 + #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 75 + #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 76 + #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 77 + #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 78 + 71 79 #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */

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