Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: cadence: Sierra: Add single link SGMII register configuration
Add single link SGMII register configuration for no SSC for
cdns,sierra-phy-t0 compatibility string.
The configuration is based on Sierra Programmer's Guide and
validated in Cisco CrayAR SoC.
Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Signed-off-by: Marcin Wierzbicki <mawierzb@cisco.com>
Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Marcin Wierzbicki
and committed by
Vinod Koul
a1d12987
d1ea4239
+98
+98
drivers/phy/cadence/phy-cadence-sierra.c
+98
drivers/phy/cadence/phy-cadence-sierra.c
···
30
30
#define SIERRA_COMMON_CDB_OFFSET 0x0
31
31
#define SIERRA_MACRO_ID_REG 0x0
32
32
#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
33
+
#define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG 0x43
34
+
#define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG 0x45
35
+
#define SIERRA_CMN_PLLLC_INIT_PREG 0x46
36
+
#define SIERRA_CMN_PLLLC_ITERTMR_PREG 0x47
33
37
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
34
38
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
35
39
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
36
40
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
41
+
#define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG 0x4C
37
42
#define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D
43
+
#define SIERRA_CMN_PLLLC_CLK0_PREG 0x4E
38
44
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
39
45
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
40
46
#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
41
47
#define SIERRA_CMN_PLLLC_SS_PREG 0x52
42
48
#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
43
49
#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
50
+
#define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG 0x5D
51
+
#define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG 0x5E
44
52
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
45
53
#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
54
+
#define SIERRA_SDOSCCAL_CLK_CNT_PREG 0x6E
46
55
#define SIERRA_CMN_REFRCV_PREG 0x98
56
+
#define SIERRA_CMN_RESCAL_CTRLA_PREG 0xA0
47
57
#define SIERRA_CMN_REFRCV1_PREG 0xB8
48
58
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
49
59
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
60
+
#define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5
50
61
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
51
62
#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
52
63
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
···
97
86
#define SIERRA_DFE_BIASTRIM_PREG 0x04C
98
87
#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
99
88
#define SIERRA_DRVCTRL_BOOST_PREG 0x06F
89
+
#define SIERRA_LANE_TX_RECEIVER_DETECT_PREG 0x071
100
90
#define SIERRA_TX_RCVDET_OVRD_PREG 0x072
101
91
#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
102
92
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
···
113
101
#define SIERRA_CREQ_SPARE_PREG 0x096
114
102
#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097
115
103
#define SIERRA_CTLELUT_CTRL_PREG 0x098
104
+
#define SIERRA_DEQ_BLK_TAU_CTRL1_PREG 0x0AC
105
+
#define SIERRA_DEQ_BLK_TAU_CTRL4_PREG 0x0AF
116
106
#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0
117
107
#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1
118
108
#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4
···
143
129
#define SIERRA_DEQ_GLUT14 0x0F6
144
130
#define SIERRA_DEQ_GLUT15 0x0F7
145
131
#define SIERRA_DEQ_GLUT16 0x0F8
132
+
#define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG 0x0F9
133
+
#define SIERRA_TAU_EN_CEPH2TO0_PREG 0x0FB
134
+
#define SIERRA_TAU_EN_CEPH5TO3_PREG 0x0FC
146
135
#define SIERRA_DEQ_ALUT0 0x108
147
136
#define SIERRA_DEQ_ALUT1 0x109
148
137
#define SIERRA_DEQ_ALUT2 0x10A
···
160
143
#define SIERRA_DEQ_ALUT11 0x113
161
144
#define SIERRA_DEQ_ALUT12 0x114
162
145
#define SIERRA_DEQ_ALUT13 0x115
146
+
#define SIERRA_OEPH_EN_CTRL_PREG 0x124
163
147
#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
164
148
#define SIERRA_DEQ_DFETAP0 0x129
165
149
#define SIERRA_DEQ_DFETAP1 0x12B
···
175
157
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
176
158
#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
177
159
#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
160
+
#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159
178
161
#define SIERRA_DEQ_PICTRL_PREG 0x161
179
162
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
180
163
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
···
184
165
#define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E
185
166
#define SIERRA_CPI_TRIM_PREG 0x17F
186
167
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
168
+
#define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG 0x184
187
169
#define SIERRA_EPI_CTRL_PREG 0x187
188
170
#define SIERRA_LFPSDET_SUPPORT_PREG 0x188
189
171
#define SIERRA_LFPSFILT_NS_PREG 0x18A
···
196
176
#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E
197
177
#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F
198
178
#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0
179
+
#define SIERRA_LN_SPARE_REG_PREG 0x1B0
199
180
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
200
181
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
201
182
···
2423
2402
.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
2424
2403
};
2425
2404
2405
+
/* SGMII PHY common configuration */
2406
+
static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = {
2407
+
{0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG},
2408
+
{0x6000, SIERRA_CMN_REFRCV_PREG},
2409
+
{0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG},
2410
+
{0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG},
2411
+
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
2412
+
{0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG},
2413
+
{0x8103, SIERRA_CMN_PLLLC_CLK0_PREG},
2414
+
{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
2415
+
{0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG},
2416
+
{0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG},
2417
+
{0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},
2418
+
{0x0000, SIERRA_CMN_PLLLC_INIT_PREG},
2419
+
{0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG},
2420
+
{0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG},
2421
+
{0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG},
2422
+
{0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG},
2423
+
};
2424
+
2425
+
static struct cdns_sierra_vals sgmii_cmn_vals = {
2426
+
.reg_pairs = sgmii_pma_cmn_vals,
2427
+
.num_regs = ARRAY_SIZE(sgmii_pma_cmn_vals),
2428
+
};
2429
+
2430
+
/* SGMII PHY lane configuration */
2431
+
static const struct cdns_reg_pairs sgmii_ln_regs[] = {
2432
+
{0x691E, SIERRA_DET_STANDEC_D_PREG},
2433
+
{0x0FFE, SIERRA_PSC_RX_A0_PREG},
2434
+
{0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
2435
+
{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},
2436
+
{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},
2437
+
{0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
2438
+
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
2439
+
{0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
2440
+
{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},
2441
+
{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},
2442
+
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
2443
+
{0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG},
2444
+
{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},
2445
+
{0x15A2, SIERRA_LN_SPARE_REG_PREG},
2446
+
{0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG},
2447
+
{0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG},
2448
+
{0x2206, SIERRA_DEQ_TAU_CTRL2_PREG},
2449
+
{0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG},
2450
+
{0x8001, SIERRA_CREQ_SPARE_PREG},
2451
+
{0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG},
2452
+
{0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG},
2453
+
{0x0101, SIERRA_DEQ_GLUT9},
2454
+
{0x0101, SIERRA_DEQ_GLUT10},
2455
+
{0x0101, SIERRA_DEQ_GLUT11},
2456
+
{0x0101, SIERRA_DEQ_GLUT12},
2457
+
{0x0000, SIERRA_DEQ_GLUT13},
2458
+
{0x0000, SIERRA_DEQ_GLUT16},
2459
+
{0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG},
2460
+
{0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG},
2461
+
{0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG},
2462
+
{0x0101, SIERRA_DEQ_ALUT8},
2463
+
{0x0101, SIERRA_DEQ_ALUT9},
2464
+
{0x0100, SIERRA_DEQ_ALUT10},
2465
+
{0x0000, SIERRA_OEPH_EN_CTRL_PREG},
2466
+
{0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG},
2467
+
{0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
2468
+
{0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG},
2469
+
};
2470
+
2471
+
static struct cdns_sierra_vals sgmii_pma_ln_vals = {
2472
+
.reg_pairs = sgmii_ln_regs,
2473
+
.num_regs = ARRAY_SIZE(sgmii_ln_regs),
2474
+
};
2475
+
2426
2476
static const struct cdns_sierra_data cdns_map_sierra = {
2427
2477
.id_value = SIERRA_MACRO_ID,
2428
2478
.block_offset_shift = 0x2,
···
2541
2449
},
2542
2450
},
2543
2451
[TYPE_SGMII] = {
2452
+
[TYPE_NONE] = {
2453
+
[NO_SSC] = &sgmii_cmn_vals,
2454
+
},
2544
2455
[TYPE_PCIE] = {
2545
2456
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
2546
2457
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,
···
2582
2487
},
2583
2488
},
2584
2489
[TYPE_SGMII] = {
2490
+
[TYPE_NONE] = {
2491
+
[NO_SSC] = &sgmii_pma_ln_vals,
2492
+
},
2585
2493
[TYPE_PCIE] = {
2586
2494
[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,
2587
2495
[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,