Merge branch 'pci/controller/dwc-qcom-ep'

+110

Documentation/devicetree/bindings/pci/qcom,sa8255p-pcie-ep.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/pci/qcom,sa8255p-pcie-ep.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm firmware managed PCIe Endpoint Controller 8 + 9 + description: 10 + Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys 11 + DesignWare PCIe IP which is managed by firmware. 12 + 13 + maintainers: 14 + - Manivannan Sadhasivam <mani@kernel.org> 15 + 16 + properties: 17 + compatible: 18 + const: qcom,sa8255p-pcie-ep 19 + 20 + reg: 21 + items: 22 + - description: Qualcomm-specific PARF configuration registers 23 + - description: DesignWare PCIe registers 24 + - description: External local bus interface registers 25 + - description: Address Translation Unit (ATU) registers 26 + - description: Memory region used to map remote RC address space 27 + - description: BAR memory region 28 + - description: DMA register space 29 + 30 + reg-names: 31 + items: 32 + - const: parf 33 + - const: dbi 34 + - const: elbi 35 + - const: atu 36 + - const: addr_space 37 + - const: mmio 38 + - const: dma 39 + 40 + interrupts: 41 + items: 42 + - description: PCIe Global interrupt 43 + - description: PCIe Doorbell interrupt 44 + - description: DMA interrupt 45 + 46 + interrupt-names: 47 + items: 48 + - const: global 49 + - const: doorbell 50 + - const: dma 51 + 52 + iommus: 53 + maxItems: 1 54 + 55 + reset-gpios: 56 + description: GPIO used as PERST# input signal 57 + maxItems: 1 58 + 59 + wake-gpios: 60 + description: GPIO used as WAKE# output signal 61 + maxItems: 1 62 + 63 + power-domains: 64 + maxItems: 1 65 + 66 + dma-coherent: true 67 + 68 + num-lanes: 69 + default: 2 70 + 71 + required: 72 + - compatible 73 + - reg 74 + - reg-names 75 + - interrupts 76 + - interrupt-names 77 + - reset-gpios 78 + - power-domains 79 + 80 + additionalProperties: false 81 + 82 + examples: 83 + - | 84 + #include <dt-bindings/gpio/gpio.h> 85 + #include <dt-bindings/interrupt-controller/arm-gic.h> 86 + soc { 87 + #address-cells = <2>; 88 + #size-cells = <2>; 89 + pcie1_ep: pcie-ep@1c10000 { 90 + compatible = "qcom,sa8255p-pcie-ep"; 91 + reg = <0x0 0x01c10000 0x0 0x3000>, 92 + <0x0 0x60000000 0x0 0xf20>, 93 + <0x0 0x60000f20 0x0 0xa8>, 94 + <0x0 0x60001000 0x0 0x4000>, 95 + <0x0 0x60200000 0x0 0x100000>, 96 + <0x0 0x01c13000 0x0 0x1000>, 97 + <0x0 0x60005000 0x0 0x2000>; 98 + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio", "dma"; 99 + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 100 + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 101 + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 102 + interrupt-names = "global", "doorbell", "dma"; 103 + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; 104 + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; 105 + dma-coherent; 106 + iommus = <&pcie_smmu 0x80 0x7f>; 107 + power-domains = <&scmi6_pd 1>; 108 + num-lanes = <4>; 109 + }; 110 + };

+1

MAINTAINERS

··· 20365 20365 L: linux-arm-msm@vger.kernel.org 20366 20366 S: Maintained 20367 20367 F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml 20368 + F: Documentation/devicetree/bindings/pci/qcom,sa8255p-pcie-ep.yaml 20368 20369 F: drivers/pci/controller/dwc/pcie-qcom-common.c 20369 20370 F: drivers/pci/controller/dwc/pcie-qcom-ep.c 20370 20371

+56 -11

drivers/pci/controller/dwc/pcie-qcom-ep.c

··· 168 168 * @hdma_support: HDMA support on this SoC 169 169 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping 170 170 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check 171 + * @firmware_managed: Set if the controller is firmware managed 171 172 */ 172 173 struct qcom_pcie_ep_cfg { 173 174 bool hdma_support; 174 175 bool override_no_snoop; 175 176 bool disable_mhi_ram_parity_check; 177 + bool firmware_managed; 176 178 }; 177 179 178 180 /** ··· 379 377 380 378 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) 381 379 { 380 + struct device *dev = pcie_ep->pci.dev; 381 + 382 + pm_runtime_put(dev); 383 + 384 + /* Skip resource disablement if controller is firmware-managed */ 385 + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 386 + return; 387 + 382 388 icc_set_bw(pcie_ep->icc_mem, 0, 0); 383 389 phy_power_off(pcie_ep->phy); 384 390 phy_exit(pcie_ep->phy); ··· 400 390 u32 val, offset; 401 391 int ret; 402 392 403 - ret = qcom_pcie_enable_resources(pcie_ep); 404 - if (ret) { 405 - dev_err(dev, "Failed to enable resources: %d\n", ret); 393 + ret = pm_runtime_resume_and_get(dev); 394 + if (ret < 0) { 395 + dev_err(dev, "Failed to enable device: %d\n", ret); 406 396 return ret; 407 397 } 408 398 399 + /* Skip resource enablement if controller is firmware-managed */ 400 + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 401 + goto skip_resources_enable; 402 + 403 + ret = qcom_pcie_enable_resources(pcie_ep); 404 + if (ret) { 405 + dev_err(dev, "Failed to enable resources: %d\n", ret); 406 + pm_runtime_put(dev); 407 + return ret; 408 + } 409 + 410 + skip_resources_enable: 409 411 /* Perform cleanup that requires refclk */ 410 412 pci_epc_deinit_notify(pci->ep.epc); 411 413 dw_pcie_ep_cleanup(&pci->ep); ··· 652 630 return ret; 653 631 } 654 632 633 + pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 634 + if (IS_ERR(pcie_ep->reset)) 635 + return PTR_ERR(pcie_ep->reset); 636 + 637 + pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 638 + if (IS_ERR(pcie_ep->wake)) 639 + return PTR_ERR(pcie_ep->wake); 640 + 641 + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) 642 + return 0; 643 + 655 644 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks); 656 645 if (pcie_ep->num_clks < 0) { 657 646 dev_err(dev, "Failed to get clocks\n"); ··· 672 639 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core"); 673 640 if (IS_ERR(pcie_ep->core_reset)) 674 641 return PTR_ERR(pcie_ep->core_reset); 675 - 676 - pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN); 677 - if (IS_ERR(pcie_ep->reset)) 678 - return PTR_ERR(pcie_ep->reset); 679 - 680 - pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); 681 - if (IS_ERR(pcie_ep->wake)) 682 - return PTR_ERR(pcie_ep->wake); 683 642 684 643 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy"); 685 644 if (IS_ERR(pcie_ep->phy)) ··· 900 875 901 876 platform_set_drvdata(pdev, pcie_ep); 902 877 878 + pm_runtime_get_noresume(dev); 879 + pm_runtime_set_active(dev); 880 + ret = devm_pm_runtime_enable(dev); 881 + if (ret) 882 + return ret; 883 + 903 884 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); 904 885 if (ret) 905 886 return ret; ··· 923 892 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 924 893 if (!name) { 925 894 ret = -ENOMEM; 895 + goto err_disable_irqs; 896 + } 897 + 898 + ret = pm_runtime_put_sync(dev); 899 + if (ret < 0) { 900 + dev_err(dev, "Failed to suspend device: %d\n", ret); 926 901 goto err_disable_irqs; 927 902 } 928 903 ··· 968 931 .disable_mhi_ram_parity_check = true, 969 932 }; 970 933 934 + static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed = { 935 + .hdma_support = true, 936 + .override_no_snoop = true, 937 + .disable_mhi_ram_parity_check = true, 938 + .firmware_managed = true, 939 + }; 940 + 971 941 static const struct of_device_id qcom_pcie_ep_match[] = { 942 + { .compatible = "qcom,sa8255p-pcie-ep", .data = &cfg_1_34_0_fw_managed}, 972 943 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, 973 944 { .compatible = "qcom,sdx55-pcie-ep", }, 974 945 { .compatible = "qcom,sm8450-pcie-ep", },

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