Merge tag 'sound-6.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound fixes from Takashi Iwai:
"Likely the last piece for 6.1; the only significant fixes are ASoC
core ops fixes, while others are device-specific (rather minor) fixes
in ASoC and FireWire drivers.

All appear safe enough to take as a late stage material"

* tag 'sound-6.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound:
ALSA: dice: fix regression for Lexicon I-ONIX FW810S
ASoC: cs42l51: Correct PGA Volume minimum value
ASoC: ops: Correct bounds check for second channel on SX controls
ASoC: tlv320adc3xxx: Fix build error for implicit function declaration
ASoC: ops: Check bounds for second channel in snd_soc_put_volsw_sx()
ASoC: ops: Fix bounds check for _sx controls
ASoC: fsl_micfil: explicitly clear CHnF flags
ASoC: fsl_micfil: explicitly clear software reset bit

Linus Torvalds 3 years ago a1e9185d c290db01

+38 -9

5 changed files

expand all

sound

firewire

dice

dice-stream.c

soc

codecs

cs42l51.c

tlv320adc3xxx.c

fsl

fsl_micfil.c

soc-ops.c

+7 -5

sound/firewire/dice/dice-stream.c

··· 59 59 60 60 static int select_clock(struct snd_dice *dice, unsigned int rate) 61 61 { 62 - __be32 reg; 62 + __be32 reg, new; 63 63 u32 data; 64 64 int i; 65 65 int err; ··· 83 83 if (completion_done(&dice->clock_accepted)) 84 84 reinit_completion(&dice->clock_accepted); 85 85 86 - reg = cpu_to_be32(data); 86 + new = cpu_to_be32(data); 87 87 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT, 88 - &reg, sizeof(reg)); 88 + &new, sizeof(new)); 89 89 if (err < 0) 90 90 return err; 91 91 92 92 if (wait_for_completion_timeout(&dice->clock_accepted, 93 - msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) 94 - return -ETIMEDOUT; 93 + msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) { 94 + if (reg != new) 95 + return -ETIMEDOUT; 96 + } 95 97 96 98 return 0; 97 99 }

+1 -1

sound/soc/codecs/cs42l51.c

··· 143 143 0, 0xA0, 96, adc_att_tlv), 144 144 SOC_DOUBLE_R_SX_TLV("PGA Volume", 145 145 CS42L51_ALC_PGA_CTL, CS42L51_ALC_PGB_CTL, 146 - 0, 0x19, 30, pga_tlv), 146 + 0, 0x1A, 30, pga_tlv), 147 147 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0), 148 148 SOC_SINGLE("Auto-Mute Switch", CS42L51_DAC_CTL, 2, 1, 0), 149 149 SOC_SINGLE("Soft Ramp Switch", CS42L51_DAC_CTL, 1, 1, 0),

sound/soc/codecs/tlv320adc3xxx.c

··· 14 14 15 15 #include <dt-bindings/sound/tlv320adc3xxx.h> 16 16 #include <linux/clk.h> 17 + #include <linux/gpio/consumer.h> 17 18 #include <linux/module.h> 18 19 #include <linux/moduleparam.h> 19 20 #include <linux/io.h> ··· 1026 1025 1027 1026 static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) 1028 1027 { 1028 + #ifdef CONFIG_GPIOLIB 1029 1029 gpiochip_remove(&adc3xxx->gpio_chip); 1030 + #endif 1030 1031 } 1031 1032 1032 1033 static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx)

+19

sound/soc/fsl/fsl_micfil.c

··· 194 194 if (ret) 195 195 return ret; 196 196 197 + /* 198 + * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 199 + * as non-volatile register, so SRES still remain in regmap 200 + * cache after set, that every update of REG_MICFIL_CTRL1, 201 + * software reset happens. so clear it explicitly. 202 + */ 203 + ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 204 + MICFIL_CTRL1_SRES); 205 + if (ret) 206 + return ret; 207 + 208 + /* 209 + * Set SRES should clear CHnF flags, But even add delay here 210 + * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 211 + */ 212 + ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 213 + if (ret) 214 + return ret; 215 + 197 216 return 0; 198 217 } 199 218

+8 -3

sound/soc/soc-ops.c

··· 452 452 val = ucontrol->value.integer.value[0]; 453 453 if (mc->platform_max && val > mc->platform_max) 454 454 return -EINVAL; 455 - if (val > max - min) 455 + if (val > max) 456 456 return -EINVAL; 457 457 val_mask = mask << shift; 458 458 val = (val + min) & mask; ··· 464 464 ret = err; 465 465 466 466 if (snd_soc_volsw_is_stereo(mc)) { 467 - unsigned int val2; 467 + unsigned int val2 = ucontrol->value.integer.value[1]; 468 + 469 + if (mc->platform_max && val2 > mc->platform_max) 470 + return -EINVAL; 471 + if (val2 > max) 472 + return -EINVAL; 468 473 469 474 val_mask = mask << rshift; 470 - val2 = (ucontrol->value.integer.value[1] + min) & mask; 475 + val2 = (val2 + min) & mask; 471 476 val2 = val2 << rshift; 472 477 473 478 err = snd_soc_component_update_bits(component, reg2, val_mask,

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