tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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crypto: qat - fix ring to service map for QAT GEN4

The 4xxx drivers hardcode the ring to service mapping. However, when
additional configurations where added to the driver, the mappings were
not updated. This implies that an incorrect mapping might be reported
through pfvf for certain configurations.

Add an algorithm that computes the correct ring to service mapping based
on the firmware loaded on the device.

Fixes: 0cec19c761e5 ("crypto: qat - add support for compression for 4xxx")
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Damian Muszynski <damian.muszynski@intel.com>
Reviewed-by: Tero Kristo <tero.kristo@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Giovanni Cabiddu and committed by
Herbert Xu a238487f f7df2329

+58
+54
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
··· 424 424 } 425 425 } 426 426 427 + enum adf_rp_groups { 428 + RP_GROUP_0 = 0, 429 + RP_GROUP_1, 430 + RP_GROUP_COUNT 431 + }; 432 + 433 + static u16 get_ring_to_svc_map(struct adf_accel_dev *accel_dev) 434 + { 435 + enum adf_cfg_service_type rps[RP_GROUP_COUNT]; 436 + const struct adf_fw_config *fw_config; 437 + u16 ring_to_svc_map; 438 + int i, j; 439 + 440 + fw_config = get_fw_config(accel_dev); 441 + if (!fw_config) 442 + return 0; 443 + 444 + for (i = 0; i < RP_GROUP_COUNT; i++) { 445 + switch (fw_config[i].ae_mask) { 446 + case ADF_AE_GROUP_0: 447 + j = RP_GROUP_0; 448 + break; 449 + case ADF_AE_GROUP_1: 450 + j = RP_GROUP_1; 451 + break; 452 + default: 453 + return 0; 454 + } 455 + 456 + switch (fw_config[i].obj) { 457 + case ADF_FW_SYM_OBJ: 458 + rps[j] = SYM; 459 + break; 460 + case ADF_FW_ASYM_OBJ: 461 + rps[j] = ASYM; 462 + break; 463 + case ADF_FW_DC_OBJ: 464 + rps[j] = COMP; 465 + break; 466 + default: 467 + rps[j] = 0; 468 + break; 469 + } 470 + } 471 + 472 + ring_to_svc_map = rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_0_SHIFT | 473 + rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_1_SHIFT | 474 + rps[RP_GROUP_0] << ADF_CFG_SERV_RING_PAIR_2_SHIFT | 475 + rps[RP_GROUP_1] << ADF_CFG_SERV_RING_PAIR_3_SHIFT; 476 + 477 + return ring_to_svc_map; 478 + } 479 + 427 480 static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num, 428 481 const char * const fw_objs[], int num_objs) 429 482 { ··· 583 530 hw_data->uof_get_ae_mask = uof_get_ae_mask; 584 531 hw_data->set_msix_rttable = set_msix_default_rttable; 585 532 hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer; 533 + hw_data->get_ring_to_svc_map = get_ring_to_svc_map; 586 534 hw_data->disable_iov = adf_disable_sriov; 587 535 hw_data->ring_pair_reset = adf_gen4_ring_pair_reset; 588 536 hw_data->enable_pm = adf_gen4_enable_pm;
+1
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
··· 212 212 void (*get_arb_info)(struct arb_info *arb_csrs_info); 213 213 void (*get_admin_info)(struct admin_info *admin_csrs_info); 214 214 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); 215 + u16 (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev); 215 216 int (*alloc_irq)(struct adf_accel_dev *accel_dev); 216 217 void (*free_irq)(struct adf_accel_dev *accel_dev); 217 218 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
+3
drivers/crypto/intel/qat/qat_common/adf_init.c
··· 97 97 return -EFAULT; 98 98 } 99 99 100 + if (hw_data->get_ring_to_svc_map) 101 + hw_data->ring_to_svc_map = hw_data->get_ring_to_svc_map(accel_dev); 102 + 100 103 if (adf_ae_init(accel_dev)) { 101 104 dev_err(&GET_DEV(accel_dev), 102 105 "Failed to initialise Acceleration Engine\n");