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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-phy-realtek-improve-mmd-register-access-for-internal-phy-s'
Heiner Kallweit says:
====================
net: phy: realtek: improve MMD register access for internal PHY's
The integrated PHYs on chip versions from RTL8168g allow to address
MDIO_MMD_VEND2 registers. All c22 standard registers are mapped to
MDIO_MMD_VEND2 registers. So far the paging mechanism is used to
address PHY registers. Add support for c45 ops to address MDIO_MMD_VEND2
registers directly, w/o the paging.
====================
Link: https://patch.msgid.link/c6a969ef-fd7f-48d6-8c48-4bc548831a8d@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+70
-52
+32
drivers/net/ethernet/realtek/r8169_main.c
+32
drivers/net/ethernet/realtek/r8169_main.c
···
5200
5200
return 0;
5201
5201
}
5202
5202
5203
+
static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr,
5204
+
int devnum, int regnum)
5205
+
{
5206
+
struct rtl8169_private *tp = mii_bus->priv;
5207
+
5208
+
if (addr > 0)
5209
+
return -ENODEV;
5210
+
5211
+
if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2)
5212
+
return r8168_phy_ocp_read(tp, regnum);
5213
+
5214
+
return 0;
5215
+
}
5216
+
5217
+
static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr,
5218
+
int devnum, int regnum, u16 val)
5219
+
{
5220
+
struct rtl8169_private *tp = mii_bus->priv;
5221
+
5222
+
if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2)
5223
+
return -ENODEV;
5224
+
5225
+
r8168_phy_ocp_write(tp, regnum, val);
5226
+
5227
+
return 0;
5228
+
}
5229
+
5203
5230
static int r8169_mdio_register(struct rtl8169_private *tp)
5204
5231
{
5205
5232
struct pci_dev *pdev = tp->pci_dev;
···
5256
5229
5257
5230
new_bus->read = r8169_mdio_read_reg;
5258
5231
new_bus->write = r8169_mdio_write_reg;
5232
+
5233
+
if (tp->mac_version >= RTL_GIGA_MAC_VER_40) {
5234
+
new_bus->read_c45 = r8169_mdio_read_reg_c45;
5235
+
new_bus->write_c45 = r8169_mdio_write_reg_c45;
5236
+
}
5259
5237
5260
5238
ret = devm_mdiobus_register(&pdev->dev, new_bus);
5261
5239
if (ret)
+38
-52
drivers/net/phy/realtek/realtek_main.c
+38
-52
drivers/net/phy/realtek/realtek_main.c
···
735
735
return 0;
736
736
}
737
737
738
+
static int rtlgen_read_vend2(struct phy_device *phydev, int regnum)
739
+
{
740
+
return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum);
741
+
}
742
+
743
+
static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val)
744
+
{
745
+
return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum,
746
+
val);
747
+
}
748
+
738
749
static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
739
750
{
740
751
int ret;
741
752
742
-
if (devnum == MDIO_MMD_VEND2) {
743
-
rtl821x_write_page(phydev, regnum >> 4);
744
-
ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
745
-
rtl821x_write_page(phydev, 0);
746
-
} else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
747
-
rtl821x_write_page(phydev, 0xa5c);
748
-
ret = __phy_read(phydev, 0x12);
749
-
rtl821x_write_page(phydev, 0);
750
-
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
751
-
rtl821x_write_page(phydev, 0xa5d);
752
-
ret = __phy_read(phydev, 0x10);
753
-
rtl821x_write_page(phydev, 0);
754
-
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
755
-
rtl821x_write_page(phydev, 0xa5d);
756
-
ret = __phy_read(phydev, 0x11);
757
-
rtl821x_write_page(phydev, 0);
758
-
} else {
753
+
if (devnum == MDIO_MMD_VEND2)
754
+
ret = rtlgen_read_vend2(phydev, regnum);
755
+
else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
756
+
ret = rtlgen_read_vend2(phydev, 0xa5c4);
757
+
else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
758
+
ret = rtlgen_read_vend2(phydev, 0xa5d0);
759
+
else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
760
+
ret = rtlgen_read_vend2(phydev, 0xa5d2);
761
+
else
759
762
ret = -EOPNOTSUPP;
760
-
}
761
763
762
764
return ret;
763
765
}
···
769
767
{
770
768
int ret;
771
769
772
-
if (devnum == MDIO_MMD_VEND2) {
773
-
rtl821x_write_page(phydev, regnum >> 4);
774
-
ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
775
-
rtl821x_write_page(phydev, 0);
776
-
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
777
-
rtl821x_write_page(phydev, 0xa5d);
778
-
ret = __phy_write(phydev, 0x10, val);
779
-
rtl821x_write_page(phydev, 0);
780
-
} else {
770
+
if (devnum == MDIO_MMD_VEND2)
771
+
ret = rtlgen_write_vend2(phydev, regnum, val);
772
+
else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
773
+
ret = rtlgen_write_vend2(phydev, regnum, 0xa5d0);
774
+
else
781
775
ret = -EOPNOTSUPP;
782
-
}
783
776
784
777
return ret;
785
778
}
···
786
789
if (ret != -EOPNOTSUPP)
787
790
return ret;
788
791
789
-
if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
790
-
rtl821x_write_page(phydev, 0xa6e);
791
-
ret = __phy_read(phydev, 0x16);
792
-
rtl821x_write_page(phydev, 0);
793
-
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
794
-
rtl821x_write_page(phydev, 0xa6d);
795
-
ret = __phy_read(phydev, 0x12);
796
-
rtl821x_write_page(phydev, 0);
797
-
} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
798
-
rtl821x_write_page(phydev, 0xa6d);
799
-
ret = __phy_read(phydev, 0x10);
800
-
rtl821x_write_page(phydev, 0);
801
-
}
792
+
if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
793
+
ret = rtlgen_read_vend2(phydev, 0xa6ec);
794
+
else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
795
+
ret = rtlgen_read_vend2(phydev, 0xa6d4);
796
+
else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
797
+
ret = rtlgen_read_vend2(phydev, 0xa6d0);
802
798
803
799
return ret;
804
800
}
···
804
814
if (ret != -EOPNOTSUPP)
805
815
return ret;
806
816
807
-
if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
808
-
rtl821x_write_page(phydev, 0xa6d);
809
-
ret = __phy_write(phydev, 0x12, val);
810
-
rtl821x_write_page(phydev, 0);
811
-
}
817
+
if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
818
+
ret = rtlgen_write_vend2(phydev, 0xa6d4, val);
812
819
813
820
return ret;
814
821
}
···
901
914
{
902
915
int val;
903
916
904
-
val = phy_read_paged(phydev, 0xa61, 0x13);
917
+
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa616);
905
918
if (val < 0)
906
919
return val;
907
920
···
922
935
if (phydev->autoneg == AUTONEG_ENABLE) {
923
936
u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
924
937
925
-
ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
926
-
MDIO_AN_10GBT_CTRL_ADV2_5G |
927
-
MDIO_AN_10GBT_CTRL_ADV5G,
928
-
adv);
938
+
ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xa5d4,
939
+
MDIO_AN_10GBT_CTRL_ADV2_5G |
940
+
MDIO_AN_10GBT_CTRL_ADV5G, adv);
929
941
if (ret < 0)
930
942
return ret;
931
943
}
···
968
982
!phydev->autoneg_complete)
969
983
return 0;
970
984
971
-
lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
985
+
lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xa5d6);
972
986
if (lpadv < 0)
973
987
return lpadv;
974
988