Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2020-05-23' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Things seemed to have quieten down, though no i915 pull (I even gave
them an extra 12 hours in case they were late).
The amdgpu floating point fix is probably the largest, but it just
moves some code around to it doesn't do fpu stuff outside the fpu
boundaries. Otherwise it's just a couple of vmwgfx fixes (maintainer
change) and two etnaviv fixes.
vmwgfx:
- change maintainers
- fix redundant assignment
- fix parameter name
- fix return value
etnaviv:
- memory leak fix when userspace passes a invalid softpin address
- off-by-one crashing the kernel in the perfmon domain iteration when
the GPU core has both 2D and 3D capabilities
amdgpu:
- DP fix
- Floating point fix
- Fix cursor stutter issue"
* tag 'drm-fixes-2020-05-23' of git://anongit.freedesktop.org/drm/drm:
drm/amd/display: Defer cursor lock until after VUPDATE
drm/amd/display: Remove dml_common_def file
drm/amd/display: DP training to set properly SCRAMBLING_DISABLE
drm/edid: Add Oculus Rift S to non-desktop list
drm/etnaviv: Fix a leak in submit_pin_objects()
drm/etnaviv: fix perfmon domain interation
drm/vmwgfx: Return true in function vmw_fence_obj_signaled()
drm/vmwgfx: remove redundant assignment to variable ret
drm/vmwgfx: Fix parameter name in vmw_bo_init
drm/vmwgfx: update MAINTAINERS entry
+137
-103
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
5507
5507
5508
5508
DRM DRIVER FOR VMWARE VIRTUAL GPU
5509
5509
M: "VMware Graphics" <linux-graphics-maintainer@vmware.com>
5510
-
M: Thomas Hellstrom <thellstrom@vmware.com>
5510
+
M: Roland Scheidegger <sroland@vmware.com>
5511
5511
L: dri-devel@lists.freedesktop.org
5512
5512
S: Supported
5513
-
T: git git://people.freedesktop.org/~thomash/linux
5513
+
T: git git://people.freedesktop.org/~sroland/linux
5514
5514
F: drivers/gpu/drm/vmwgfx/
5515
5515
F: include/uapi/drm/vmwgfx_drm.h
5516
5516
+27
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+27
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
···
220
220
return dpcd_tr_pattern;
221
221
}
222
222
223
+
static uint8_t dc_dp_initialize_scrambling_data_symbols(
224
+
struct dc_link *link,
225
+
enum dc_dp_training_pattern pattern)
226
+
{
227
+
uint8_t disable_scrabled_data_symbols = 0;
228
+
229
+
switch (pattern) {
230
+
case DP_TRAINING_PATTERN_SEQUENCE_1:
231
+
case DP_TRAINING_PATTERN_SEQUENCE_2:
232
+
case DP_TRAINING_PATTERN_SEQUENCE_3:
233
+
disable_scrabled_data_symbols = 1;
234
+
break;
235
+
case DP_TRAINING_PATTERN_SEQUENCE_4:
236
+
disable_scrabled_data_symbols = 0;
237
+
break;
238
+
default:
239
+
ASSERT(0);
240
+
DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
241
+
__func__, pattern);
242
+
break;
243
+
}
244
+
return disable_scrabled_data_symbols;
245
+
}
246
+
223
247
static inline bool is_repeater(struct dc_link *link, uint32_t offset)
224
248
{
225
249
return (!link->is_lttpr_mode_transparent && offset != 0);
···
275
251
*****************************************************************/
276
252
dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
277
253
dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
254
+
255
+
dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
256
+
dc_dp_initialize_scrambling_data_symbols(link, pattern);
278
257
279
258
dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
280
259
= dpcd_pattern.raw;
+68
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+68
-1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
···
1625
1625
hws->funcs.verify_allow_pstate_change_high(dc);
1626
1626
}
1627
1627
1628
+
/**
1629
+
* delay_cursor_until_vupdate() - Delay cursor update if too close to VUPDATE.
1630
+
*
1631
+
* Software keepout workaround to prevent cursor update locking from stalling
1632
+
* out cursor updates indefinitely or from old values from being retained in
1633
+
* the case where the viewport changes in the same frame as the cursor.
1634
+
*
1635
+
* The idea is to calculate the remaining time from VPOS to VUPDATE. If it's
1636
+
* too close to VUPDATE, then stall out until VUPDATE finishes.
1637
+
*
1638
+
* TODO: Optimize cursor programming to be once per frame before VUPDATE
1639
+
* to avoid the need for this workaround.
1640
+
*/
1641
+
static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)
1642
+
{
1643
+
struct dc_stream_state *stream = pipe_ctx->stream;
1644
+
struct crtc_position position;
1645
+
uint32_t vupdate_start, vupdate_end;
1646
+
unsigned int lines_to_vupdate, us_to_vupdate, vpos;
1647
+
unsigned int us_per_line, us_vupdate;
1648
+
1649
+
if (!dc->hwss.calc_vupdate_position || !dc->hwss.get_position)
1650
+
return;
1651
+
1652
+
if (!pipe_ctx->stream_res.stream_enc || !pipe_ctx->stream_res.tg)
1653
+
return;
1654
+
1655
+
dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,
1656
+
&vupdate_end);
1657
+
1658
+
dc->hwss.get_position(&pipe_ctx, 1, &position);
1659
+
vpos = position.vertical_count;
1660
+
1661
+
/* Avoid wraparound calculation issues */
1662
+
vupdate_start += stream->timing.v_total;
1663
+
vupdate_end += stream->timing.v_total;
1664
+
vpos += stream->timing.v_total;
1665
+
1666
+
if (vpos <= vupdate_start) {
1667
+
/* VPOS is in VACTIVE or back porch. */
1668
+
lines_to_vupdate = vupdate_start - vpos;
1669
+
} else if (vpos > vupdate_end) {
1670
+
/* VPOS is in the front porch. */
1671
+
return;
1672
+
} else {
1673
+
/* VPOS is in VUPDATE. */
1674
+
lines_to_vupdate = 0;
1675
+
}
1676
+
1677
+
/* Calculate time until VUPDATE in microseconds. */
1678
+
us_per_line =
1679
+
stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz;
1680
+
us_to_vupdate = lines_to_vupdate * us_per_line;
1681
+
1682
+
/* 70 us is a conservative estimate of cursor update time*/
1683
+
if (us_to_vupdate > 70)
1684
+
return;
1685
+
1686
+
/* Stall out until the cursor update completes. */
1687
+
us_vupdate = (vupdate_end - vupdate_start + 1) * us_per_line;
1688
+
udelay(us_to_vupdate + us_vupdate);
1689
+
}
1690
+
1628
1691
void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
1629
1692
{
1630
1693
/* cursor lock is per MPCC tree, so only need to lock one pipe per stream */
1631
1694
if (!pipe || pipe->top_pipe)
1632
1695
return;
1696
+
1697
+
/* Prevent cursor lock from stalling out cursor updates. */
1698
+
if (lock)
1699
+
delay_cursor_until_vupdate(dc, pipe);
1633
1700
1634
1701
dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,
1635
1702
pipe->stream_res.opp->inst, lock);
···
3303
3236
return vertical_line_start;
3304
3237
}
3305
3238
3306
-
static void dcn10_calc_vupdate_position(
3239
+
void dcn10_calc_vupdate_position(
3307
3240
struct dc *dc,
3308
3241
struct pipe_ctx *pipe_ctx,
3309
3242
uint32_t *start_line,
+5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
···
34
34
void dcn10_hw_sequencer_construct(struct dc *dc);
35
35
36
36
int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
37
+
void dcn10_calc_vupdate_position(
38
+
struct dc *dc,
39
+
struct pipe_ctx *pipe_ctx,
40
+
uint32_t *start_line,
41
+
uint32_t *end_line);
37
42
void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
38
43
enum dc_status dcn10_enable_stream_timing(
39
44
struct pipe_ctx *pipe_ctx,
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
···
83
83
.init_vm_ctx = dcn20_init_vm_ctx,
84
84
.set_flip_control_gsl = dcn20_set_flip_control_gsl,
85
85
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
86
+
.calc_vupdate_position = dcn10_calc_vupdate_position,
86
87
};
87
88
88
89
static const struct hwseq_private_funcs dcn20_private_funcs = {
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
···
86
86
.optimize_pwr_state = dcn21_optimize_pwr_state,
87
87
.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
88
88
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
89
+
.calc_vupdate_position = dcn10_calc_vupdate_position,
89
90
.set_cursor_position = dcn10_set_cursor_position,
90
91
.set_cursor_attribute = dcn10_set_cursor_attribute,
91
92
.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
-2
drivers/gpu/drm/amd/display/dc/dml/Makefile
-2
drivers/gpu/drm/amd/display/dc/dml/Makefile
···
63
63
endif
64
64
CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
65
65
CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
66
-
CFLAGS_$(AMDDALPATH)/dc/dml/dml_common_defs.o := $(dml_ccflags)
67
66
68
67
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
69
-
dml_common_defs.o
70
68
71
69
ifdef CONFIG_DRM_AMD_DC_DCN
72
70
DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
-1
drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
+4
-2
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+4
-2
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
···
25
25
#ifndef __DISPLAY_MODE_LIB_H__
26
26
#define __DISPLAY_MODE_LIB_H__
27
27
28
-
29
-
#include "dml_common_defs.h"
28
+
#include "dm_services.h"
29
+
#include "dc_features.h"
30
+
#include "display_mode_structs.h"
31
+
#include "display_mode_enums.h"
30
32
#include "display_mode_vba.h"
31
33
32
34
enum dml_project {
-2
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
-2
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
-1
drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
-1
drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
-2
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
-2
drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h
-43
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
-43
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
···
1
-
/*
2
-
* Copyright 2017 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
* Authors: AMD
23
-
*
24
-
*/
25
-
26
-
#include "dml_common_defs.h"
27
-
#include "dcn_calc_math.h"
28
-
29
-
#include "dml_inline_defs.h"
30
-
31
-
double dml_round(double a)
32
-
{
33
-
double round_pt = 0.5;
34
-
double ceil = dml_ceil(a, 1);
35
-
double floor = dml_floor(a, 1);
36
-
37
-
if (a - floor >= round_pt)
38
-
return ceil;
39
-
else
40
-
return floor;
41
-
}
42
-
43
-
-37
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
-37
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
···
1
-
/*
2
-
* Copyright 2017 Advanced Micro Devices, Inc.
3
-
*
4
-
* Permission is hereby granted, free of charge, to any person obtaining a
5
-
* copy of this software and associated documentation files (the "Software"),
6
-
* to deal in the Software without restriction, including without limitation
7
-
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
-
* and/or sell copies of the Software, and to permit persons to whom the
9
-
* Software is furnished to do so, subject to the following conditions:
10
-
*
11
-
* The above copyright notice and this permission notice shall be included in
12
-
* all copies or substantial portions of the Software.
13
-
*
14
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
-
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
-
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
-
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
-
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
-
* OTHER DEALINGS IN THE SOFTWARE.
21
-
*
22
-
* Authors: AMD
23
-
*
24
-
*/
25
-
26
-
#ifndef __DC_COMMON_DEFS_H__
27
-
#define __DC_COMMON_DEFS_H__
28
-
29
-
#include "dm_services.h"
30
-
#include "dc_features.h"
31
-
#include "display_mode_structs.h"
32
-
#include "display_mode_enums.h"
33
-
34
-
35
-
double dml_round(double a);
36
-
37
-
#endif /* __DC_COMMON_DEFS_H__ */
+13
-2
drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+13
-2
drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
···
26
26
#ifndef __DML_INLINE_DEFS_H__
27
27
#define __DML_INLINE_DEFS_H__
28
28
29
-
#include "dml_common_defs.h"
30
29
#include "dcn_calc_math.h"
31
30
#include "dml_logger.h"
32
31
···
74
75
return (double) dcn_bw_floor2(a, granularity);
75
76
}
76
77
78
+
static inline double dml_round(double a)
79
+
{
80
+
double round_pt = 0.5;
81
+
double ceil = dml_ceil(a, 1);
82
+
double floor = dml_floor(a, 1);
83
+
84
+
if (a - floor >= round_pt)
85
+
return ceil;
86
+
else
87
+
return floor;
88
+
}
89
+
77
90
static inline int dml_log2(double x)
78
91
{
79
92
return dml_round((double)dcn_bw_log(x, 2));
···
123
112
124
113
static inline unsigned int dml_round_to_multiple(unsigned int num,
125
114
unsigned int multiple,
126
-
bool up)
115
+
unsigned char up)
127
116
{
128
117
unsigned int remainder;
129
118
+5
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+5
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
···
92
92
void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
93
93
struct crtc_position *position);
94
94
int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx);
95
+
void (*calc_vupdate_position)(
96
+
struct dc *dc,
97
+
struct pipe_ctx *pipe_ctx,
98
+
uint32_t *start_line,
99
+
uint32_t *end_line);
95
100
void (*enable_per_frame_crtc_position_reset)(struct dc *dc,
96
101
int group_size, struct pipe_ctx *grouped_pipes[]);
97
102
void (*enable_timing_synchronization)(struct dc *dc,
+2
-1
drivers/gpu/drm/drm_edid.c
+2
-1
drivers/gpu/drm/drm_edid.c
···
191
191
{ "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192
192
{ "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
193
193
194
-
/* Oculus Rift DK1, DK2, and CV1 VR Headsets */
194
+
/* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
195
195
{ "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196
196
{ "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197
197
{ "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
198
+
{ "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
198
199
199
200
/* Windows Mixed Reality Headsets */
200
201
{ "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
···
850
850
extern int vmw_bo_init(struct vmw_private *dev_priv,
851
851
struct vmw_buffer_object *vmw_bo,
852
852
size_t size, struct ttm_placement *placement,
853
-
bool interuptable,
853
+
bool interruptible,
854
854
void (*bo_free)(struct ttm_buffer_object *bo));
855
855
extern int vmw_user_bo_verify_access(struct ttm_buffer_object *bo,
856
856
struct ttm_object_file *tfile);
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_fence.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c