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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: rzg2l_adc: Prepare for the addition of RZ/G3S support
The ADC IP available on the RZ/G3S differs slightly from the one found on
the RZ/G2L. The identified differences are as follows:
- different number of channels (one being used for temperature conversion);
consequently, various registers differ
- different default sampling periods
- the RZ/G3S variant lacks the ADVIC register.
To accommodate these differences, the rzg2l_adc driver has been updated by
introducing the struct rzg2l_adc_hw_params, which encapsulates the
hardware-specific differences between the IP variants. A pointer to an
object of type struct rzg2l_adc_hw_params is embedded in
struct rzg2l_adc_data.
Additionally, the completion member of struct rzg2l_adc_data was relocated
to avoid potential padding, if any.
The code has been adjusted to utilize hardware-specific parameters stored
in the new structure instead of relying on plain macros.
The check of chan->channel in rzg2l_adc_read_raw() function, against the
driver specific mask was removed as the subsystem should have already
been done this before reaching the rzg2l_adc_read_raw() function. Along
with it the local variable ch was dropped as chan->channel could be used
instead.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-10-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Claudiu Beznea
and committed by
Jonathan Cameron
a259a846
d7c3e346
+59
-28
+59
-28
drivers/iio/adc/rzg2l_adc.c
+59
-28
drivers/iio/adc/rzg2l_adc.c
···
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#define RZG2L_ADM1_MS BIT(2)
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#define RZG2L_ADM1_BS BIT(4)
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#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
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#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0)
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#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
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#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
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#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)
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#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0)
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#define RZG2L_ADINT 0x20
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#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0)
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#define RZG2L_ADINT_CSEEN BIT(16)
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#define RZG2L_ADINT_INTS BIT(31)
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#define RZG2L_ADSTS 0x24
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#define RZG2L_ADSTS_CSEST BIT(16)
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#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0)
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#define RZG2L_ADIVC 0x28
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#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
···
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#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
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#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
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-
#define RZG2L_ADSMP_DEFAULT_SAMPLING 0x578
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-
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#define RZG2L_ADC_MAX_CHANNELS 8
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#define RZG2L_ADC_CHN_MASK 0x7
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#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
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/**
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* struct rzg2l_adc_hw_params - ADC hardware specific parameters
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* @default_adsmp: default ADC sampling period (see ADM3 register)
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* @adsmp_mask: ADC sampling period mask (see ADM3 register)
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* @adint_inten_mask: conversion end interrupt mask (see ADINT register)
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* @default_adcmp: default ADC cmp (see ADM3 register)
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* @num_channels: number of supported channels
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* @adivc: specifies if ADVIC register is available
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*/
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struct rzg2l_adc_hw_params {
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u16 default_adsmp;
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u16 adsmp_mask;
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u16 adint_inten_mask;
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u8 default_adcmp;
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u8 num_channels;
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bool adivc;
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};
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struct rzg2l_adc_data {
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const struct iio_chan_spec *channels;
···
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void __iomem *base;
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struct reset_control *presetn;
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struct reset_control *adrstn;
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-
struct completion completion;
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const struct rzg2l_adc_data *data;
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const struct rzg2l_adc_hw_params *hw_params;
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struct completion completion;
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struct mutex lock;
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u16 last_val[RZG2L_ADC_MAX_CHANNELS];
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};
···
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static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
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{
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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u32 reg;
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if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
···
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/* Select analog input channel subjected to conversion. */
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
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reg &= ~RZG2L_ADM2_CHSEL_MASK;
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reg &= ~GENMASK(hw_params->num_channels - 1, 0);
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reg |= BIT(ch);
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rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
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···
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*/
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reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
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reg &= ~RZG2L_ADINT_INTS;
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reg &= ~RZG2L_ADINT_INTEN_MASK;
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reg &= ~hw_params->adint_inten_mask;
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reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
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rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
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···
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static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
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{
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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struct device *dev = indio_dev->dev.parent;
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int ret;
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···
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if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
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rzg2l_adc_writel(adc, RZG2L_ADINT,
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rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
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rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
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ret = -ETIMEDOUT;
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}
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···
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{
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struct rzg2l_adc *adc = iio_priv(indio_dev);
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int ret;
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u8 ch;
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switch (mask) {
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case IIO_CHAN_INFO_RAW: {
···
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guard(mutex)(&adc->lock);
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ch = chan->channel & RZG2L_ADC_CHN_MASK;
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ret = rzg2l_adc_conversion(indio_dev, adc, ch);
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ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);
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if (ret)
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return ret;
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*val = adc->last_val[ch];
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*val = adc->last_val[chan->channel];
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return IIO_VAL_INT;
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}
···
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static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
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{
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struct rzg2l_adc *adc = dev_id;
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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unsigned long intst;
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u32 reg;
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int ch;
···
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return IRQ_HANDLED;
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}
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intst = reg & RZG2L_ADSTS_INTST_MASK;
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intst = reg & GENMASK(hw_params->num_channels - 1, 0);
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if (!intst)
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return IRQ_NONE;
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-
for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)
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for_each_set_bit(ch, &intst, hw_params->num_channels)
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adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
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/* clear the channel interrupt */
···
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static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
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{
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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struct iio_chan_spec *chan_array;
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struct rzg2l_adc_data *data;
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unsigned int channel;
···
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if (!num_channels)
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return dev_err_probe(&pdev->dev, -ENODEV, "no channel children\n");
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if (num_channels > RZG2L_ADC_MAX_CHANNELS)
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if (num_channels > hw_params->num_channels)
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return dev_err_probe(&pdev->dev, -EINVAL,
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"num of channel children out of range\n");
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···
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if (ret)
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return ret;
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if (channel >= RZG2L_ADC_MAX_CHANNELS)
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if (channel >= hw_params->num_channels)
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return -EINVAL;
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chan_array[i].type = IIO_VOLTAGE;
···
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static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
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{
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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u32 reg;
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int ret;
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···
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if (ret)
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goto exit_hw_init;
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/* Only division by 4 can be set */
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reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
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reg &= ~RZG2L_ADIVC_DIVADC_MASK;
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reg |= RZG2L_ADIVC_DIVADC_4;
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rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
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if (hw_params->adivc) {
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/* Only division by 4 can be set */
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reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
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reg &= ~RZG2L_ADIVC_DIVADC_MASK;
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reg |= RZG2L_ADIVC_DIVADC_4;
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rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
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}
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/*
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* Setup AMD3
···
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
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reg &= ~RZG2L_ADM3_ADIL_MASK;
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reg &= ~RZG2L_ADM3_ADCMP_MASK;
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reg &= ~RZG2L_ADM3_ADSMP_MASK;
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reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFAULT_SAMPLING);
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reg &= ~hw_params->adsmp_mask;
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reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
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hw_params->default_adsmp;
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rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
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exit_hw_init:
···
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return -ENOMEM;
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adc = iio_priv(indio_dev);
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adc->hw_params = device_get_match_data(dev);
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if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
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return -EINVAL;
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ret = rzg2l_adc_parse_properties(pdev, adc);
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if (ret)
···
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return devm_iio_device_register(dev, indio_dev);
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}
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static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
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.num_channels = 8,
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.default_adcmp = 0xe,
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.default_adsmp = 0x578,
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.adsmp_mask = GENMASK(15, 0),
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.adint_inten_mask = GENMASK(7, 0),
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.adivc = true
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};
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static const struct of_device_id rzg2l_adc_match[] = {
472
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{ .compatible = "renesas,rzg2l-adc",},
459
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{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzg2l_adc_match);