Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mmc-v5.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC host fixes from Ulf Hansson:
- dw_mmc: Fix hang on data CRC error
- mmci: Fix voltage switch procedure for the stm32 variant
- sdhci-iproc: Fix some clock issues for BCM2711
- sdhci-msm: Fixup software timeout value
* tag 'mmc-v5.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
mmc: sdhci-iproc: Set SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN on BCM2711
mmc: sdhci-iproc: Cap min clock frequency on BCM2711
mmc: sdhci-msm: Update the software timeout value for sdhc
mmc: mmci: stm32: Check when the voltage switch procedure should be done
mmc: dw_mmc: Fix hang on data CRC error
+46
-6
+3
-3
drivers/mmc/host/dw_mmc.c
+3
-3
drivers/mmc/host/dw_mmc.c
···
2018
2018
continue;
2019
2019
}
2020
2020
2021
-
dw_mci_stop_dma(host);
2022
2021
send_stop_abort(host, data);
2022
+
dw_mci_stop_dma(host);
2023
2023
state = STATE_SENDING_STOP;
2024
2024
break;
2025
2025
}
···
2043
2043
*/
2044
2044
if (test_and_clear_bit(EVENT_DATA_ERROR,
2045
2045
&host->pending_events)) {
2046
-
dw_mci_stop_dma(host);
2047
2046
if (!(host->data_status & (SDMMC_INT_DRTO |
2048
2047
SDMMC_INT_EBE)))
2049
2048
send_stop_abort(host, data);
2049
+
dw_mci_stop_dma(host);
2050
2050
state = STATE_DATA_ERROR;
2051
2051
break;
2052
2052
}
···
2079
2079
*/
2080
2080
if (test_and_clear_bit(EVENT_DATA_ERROR,
2081
2081
&host->pending_events)) {
2082
-
dw_mci_stop_dma(host);
2083
2082
if (!(host->data_status & (SDMMC_INT_DRTO |
2084
2083
SDMMC_INT_EBE)))
2085
2084
send_stop_abort(host, data);
2085
+
dw_mci_stop_dma(host);
2086
2086
state = STATE_DATA_ERROR;
2087
2087
break;
2088
2088
}
+5
-2
drivers/mmc/host/mmci_stm32_sdmmc.c
+5
-2
drivers/mmc/host/mmci_stm32_sdmmc.c
···
479
479
u32 status;
480
480
int ret = 0;
481
481
482
-
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
483
-
spin_lock_irqsave(&host->lock, flags);
482
+
spin_lock_irqsave(&host->lock, flags);
483
+
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
484
+
host->pwr_reg & MCI_STM32_VSWITCHEN) {
484
485
mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
485
486
spin_unlock_irqrestore(&host->lock, flags);
486
487
···
493
492
494
493
writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
495
494
host->base + MMCICLEAR);
495
+
spin_lock_irqsave(&host->lock, flags);
496
496
mmci_write_pwrreg(host, host->pwr_reg &
497
497
~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
498
498
}
499
+
spin_unlock_irqrestore(&host->lock, flags);
499
500
500
501
return ret;
501
502
}
+20
-1
drivers/mmc/host/sdhci-iproc.c
+20
-1
drivers/mmc/host/sdhci-iproc.c
···
173
173
return pltfm_host->clock;
174
174
}
175
175
176
+
/*
177
+
* There is a known bug on BCM2711's SDHCI core integration where the
178
+
* controller will hang when the difference between the core clock and the bus
179
+
* clock is too great. Specifically this can be reproduced under the following
180
+
* conditions:
181
+
*
182
+
* - No SD card plugged in, polling thread is running, probing cards at
183
+
* 100 kHz.
184
+
* - BCM2711's core clock configured at 500MHz or more
185
+
*
186
+
* So we set 200kHz as the minimum clock frequency available for that SoC.
187
+
*/
188
+
static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
189
+
{
190
+
return 200000;
191
+
}
192
+
176
193
static const struct sdhci_ops sdhci_iproc_ops = {
177
194
.set_clock = sdhci_set_clock,
178
195
.get_max_clock = sdhci_iproc_get_max_clock,
···
288
271
.set_clock = sdhci_set_clock,
289
272
.set_power = sdhci_set_power_and_bus_voltage,
290
273
.get_max_clock = sdhci_iproc_get_max_clock,
274
+
.get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
291
275
.set_bus_width = sdhci_set_bus_width,
292
276
.reset = sdhci_reset,
293
277
.set_uhs_signaling = sdhci_set_uhs_signaling,
294
278
};
295
279
296
280
static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
297
-
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
281
+
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
282
+
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
298
283
.ops = &sdhci_iproc_bcm2711_ops,
299
284
};
300
285
+18
drivers/mmc/host/sdhci-msm.c
+18
drivers/mmc/host/sdhci-msm.c
···
2089
2089
sdhci_cqe_disable(mmc, recovery);
2090
2090
}
2091
2091
2092
+
static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
2093
+
{
2094
+
u32 count, start = 15;
2095
+
2096
+
__sdhci_set_timeout(host, cmd);
2097
+
count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
2098
+
/*
2099
+
* Update software timeout value if its value is less than hardware data
2100
+
* timeout value. Qcom SoC hardware data timeout value was calculated
2101
+
* using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
2102
+
*/
2103
+
if (cmd && cmd->data && host->clock > 400000 &&
2104
+
host->clock <= 50000000 &&
2105
+
((1 << (count + start)) > (10 * host->clock)))
2106
+
host->data_timeout = 22LL * NSEC_PER_SEC;
2107
+
}
2108
+
2092
2109
static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
2093
2110
.enable = sdhci_msm_cqe_enable,
2094
2111
.disable = sdhci_msm_cqe_disable,
···
2455
2438
.irq = sdhci_msm_cqe_irq,
2456
2439
.dump_vendor_regs = sdhci_msm_dump_vendor_regs,
2457
2440
.set_power = sdhci_set_power_noreg,
2441
+
.set_timeout = sdhci_msm_set_timeout,
2458
2442
};
2459
2443
2460
2444
static const struct sdhci_pltfm_data sdhci_msm_pdata = {