Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze
* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Fix msr instruction detection
microblaze: Fix pte_update function
microblaze: Fix asm compilation warning
microblaze: Fix IRQ flag handling for MSR=0
+24
-26
+1
-1
arch/microblaze/include/asm/irqflags.h
+1
-1
arch/microblaze/include/asm/irqflags.h
+12
-13
arch/microblaze/include/asm/pgtable.h
+12
-13
arch/microblaze/include/asm/pgtable.h
···
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static inline unsigned long pte_update(pte_t *p, unsigned long clr,
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unsigned long set)
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{
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unsigned long old, tmp, msr;
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+
unsigned long flags, old, tmp;
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-
__asm__ __volatile__("\
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msrclr %2, 0x2\n\
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-
nop\n\
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-
lw %0, %4, r0\n\
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-
andn %1, %0, %5\n\
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-
or %1, %1, %6\n\
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-
sw %1, %4, r0\n\
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-
mts rmsr, %2\n\
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nop"
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: "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p)
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: "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set), "m" (*p)
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: "cc");
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+
raw_local_irq_save(flags);
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+
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+
__asm__ __volatile__( "lw %0, %2, r0 \n"
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"andn %1, %0, %3 \n"
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+
"or %1, %1, %4 \n"
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+
"sw %1, %2, r0 \n"
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: "=&r" (old), "=&r" (tmp)
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: "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
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+
: "cc");
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+
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+
raw_local_irq_restore(flags);
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return old;
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}
+2
-2
arch/microblaze/kernel/cpu/pvr.c
+2
-2
arch/microblaze/kernel/cpu/pvr.c
···
27
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register unsigned tmp __asm__("r3"); \
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tmp = 0x0; /* Prevent warning about unused */ \
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__asm__ __volatile__ ( \
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"mfs %0, rpvr" #pvrid ";" \
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+
"mfs %0, rpvr" #pvrid ";" \
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: "=r" (tmp) : : "memory"); \
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val = tmp; \
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}
···
54
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if (!(flags & PVR_MSR_BIT))
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return 0;
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-
get_single_pvr(0x00, pvr0);
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+
get_single_pvr(0, pvr0);
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pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
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if (pvr0 & PVR0_PVR_FULL_MASK)
+7
-8
arch/microblaze/kernel/head.S
+7
-8
arch/microblaze/kernel/head.S
···
62
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andi r1, r1, ~2
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mts rmsr, r1
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/*
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* Here is checking mechanism which check if Microblaze has msr instructions
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-
* We load msr and compare it with previous r1 value - if is the same,
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-
* msr instructions works if not - cpu don't have them.
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+
* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
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+
* if the msrclr instruction is not enabled. We use this to detect
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+
* if the opcode is available, by issuing msrclr and then testing the result.
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+
* r8 == 0 - msr instructions are implemented
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+
* r8 != 0 - msr instructions are not implemented
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*/
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/* r8=0 - I have msr instr, 1 - I don't have them */
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rsubi r0, r0, 1 /* set the carry bit */
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-
msrclr r0, 0x4 /* try to clear it */
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/* read the carry bit, r8 will be '0' if msrclr exists */
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addik r8, r0, 0
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+
msrclr r8, 0 /* clear nothing - just read msr for test */
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+
cmpu r8, r8, r1 /* r1 must contain msr reg content */
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74
/* r7 may point to an FDT, or there may be one linked in.
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if it's in r7, we've got to save it away ASAP.
+2
-2
arch/microblaze/kernel/setup.c
+2
-2
arch/microblaze/kernel/setup.c
···
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#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
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if (msr)
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eprintk("!!!Your kernel has setup MSR instruction but "
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-
"CPU don't have it %d\n", msr);
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+
"CPU don't have it %x\n", msr);
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#else
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if (!msr)
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eprintk("!!!Your kernel not setup MSR instruction but "
168
-
"CPU have it %d\n", msr);
168
+
"CPU have it %x\n", msr);
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#endif
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for (src = __ivt_start; src < __ivt_end; src++, dst++)