Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op
ARM: dma-mapping: free allocated page if unable to map
ARM: fix vmlinux.lds.S discarding sections
ARM: nommu: fix warning with checksyscalls.sh
ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeed
+77
-22
+14
arch/arm/Kconfig
+14
arch/arm/Kconfig
···
1283
1283
processor into full low interrupt latency mode. ARM11MPCore
1284
1284
is not affected.
1285
1285
1286
+
config ARM_ERRATA_764369
1287
+
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1288
+
depends on CPU_V7 && SMP
1289
+
help
1290
+
This option enables the workaround for erratum 764369
1291
+
affecting Cortex-A9 MPCore with two or more processors (all
1292
+
current revisions). Under certain timing circumstances, a data
1293
+
cache line maintenance operation by MVA targeting an Inner
1294
+
Shareable memory region may fail to proceed up to either the
1295
+
Point of Coherency or to the Point of Unification of the
1296
+
system. This workaround adds a DSB instruction before the
1297
+
relevant cache maintenance functions and sets a specific bit
1298
+
in the diagnostic control register of the SCU.
1299
+
1286
1300
endmenu
1287
1301
1288
1302
source "arch/arm/common/Kconfig"
+17
-17
arch/arm/include/asm/futex.h
+17
-17
arch/arm/include/asm/futex.h
···
25
25
26
26
#ifdef CONFIG_SMP
27
27
28
-
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
28
+
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
29
29
smp_mb(); \
30
30
__asm__ __volatile__( \
31
-
"1: ldrex %1, [%2]\n" \
31
+
"1: ldrex %1, [%3]\n" \
32
32
" " insn "\n" \
33
-
"2: strex %1, %0, [%2]\n" \
34
-
" teq %1, #0\n" \
33
+
"2: strex %2, %0, [%3]\n" \
34
+
" teq %2, #0\n" \
35
35
" bne 1b\n" \
36
36
" mov %0, #0\n" \
37
-
__futex_atomic_ex_table("%4") \
38
-
: "=&r" (ret), "=&r" (oldval) \
37
+
__futex_atomic_ex_table("%5") \
38
+
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
39
39
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
40
40
: "cc", "memory")
41
41
···
73
73
#include <linux/preempt.h>
74
74
#include <asm/domain.h>
75
75
76
-
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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+
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
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77
__asm__ __volatile__( \
78
-
"1: " T(ldr) " %1, [%2]\n" \
78
+
"1: " T(ldr) " %1, [%3]\n" \
79
79
" " insn "\n" \
80
-
"2: " T(str) " %0, [%2]\n" \
80
+
"2: " T(str) " %0, [%3]\n" \
81
81
" mov %0, #0\n" \
82
-
__futex_atomic_ex_table("%4") \
83
-
: "=&r" (ret), "=&r" (oldval) \
82
+
__futex_atomic_ex_table("%5") \
83
+
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
84
84
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
85
85
: "cc", "memory")
86
86
···
117
117
int cmp = (encoded_op >> 24) & 15;
118
118
int oparg = (encoded_op << 8) >> 20;
119
119
int cmparg = (encoded_op << 20) >> 20;
120
-
int oldval = 0, ret;
120
+
int oldval = 0, ret, tmp;
121
121
122
122
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
123
123
oparg = 1 << oparg;
···
129
129
130
130
switch (op) {
131
131
case FUTEX_OP_SET:
132
-
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
132
+
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
133
133
break;
134
134
case FUTEX_OP_ADD:
135
-
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
135
+
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
136
136
break;
137
137
case FUTEX_OP_OR:
138
-
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
138
+
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
139
139
break;
140
140
case FUTEX_OP_ANDN:
141
-
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
141
+
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
142
142
break;
143
143
case FUTEX_OP_XOR:
144
-
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
144
+
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
145
145
break;
146
146
default:
147
147
ret = -ENOSYS;
+2
-2
arch/arm/include/asm/unistd.h
+2
-2
arch/arm/include/asm/unistd.h
···
478
478
/*
479
479
* Unimplemented (or alternatively implemented) syscalls
480
480
*/
481
-
#define __IGNORE_fadvise64_64 1
482
-
#define __IGNORE_migrate_pages 1
481
+
#define __IGNORE_fadvise64_64
482
+
#define __IGNORE_migrate_pages
483
483
484
484
#endif /* __KERNEL__ */
485
485
#endif /* __ASM_ARM_UNISTD_H */
+10
arch/arm/kernel/smp_scu.c
+10
arch/arm/kernel/smp_scu.c
···
13
13
14
14
#include <asm/smp_scu.h>
15
15
#include <asm/cacheflush.h>
16
+
#include <asm/cputype.h>
16
17
17
18
#define SCU_CTRL 0x00
18
19
#define SCU_CONFIG 0x04
···
37
36
void __init scu_enable(void __iomem *scu_base)
38
37
{
39
38
u32 scu_ctrl;
39
+
40
+
#ifdef CONFIG_ARM_ERRATA_764369
41
+
/* Cortex-A9 only */
42
+
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
43
+
scu_ctrl = __raw_readl(scu_base + 0x30);
44
+
if (!(scu_ctrl & 1))
45
+
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
46
+
}
47
+
#endif
40
48
41
49
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
42
50
/* already enabled? */
+12
-3
arch/arm/kernel/vmlinux.lds.S
+12
-3
arch/arm/kernel/vmlinux.lds.S
···
23
23
24
24
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25
25
#define ARM_EXIT_KEEP(x) x
26
+
#define ARM_EXIT_DISCARD(x)
26
27
#else
27
28
#define ARM_EXIT_KEEP(x)
29
+
#define ARM_EXIT_DISCARD(x) x
28
30
#endif
29
31
30
32
OUTPUT_ARCH(arm)
···
41
39
SECTIONS
42
40
{
43
41
/*
42
+
* XXX: The linker does not define how output sections are
43
+
* assigned to input sections when there are multiple statements
44
+
* matching the same input section name. There is no documented
45
+
* order of matching.
46
+
*
44
47
* unwind exit sections must be discarded before the rest of the
45
48
* unwind sections get included.
46
49
*/
···
54
47
*(.ARM.extab.exit.text)
55
48
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
56
49
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
50
+
ARM_EXIT_DISCARD(EXIT_TEXT)
51
+
ARM_EXIT_DISCARD(EXIT_DATA)
52
+
EXIT_CALL
57
53
#ifndef CONFIG_HOTPLUG
58
54
*(.ARM.exidx.devexit.text)
59
55
*(.ARM.extab.devexit.text)
···
68
58
#ifndef CONFIG_SMP_ON_UP
69
59
*(.alt.smp.init)
70
60
#endif
61
+
*(.discard)
62
+
*(.discard.*)
71
63
}
72
64
73
65
#ifdef CONFIG_XIP_KERNEL
···
291
279
292
280
STABS_DEBUG
293
281
.comment 0 : { *(.comment) }
294
-
295
-
/* Default discards */
296
-
DISCARDS
297
282
}
298
283
299
284
/*
+20
arch/arm/mm/cache-v7.S
+20
arch/arm/mm/cache-v7.S
···
174
174
dcache_line_size r2, r3
175
175
sub r3, r2, #1
176
176
bic r12, r0, r3
177
+
#ifdef CONFIG_ARM_ERRATA_764369
178
+
ALT_SMP(W(dsb))
179
+
ALT_UP(W(nop))
180
+
#endif
177
181
1:
178
182
USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179
183
add r12, r12, r2
···
227
223
add r1, r0, r1
228
224
sub r3, r2, #1
229
225
bic r0, r0, r3
226
+
#ifdef CONFIG_ARM_ERRATA_764369
227
+
ALT_SMP(W(dsb))
228
+
ALT_UP(W(nop))
229
+
#endif
230
230
1:
231
231
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
232
232
add r0, r0, r2
···
255
247
sub r3, r2, #1
256
248
tst r0, r3
257
249
bic r0, r0, r3
250
+
#ifdef CONFIG_ARM_ERRATA_764369
251
+
ALT_SMP(W(dsb))
252
+
ALT_UP(W(nop))
253
+
#endif
258
254
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
259
255
260
256
tst r1, r3
···
282
270
dcache_line_size r2, r3
283
271
sub r3, r2, #1
284
272
bic r0, r0, r3
273
+
#ifdef CONFIG_ARM_ERRATA_764369
274
+
ALT_SMP(W(dsb))
275
+
ALT_UP(W(nop))
276
+
#endif
285
277
1:
286
278
mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
287
279
add r0, r0, r2
···
304
288
dcache_line_size r2, r3
305
289
sub r3, r2, #1
306
290
bic r0, r0, r3
291
+
#ifdef CONFIG_ARM_ERRATA_764369
292
+
ALT_SMP(W(dsb))
293
+
ALT_UP(W(nop))
294
+
#endif
307
295
1:
308
296
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
309
297
add r0, r0, r2