Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+3

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 539 539 /* Constant after initialization */ 540 540 struct amdgpu_device *adev; 541 541 struct drm_gem_object gem_base; 542 + struct amdgpu_bo *parent; 542 543 543 544 struct ttm_bo_kmap_obj dma_buf_vmap; 544 545 pid_t pid; ··· 956 955 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 957 956 /* for interval tree */ 958 957 spinlock_t it_lock; 958 + /* protecting freed */ 959 + spinlock_t freed_lock; 959 960 }; 960 961 961 962 struct amdgpu_vm_manager {

+4 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

··· 222 222 } 223 223 224 224 p->uf.bo = gem_to_amdgpu_bo(gobj); 225 + amdgpu_bo_ref(p->uf.bo); 226 + drm_gem_object_unreference_unlocked(gobj); 225 227 p->uf.offset = fence_data->offset; 226 228 } else { 227 229 ret = -EINVAL; ··· 489 487 amdgpu_ib_free(parser->adev, &parser->ibs[i]); 490 488 kfree(parser->ibs); 491 489 if (parser->uf.bo) 492 - drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); 490 + amdgpu_bo_unref(&parser->uf.bo); 493 491 } 494 492 495 493 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, ··· 778 776 amdgpu_ib_free(job->adev, &job->ibs[i]); 779 777 kfree(job->ibs); 780 778 if (job->uf.bo) 781 - drm_gem_object_unreference_unlocked(&job->uf.bo->gem_base); 779 + amdgpu_bo_unref(&job->uf.bo); 782 780 return 0; 783 781 } 784 782

+79 -29

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

··· 73 73 struct drm_crtc *crtc = &amdgpuCrtc->base; 74 74 unsigned long flags; 75 75 unsigned i; 76 + int vpos, hpos, stat, min_udelay; 77 + struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 76 78 77 79 amdgpu_flip_wait_fence(adev, &work->excl); 78 80 for (i = 0; i < work->shared_count; ++i) ··· 82 80 83 81 /* We borrow the event spin lock for protecting flip_status */ 84 82 spin_lock_irqsave(&crtc->dev->event_lock, flags); 83 + 84 + /* If this happens to execute within the "virtually extended" vblank 85 + * interval before the start of the real vblank interval then it needs 86 + * to delay programming the mmio flip until the real vblank is entered. 87 + * This prevents completing a flip too early due to the way we fudge 88 + * our vblank counter and vblank timestamps in order to work around the 89 + * problem that the hw fires vblank interrupts before actual start of 90 + * vblank (when line buffer refilling is done for a frame). It 91 + * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for 92 + * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. 93 + * 94 + * In practice this won't execute very often unless on very fast 95 + * machines because the time window for this to happen is very small. 96 + */ 97 + for (;;) { 98 + /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 99 + * start in hpos, and to the "fudged earlier" vblank start in 100 + * vpos. 101 + */ 102 + stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 103 + GET_DISTANCE_TO_VBLANKSTART, 104 + &vpos, &hpos, NULL, NULL, 105 + &crtc->hwmode); 106 + 107 + if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 108 + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 109 + !(vpos >= 0 && hpos <= 0)) 110 + break; 111 + 112 + /* Sleep at least until estimated real start of hw vblank */ 113 + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 114 + min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 115 + usleep_range(min_udelay, 2 * min_udelay); 116 + spin_lock_irqsave(&crtc->dev->event_lock, flags); 117 + }; 85 118 86 119 /* do the flip (mmio) */ 87 120 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); ··· 146 109 } else 147 110 DRM_ERROR("failed to reserve buffer after flip\n"); 148 111 149 - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 112 + amdgpu_bo_unref(&work->old_rbo); 150 113 kfree(work->shared); 151 114 kfree(work); 152 115 } ··· 185 148 obj = old_amdgpu_fb->obj; 186 149 187 150 /* take a reference to the old object */ 188 - drm_gem_object_reference(obj); 189 151 work->old_rbo = gem_to_amdgpu_bo(obj); 152 + amdgpu_bo_ref(work->old_rbo); 190 153 191 154 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 192 155 obj = new_amdgpu_fb->obj; ··· 259 222 amdgpu_bo_unreserve(new_rbo); 260 223 261 224 cleanup: 262 - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); 225 + amdgpu_bo_unref(&work->old_rbo); 263 226 fence_put(work->excl); 264 227 for (i = 0; i < work->shared_count; ++i) 265 228 fence_put(work->shared[i]); ··· 749 712 * \param dev Device to query. 750 713 * \param pipe Crtc to query. 751 714 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 715 + * For driver internal use only also supports these flags: 716 + * 717 + * USE_REAL_VBLANKSTART to use the real start of vblank instead 718 + * of a fudged earlier start of vblank. 719 + * 720 + * GET_DISTANCE_TO_VBLANKSTART to return distance to the 721 + * fudged earlier start of vblank in *vpos and the distance 722 + * to true start of vblank in *hpos. 723 + * 752 724 * \param *vpos Location where vertical scanout position should be stored. 753 725 * \param *hpos Location where horizontal scanout position should go. 754 726 * \param *stime Target location for timestamp taken immediately before ··· 822 776 vbl_end = 0; 823 777 } 824 778 779 + /* Called from driver internal vblank counter query code? */ 780 + if (flags & GET_DISTANCE_TO_VBLANKSTART) { 781 + /* Caller wants distance from real vbl_start in *hpos */ 782 + *hpos = *vpos - vbl_start; 783 + } 784 + 785 + /* Fudge vblank to start a few scanlines earlier to handle the 786 + * problem that vblank irqs fire a few scanlines before start 787 + * of vblank. Some driver internal callers need the true vblank 788 + * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 789 + * 790 + * The cause of the "early" vblank irq is that the irq is triggered 791 + * by the line buffer logic when the line buffer read position enters 792 + * the vblank, whereas our crtc scanout position naturally lags the 793 + * line buffer read position. 794 + */ 795 + if (!(flags & USE_REAL_VBLANKSTART)) 796 + vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 797 + 825 798 /* Test scanout position against vblank region. */ 826 799 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 827 800 in_vbl = false; 801 + 802 + /* In vblank? */ 803 + if (in_vbl) 804 + ret |= DRM_SCANOUTPOS_IN_VBLANK; 805 + 806 + /* Called from driver internal vblank counter query code? */ 807 + if (flags & GET_DISTANCE_TO_VBLANKSTART) { 808 + /* Caller wants distance from fudged earlier vbl_start */ 809 + *vpos -= vbl_start; 810 + return ret; 811 + } 828 812 829 813 /* Check if inside vblank area and apply corrective offsets: 830 814 * vpos will then be >=0 in video scanout area, but negative ··· 870 794 871 795 /* Correct for shifted end of vbl at vbl_end. */ 872 796 *vpos = *vpos - vbl_end; 873 - 874 - /* In vblank? */ 875 - if (in_vbl) 876 - ret |= DRM_SCANOUTPOS_IN_VBLANK; 877 - 878 - /* Is vpos outside nominal vblank area, but less than 879 - * 1/100 of a frame height away from start of vblank? 880 - * If so, assume this isn't a massively delayed vblank 881 - * interrupt, but a vblank interrupt that fired a few 882 - * microseconds before true start of vblank. Compensate 883 - * by adding a full frame duration to the final timestamp. 884 - * Happens, e.g., on ATI R500, R600. 885 - * 886 - * We only do this if DRM_CALLED_FROM_VBLIRQ. 887 - */ 888 - if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 889 - vbl_start = mode->crtc_vdisplay; 890 - vtotal = mode->crtc_vtotal; 891 - 892 - if (vbl_start - *vpos < vtotal / 100) { 893 - *vpos -= vtotal; 894 - 895 - /* Signal this correction as "applied". */ 896 - ret |= 0x8; 897 - } 898 - } 899 797 900 798 return ret; 901 799 }

+3 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

··· 235 235 AMDGPU_GEM_USERPTR_REGISTER)) 236 236 return -EINVAL; 237 237 238 - if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || 239 - !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 238 + if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && ( 239 + !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || 240 + !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) { 240 241 241 242 /* if we want to write to it we must require anonymous 242 243 memory and install a MMU notifier */

+47 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

··· 611 611 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 612 612 { 613 613 struct amdgpu_device *adev = dev->dev_private; 614 + int vpos, hpos, stat; 615 + u32 count; 614 616 615 617 if (pipe >= adev->mode_info.num_crtc) { 616 618 DRM_ERROR("Invalid crtc %u\n", pipe); 617 619 return -EINVAL; 618 620 } 619 621 620 - return amdgpu_display_vblank_get_counter(adev, pipe); 622 + /* The hw increments its frame counter at start of vsync, not at start 623 + * of vblank, as is required by DRM core vblank counter handling. 624 + * Cook the hw count here to make it appear to the caller as if it 625 + * incremented at start of vblank. We measure distance to start of 626 + * vblank in vpos. vpos therefore will be >= 0 between start of vblank 627 + * and start of vsync, so vpos >= 0 means to bump the hw frame counter 628 + * result by 1 to give the proper appearance to caller. 629 + */ 630 + if (adev->mode_info.crtcs[pipe]) { 631 + /* Repeat readout if needed to provide stable result if 632 + * we cross start of vsync during the queries. 633 + */ 634 + do { 635 + count = amdgpu_display_vblank_get_counter(adev, pipe); 636 + /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 637 + * distance to start of vblank, instead of regular 638 + * vertical scanout pos. 639 + */ 640 + stat = amdgpu_get_crtc_scanoutpos( 641 + dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 642 + &vpos, &hpos, NULL, NULL, 643 + &adev->mode_info.crtcs[pipe]->base.hwmode); 644 + } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 645 + 646 + if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 647 + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 648 + DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 649 + } else { 650 + DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 651 + pipe, vpos); 652 + 653 + /* Bump counter if we are at >= leading edge of vblank, 654 + * but before vsync where vpos would turn negative and 655 + * the hw counter really increments. 656 + */ 657 + if (vpos >= 0) 658 + count++; 659 + } 660 + } else { 661 + /* Fallback to use value as is. */ 662 + count = amdgpu_display_vblank_get_counter(adev, pipe); 663 + DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 664 + } 665 + 666 + return count; 621 667 } 622 668 623 669 /**

+5

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

··· 407 407 u32 line_time; 408 408 u32 wm_low; 409 409 u32 wm_high; 410 + u32 lb_vblank_lead_lines; 410 411 struct drm_display_mode hw_mode; 411 412 }; 412 413 ··· 528 527 529 528 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 530 529 ((em) == ATOM_ENCODER_MODE_DP_MST)) 530 + 531 + /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 532 + #define USE_REAL_VBLANKSTART (1 << 30) 533 + #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 531 534 532 535 void amdgpu_link_encoder_connector(struct drm_device *dev); 533 536

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

··· 100 100 list_del_init(&bo->list); 101 101 mutex_unlock(&bo->adev->gem.mutex); 102 102 drm_gem_object_release(&bo->gem_base); 103 + amdgpu_bo_unref(&bo->parent); 103 104 kfree(bo->metadata); 104 105 kfree(bo); 105 106 }

+11 -6

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

··· 587 587 uint32_t flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); 588 588 int r; 589 589 590 - if (gtt->userptr) 591 - amdgpu_ttm_tt_pin_userptr(ttm); 592 - 590 + if (gtt->userptr) { 591 + r = amdgpu_ttm_tt_pin_userptr(ttm); 592 + if (r) { 593 + DRM_ERROR("failed to pin userptr\n"); 594 + return r; 595 + } 596 + } 593 597 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 594 598 if (!ttm->num_pages) { 595 599 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", ··· 801 797 if (mem && mem->mem_type != TTM_PL_SYSTEM) 802 798 flags |= AMDGPU_PTE_VALID; 803 799 804 - if (mem && mem->mem_type == TTM_PL_TT) 800 + if (mem && mem->mem_type == TTM_PL_TT) { 805 801 flags |= AMDGPU_PTE_SYSTEM; 806 802 807 - if (!ttm || ttm->caching_state == tt_cached) 808 - flags |= AMDGPU_PTE_SNOOPED; 803 + if (ttm->caching_state == tt_cached) 804 + flags |= AMDGPU_PTE_SNOOPED; 805 + } 809 806 810 807 if (adev->asic_type >= CHIP_TOPAZ) 811 808 flags |= AMDGPU_PTE_EXECUTABLE;

+18 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 885 885 struct amdgpu_bo_va_mapping *mapping; 886 886 int r; 887 887 888 + spin_lock(&vm->freed_lock); 888 889 while (!list_empty(&vm->freed)) { 889 890 mapping = list_first_entry(&vm->freed, 890 891 struct amdgpu_bo_va_mapping, list); 891 892 list_del(&mapping->list); 892 - 893 + spin_unlock(&vm->freed_lock); 893 894 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL); 894 895 kfree(mapping); 895 896 if (r) 896 897 return r; 897 898 899 + spin_lock(&vm->freed_lock); 898 900 } 901 + spin_unlock(&vm->freed_lock); 902 + 899 903 return 0; 900 904 901 905 } ··· 1083 1079 if (r) 1084 1080 goto error_free; 1085 1081 1082 + /* Keep a reference to the page table to avoid freeing 1083 + * them up in the wrong order. 1084 + */ 1085 + pt->parent = amdgpu_bo_ref(vm->page_directory); 1086 + 1086 1087 r = amdgpu_vm_clear_bo(adev, pt); 1087 1088 if (r) { 1088 1089 amdgpu_bo_unref(&pt); ··· 1159 1150 spin_unlock(&vm->it_lock); 1160 1151 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1161 1152 1162 - if (valid) 1153 + if (valid) { 1154 + spin_lock(&vm->freed_lock); 1163 1155 list_add(&mapping->list, &vm->freed); 1164 - else 1156 + spin_unlock(&vm->freed_lock); 1157 + } else { 1165 1158 kfree(mapping); 1159 + } 1166 1160 1167 1161 return 0; 1168 1162 } ··· 1198 1186 interval_tree_remove(&mapping->it, &vm->va); 1199 1187 spin_unlock(&vm->it_lock); 1200 1188 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1189 + spin_lock(&vm->freed_lock); 1201 1190 list_add(&mapping->list, &vm->freed); 1191 + spin_unlock(&vm->freed_lock); 1202 1192 } 1203 1193 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { 1204 1194 list_del(&mapping->list); ··· 1261 1247 INIT_LIST_HEAD(&vm->cleared); 1262 1248 INIT_LIST_HEAD(&vm->freed); 1263 1249 spin_lock_init(&vm->it_lock); 1250 + spin_lock_init(&vm->freed_lock); 1264 1251 pd_size = amdgpu_vm_directory_size(adev); 1265 1252 pd_entries = amdgpu_vm_num_pdes(adev); 1266 1253

+4 -1

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

··· 1250 1250 u32 pixel_period; 1251 1251 u32 line_time = 0; 1252 1252 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1253 - u32 tmp, wm_mask; 1253 + u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1254 1254 1255 1255 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1256 1256 pixel_period = 1000000 / (u32)mode->clock; ··· 1333 1333 (adev->mode_info.disp_priority == 2)) { 1334 1334 DRM_DEBUG_KMS("force priority to high\n"); 1335 1335 } 1336 + lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1336 1337 } 1337 1338 1338 1339 /* select wm A */ ··· 1358 1357 amdgpu_crtc->line_time = line_time; 1359 1358 amdgpu_crtc->wm_high = latency_watermark_a; 1360 1359 amdgpu_crtc->wm_low = latency_watermark_b; 1360 + /* Save number of lines the linebuffer leads before the scanout */ 1361 + amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1361 1362 } 1362 1363 1363 1364 /**

+4 -1

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

··· 1238 1238 u32 pixel_period; 1239 1239 u32 line_time = 0; 1240 1240 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1241 - u32 tmp, wm_mask; 1241 + u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1242 1242 1243 1243 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1244 1244 pixel_period = 1000000 / (u32)mode->clock; ··· 1321 1321 (adev->mode_info.disp_priority == 2)) { 1322 1322 DRM_DEBUG_KMS("force priority to high\n"); 1323 1323 } 1324 + lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1324 1325 } 1325 1326 1326 1327 /* select wm A */ ··· 1346 1345 amdgpu_crtc->line_time = line_time; 1347 1346 amdgpu_crtc->wm_high = latency_watermark_a; 1348 1347 amdgpu_crtc->wm_low = latency_watermark_b; 1348 + /* Save number of lines the linebuffer leads before the scanout */ 1349 + amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1349 1350 } 1350 1351 1351 1352 /**

+4 -1

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

··· 1193 1193 u32 pixel_period; 1194 1194 u32 line_time = 0; 1195 1195 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1196 - u32 tmp, wm_mask; 1196 + u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1197 1197 1198 1198 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1199 1199 pixel_period = 1000000 / (u32)mode->clock; ··· 1276 1276 (adev->mode_info.disp_priority == 2)) { 1277 1277 DRM_DEBUG_KMS("force priority to high\n"); 1278 1278 } 1279 + lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1279 1280 } 1280 1281 1281 1282 /* select wm A */ ··· 1303 1302 amdgpu_crtc->line_time = line_time; 1304 1303 amdgpu_crtc->wm_high = latency_watermark_a; 1305 1304 amdgpu_crtc->wm_low = latency_watermark_b; 1305 + /* Save number of lines the linebuffer leads before the scanout */ 1306 + amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1306 1307 } 1307 1308 1308 1309 /**

+1 -1

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

··· 513 513 WREG32(mmVM_L2_CNTL3, tmp); 514 514 /* setup context0 */ 515 515 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 516 - WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1); 516 + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 517 517 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 518 518 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 519 519 (u32)(adev->dummy_page.addr >> 12));

+1 -1

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

··· 657 657 WREG32(mmVM_L2_CNTL4, tmp); 658 658 /* setup context0 */ 659 659 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 660 - WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, (adev->mc.gtt_end >> 12) - 1); 660 + WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 661 661 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 662 662 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 663 663 (u32)(adev->dummy_page.addr >> 12));

+3 -2

drivers/gpu/drm/amd/scheduler/gpu_scheduler.c

··· 288 288 */ 289 289 static bool amd_sched_entity_in(struct amd_sched_job *sched_job) 290 290 { 291 + struct amd_gpu_scheduler *sched = sched_job->sched; 291 292 struct amd_sched_entity *entity = sched_job->s_entity; 292 293 bool added, first = false; 293 294 ··· 303 302 304 303 /* first job wakes up scheduler */ 305 304 if (first) 306 - amd_sched_wakeup(sched_job->sched); 305 + amd_sched_wakeup(sched); 307 306 308 307 return added; 309 308 } ··· 319 318 { 320 319 struct amd_sched_entity *entity = sched_job->s_entity; 321 320 321 + trace_amd_sched_job(sched_job); 322 322 wait_event(entity->sched->job_scheduled, 323 323 amd_sched_entity_in(sched_job)); 324 - trace_amd_sched_job(sched_job); 325 324 } 326 325 327 326 /**

+5

drivers/gpu/drm/drm_drv.c

··· 160 160 goto out_unlock; 161 161 } 162 162 163 + if (!file_priv->allowed_master) { 164 + ret = drm_new_set_master(dev, file_priv); 165 + goto out_unlock; 166 + } 167 + 163 168 file_priv->minor->master = drm_master_get(file_priv->master); 164 169 file_priv->is_master = 1; 165 170 if (dev->driver->master_set) {

+56 -28

drivers/gpu/drm/drm_fops.c

··· 126 126 } 127 127 128 128 /** 129 + * drm_new_set_master - Allocate a new master object and become master for the 130 + * associated master realm. 131 + * 132 + * @dev: The associated device. 133 + * @fpriv: File private identifying the client. 134 + * 135 + * This function must be called with dev::struct_mutex held. 136 + * Returns negative error code on failure. Zero on success. 137 + */ 138 + int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv) 139 + { 140 + struct drm_master *old_master; 141 + int ret; 142 + 143 + lockdep_assert_held_once(&dev->master_mutex); 144 + 145 + /* create a new master */ 146 + fpriv->minor->master = drm_master_create(fpriv->minor); 147 + if (!fpriv->minor->master) 148 + return -ENOMEM; 149 + 150 + /* take another reference for the copy in the local file priv */ 151 + old_master = fpriv->master; 152 + fpriv->master = drm_master_get(fpriv->minor->master); 153 + 154 + if (dev->driver->master_create) { 155 + ret = dev->driver->master_create(dev, fpriv->master); 156 + if (ret) 157 + goto out_err; 158 + } 159 + if (dev->driver->master_set) { 160 + ret = dev->driver->master_set(dev, fpriv, true); 161 + if (ret) 162 + goto out_err; 163 + } 164 + 165 + fpriv->is_master = 1; 166 + fpriv->allowed_master = 1; 167 + fpriv->authenticated = 1; 168 + if (old_master) 169 + drm_master_put(&old_master); 170 + 171 + return 0; 172 + 173 + out_err: 174 + /* drop both references and restore old master on failure */ 175 + drm_master_put(&fpriv->minor->master); 176 + drm_master_put(&fpriv->master); 177 + fpriv->master = old_master; 178 + 179 + return ret; 180 + } 181 + 182 + /** 129 183 * Called whenever a process opens /dev/drm. 130 184 * 131 185 * \param filp file pointer. ··· 243 189 mutex_lock(&dev->master_mutex); 244 190 if (drm_is_primary_client(priv) && !priv->minor->master) { 245 191 /* create a new master */ 246 - priv->minor->master = drm_master_create(priv->minor); 247 - if (!priv->minor->master) { 248 - ret = -ENOMEM; 192 + ret = drm_new_set_master(dev, priv); 193 + if (ret) 249 194 goto out_close; 250 - } 251 - 252 - priv->is_master = 1; 253 - /* take another reference for the copy in the local file priv */ 254 - priv->master = drm_master_get(priv->minor->master); 255 - priv->authenticated = 1; 256 - 257 - if (dev->driver->master_create) { 258 - ret = dev->driver->master_create(dev, priv->master); 259 - if (ret) { 260 - /* drop both references if this fails */ 261 - drm_master_put(&priv->minor->master); 262 - drm_master_put(&priv->master); 263 - goto out_close; 264 - } 265 - } 266 - if (dev->driver->master_set) { 267 - ret = dev->driver->master_set(dev, priv, true); 268 - if (ret) { 269 - /* drop both references if this fails */ 270 - drm_master_put(&priv->minor->master); 271 - drm_master_put(&priv->master); 272 - goto out_close; 273 - } 274 - } 275 195 } else if (drm_is_primary_client(priv)) { 276 196 /* get a reference to the master */ 277 197 priv->master = drm_master_get(priv->minor->master);

+53 -1

drivers/gpu/drm/drm_irq.c

··· 980 980 struct drm_pending_vblank_event *e, 981 981 unsigned long seq, struct timeval *now) 982 982 { 983 - WARN_ON_SMP(!spin_is_locked(&dev->event_lock)); 983 + assert_spin_locked(&dev->event_lock); 984 + 984 985 e->event.sequence = seq; 985 986 e->event.tv_sec = now->tv_sec; 986 987 e->event.tv_usec = now->tv_usec; ··· 992 991 trace_drm_vblank_event_delivered(e->base.pid, e->pipe, 993 992 e->event.sequence); 994 993 } 994 + 995 + /** 996 + * drm_arm_vblank_event - arm vblank event after pageflip 997 + * @dev: DRM device 998 + * @pipe: CRTC index 999 + * @e: the event to prepare to send 1000 + * 1001 + * A lot of drivers need to generate vblank events for the very next vblank 1002 + * interrupt. For example when the page flip interrupt happens when the page 1003 + * flip gets armed, but not when it actually executes within the next vblank 1004 + * period. This helper function implements exactly the required vblank arming 1005 + * behaviour. 1006 + * 1007 + * Caller must hold event lock. Caller must also hold a vblank reference for 1008 + * the event @e, which will be dropped when the next vblank arrives. 1009 + * 1010 + * This is the legacy version of drm_crtc_arm_vblank_event(). 1011 + */ 1012 + void drm_arm_vblank_event(struct drm_device *dev, unsigned int pipe, 1013 + struct drm_pending_vblank_event *e) 1014 + { 1015 + assert_spin_locked(&dev->event_lock); 1016 + 1017 + e->pipe = pipe; 1018 + e->event.sequence = drm_vblank_count(dev, pipe); 1019 + list_add_tail(&e->base.link, &dev->vblank_event_list); 1020 + } 1021 + EXPORT_SYMBOL(drm_arm_vblank_event); 1022 + 1023 + /** 1024 + * drm_crtc_arm_vblank_event - arm vblank event after pageflip 1025 + * @crtc: the source CRTC of the vblank event 1026 + * @e: the event to send 1027 + * 1028 + * A lot of drivers need to generate vblank events for the very next vblank 1029 + * interrupt. For example when the page flip interrupt happens when the page 1030 + * flip gets armed, but not when it actually executes within the next vblank 1031 + * period. This helper function implements exactly the required vblank arming 1032 + * behaviour. 1033 + * 1034 + * Caller must hold event lock. Caller must also hold a vblank reference for 1035 + * the event @e, which will be dropped when the next vblank arrives. 1036 + * 1037 + * This is the native KMS version of drm_arm_vblank_event(). 1038 + */ 1039 + void drm_crtc_arm_vblank_event(struct drm_crtc *crtc, 1040 + struct drm_pending_vblank_event *e) 1041 + { 1042 + drm_arm_vblank_event(crtc->dev, drm_crtc_index(crtc), e); 1043 + } 1044 + EXPORT_SYMBOL(drm_crtc_arm_vblank_event); 995 1045 996 1046 /** 997 1047 * drm_send_vblank_event - helper to send vblank event after pageflip

+2

drivers/gpu/drm/i915/i915_debugfs.c

··· 2734 2734 return "AUX_C"; 2735 2735 case POWER_DOMAIN_AUX_D: 2736 2736 return "AUX_D"; 2737 + case POWER_DOMAIN_GMBUS: 2738 + return "GMBUS"; 2737 2739 case POWER_DOMAIN_INIT: 2738 2740 return "INIT"; 2739 2741 default:

+1

drivers/gpu/drm/i915/i915_drv.h

··· 199 199 POWER_DOMAIN_AUX_B, 200 200 POWER_DOMAIN_AUX_C, 201 201 POWER_DOMAIN_AUX_D, 202 + POWER_DOMAIN_GMBUS, 202 203 POWER_DOMAIN_INIT, 203 204 204 205 POWER_DOMAIN_NUM,

+10 -2

drivers/gpu/drm/i915/i915_gem.c

··· 1210 1210 if (i915_gem_request_completed(req, true)) 1211 1211 return 0; 1212 1212 1213 - timeout_expire = timeout ? 1214 - jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; 1213 + timeout_expire = 0; 1214 + if (timeout) { 1215 + if (WARN_ON(*timeout < 0)) 1216 + return -EINVAL; 1217 + 1218 + if (*timeout == 0) 1219 + return -ETIME; 1220 + 1221 + timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); 1222 + } 1215 1223 1216 1224 if (INTEL_INFO(dev_priv)->gen >= 6) 1217 1225 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);

+27 -9

drivers/gpu/drm/i915/i915_gem_fence.c

··· 642 642 } 643 643 644 644 /* check for L-shaped memory aka modified enhanced addressing */ 645 - if (IS_GEN4(dev)) { 646 - uint32_t ddc2 = I915_READ(DCC2); 647 - 648 - if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) 649 - dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES; 645 + if (IS_GEN4(dev) && 646 + !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { 647 + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 648 + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 650 649 } 651 650 652 651 if (dcc == 0xffffffff) { ··· 674 675 * matching, which was the case for the swizzling required in 675 676 * the table above, or from the 1-ch value being less than 676 677 * the minimum size of a rank. 678 + * 679 + * Reports indicate that the swizzling actually 680 + * varies depending upon page placement inside the 681 + * channels, i.e. we see swizzled pages where the 682 + * banks of memory are paired and unswizzled on the 683 + * uneven portion, so leave that as unknown. 677 684 */ 678 - if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { 679 - swizzle_x = I915_BIT_6_SWIZZLE_NONE; 680 - swizzle_y = I915_BIT_6_SWIZZLE_NONE; 681 - } else { 685 + if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) { 682 686 swizzle_x = I915_BIT_6_SWIZZLE_9_10; 683 687 swizzle_y = I915_BIT_6_SWIZZLE_9; 684 688 } 689 + } 690 + 691 + if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN || 692 + swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) { 693 + /* Userspace likes to explode if it sees unknown swizzling, 694 + * so lie. We will finish the lie when reporting through 695 + * the get-tiling-ioctl by reporting the physical swizzle 696 + * mode as unknown instead. 697 + * 698 + * As we don't strictly know what the swizzling is, it may be 699 + * bit17 dependent, and so we need to also prevent the pages 700 + * from being moved. 701 + */ 702 + dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES; 703 + swizzle_x = I915_BIT_6_SWIZZLE_NONE; 704 + swizzle_y = I915_BIT_6_SWIZZLE_NONE; 685 705 } 686 706 687 707 dev_priv->mm.bit_6_swizzle_x = swizzle_x;

+51 -2

drivers/gpu/drm/i915/intel_display.c

··· 5194 5194 case PORT_E: 5195 5195 return POWER_DOMAIN_PORT_DDI_E_2_LANES; 5196 5196 default: 5197 - WARN_ON_ONCE(1); 5197 + MISSING_CASE(port); 5198 5198 return POWER_DOMAIN_PORT_OTHER; 5199 + } 5200 + } 5201 + 5202 + static enum intel_display_power_domain port_to_aux_power_domain(enum port port) 5203 + { 5204 + switch (port) { 5205 + case PORT_A: 5206 + return POWER_DOMAIN_AUX_A; 5207 + case PORT_B: 5208 + return POWER_DOMAIN_AUX_B; 5209 + case PORT_C: 5210 + return POWER_DOMAIN_AUX_C; 5211 + case PORT_D: 5212 + return POWER_DOMAIN_AUX_D; 5213 + case PORT_E: 5214 + /* FIXME: Check VBT for actual wiring of PORT E */ 5215 + return POWER_DOMAIN_AUX_D; 5216 + default: 5217 + MISSING_CASE(port); 5218 + return POWER_DOMAIN_AUX_A; 5199 5219 } 5200 5220 } 5201 5221 ··· 5247 5227 return POWER_DOMAIN_PORT_DSI; 5248 5228 default: 5249 5229 return POWER_DOMAIN_PORT_OTHER; 5230 + } 5231 + } 5232 + 5233 + enum intel_display_power_domain 5234 + intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) 5235 + { 5236 + struct drm_device *dev = intel_encoder->base.dev; 5237 + struct intel_digital_port *intel_dig_port; 5238 + 5239 + switch (intel_encoder->type) { 5240 + case INTEL_OUTPUT_UNKNOWN: 5241 + case INTEL_OUTPUT_HDMI: 5242 + /* 5243 + * Only DDI platforms should ever use these output types. 5244 + * We can get here after the HDMI detect code has already set 5245 + * the type of the shared encoder. Since we can't be sure 5246 + * what's the status of the given connectors, play safe and 5247 + * run the DP detection too. 5248 + */ 5249 + WARN_ON_ONCE(!HAS_DDI(dev)); 5250 + case INTEL_OUTPUT_DISPLAYPORT: 5251 + case INTEL_OUTPUT_EDP: 5252 + intel_dig_port = enc_to_dig_port(&intel_encoder->base); 5253 + return port_to_aux_power_domain(intel_dig_port->port); 5254 + case INTEL_OUTPUT_DP_MST: 5255 + intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; 5256 + return port_to_aux_power_domain(intel_dig_port->port); 5257 + default: 5258 + MISSING_CASE(intel_encoder->type); 5259 + return POWER_DOMAIN_AUX_A; 5250 5260 } 5251 5261 } 5252 5262 ··· 12510 12460 if (INTEL_INFO(dev)->gen < 8) { 12511 12461 PIPE_CONF_CHECK_M_N(dp_m_n); 12512 12462 12513 - PIPE_CONF_CHECK_I(has_drrs); 12514 12463 if (current_config->has_drrs) 12515 12464 PIPE_CONF_CHECK_M_N(dp_m2_n2); 12516 12465 } else

+16 -35

drivers/gpu/drm/i915/intel_dp.c

··· 277 277 * See vlv_power_sequencer_reset() why we need 278 278 * a power domain reference here. 279 279 */ 280 - power_domain = intel_display_port_power_domain(encoder); 280 + power_domain = intel_display_port_aux_power_domain(encoder); 281 281 intel_display_power_get(dev_priv, power_domain); 282 282 283 283 mutex_lock(&dev_priv->pps_mutex); ··· 293 293 294 294 mutex_unlock(&dev_priv->pps_mutex); 295 295 296 - power_domain = intel_display_port_power_domain(encoder); 296 + power_domain = intel_display_port_aux_power_domain(encoder); 297 297 intel_display_power_put(dev_priv, power_domain); 298 298 } 299 299 ··· 816 816 817 817 intel_dp_check_edp(intel_dp); 818 818 819 - intel_aux_display_runtime_get(dev_priv); 820 - 821 819 /* Try to wait for any previous AUX channel activity */ 822 820 for (try = 0; try < 3; try++) { 823 821 status = I915_READ_NOTRACE(ch_ctl); ··· 924 926 ret = recv_bytes; 925 927 out: 926 928 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 927 - intel_aux_display_runtime_put(dev_priv); 928 929 929 930 if (vdd) 930 931 edp_panel_vdd_off(intel_dp, false); ··· 1781 1784 if (edp_have_panel_vdd(intel_dp)) 1782 1785 return need_to_disable; 1783 1786 1784 - power_domain = intel_display_port_power_domain(intel_encoder); 1787 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 1785 1788 intel_display_power_get(dev_priv, power_domain); 1786 1789 1787 1790 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", ··· 1871 1874 if ((pp & POWER_TARGET_ON) == 0) 1872 1875 intel_dp->last_power_cycle = jiffies; 1873 1876 1874 - power_domain = intel_display_port_power_domain(intel_encoder); 1877 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 1875 1878 intel_display_power_put(dev_priv, power_domain); 1876 1879 } 1877 1880 ··· 2022 2025 wait_panel_off(intel_dp); 2023 2026 2024 2027 /* We got a reference when we enabled the VDD. */ 2025 - power_domain = intel_display_port_power_domain(intel_encoder); 2028 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 2026 2029 intel_display_power_put(dev_priv, power_domain); 2027 2030 } 2028 2031 ··· 4762 4765 intel_dp->has_audio = false; 4763 4766 } 4764 4767 4765 - static enum intel_display_power_domain 4766 - intel_dp_power_get(struct intel_dp *dp) 4767 - { 4768 - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; 4769 - enum intel_display_power_domain power_domain; 4770 - 4771 - power_domain = intel_display_port_power_domain(encoder); 4772 - intel_display_power_get(to_i915(encoder->base.dev), power_domain); 4773 - 4774 - return power_domain; 4775 - } 4776 - 4777 - static void 4778 - intel_dp_power_put(struct intel_dp *dp, 4779 - enum intel_display_power_domain power_domain) 4780 - { 4781 - struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; 4782 - intel_display_power_put(to_i915(encoder->base.dev), power_domain); 4783 - } 4784 - 4785 4768 static enum drm_connector_status 4786 4769 intel_dp_detect(struct drm_connector *connector, bool force) 4787 4770 { ··· 4785 4808 return connector_status_disconnected; 4786 4809 } 4787 4810 4788 - power_domain = intel_dp_power_get(intel_dp); 4811 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 4812 + intel_display_power_get(to_i915(dev), power_domain); 4789 4813 4790 4814 /* Can't disconnect eDP, but you can close the lid... */ 4791 4815 if (is_edp(intel_dp)) ··· 4831 4853 } 4832 4854 4833 4855 out: 4834 - intel_dp_power_put(intel_dp, power_domain); 4856 + intel_display_power_put(to_i915(dev), power_domain); 4835 4857 return status; 4836 4858 } 4837 4859 ··· 4840 4862 { 4841 4863 struct intel_dp *intel_dp = intel_attached_dp(connector); 4842 4864 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 4865 + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4843 4866 enum intel_display_power_domain power_domain; 4844 4867 4845 4868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", ··· 4850 4871 if (connector->status != connector_status_connected) 4851 4872 return; 4852 4873 4853 - power_domain = intel_dp_power_get(intel_dp); 4874 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 4875 + intel_display_power_get(dev_priv, power_domain); 4854 4876 4855 4877 intel_dp_set_edid(intel_dp); 4856 4878 4857 - intel_dp_power_put(intel_dp, power_domain); 4879 + intel_display_power_put(dev_priv, power_domain); 4858 4880 4859 4881 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4860 4882 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; ··· 5071 5091 * indefinitely. 5072 5092 */ 5073 5093 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 5074 - power_domain = intel_display_port_power_domain(&intel_dig_port->base); 5094 + power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); 5075 5095 intel_display_power_get(dev_priv, power_domain); 5076 5096 5077 5097 edp_panel_vdd_schedule_off(intel_dp); ··· 5133 5153 enum intel_display_power_domain power_domain; 5134 5154 enum irqreturn ret = IRQ_NONE; 5135 5155 5136 - if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) 5156 + if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && 5157 + intel_dig_port->base.type != INTEL_OUTPUT_HDMI) 5137 5158 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 5138 5159 5139 5160 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { ··· 5153 5172 port_name(intel_dig_port->port), 5154 5173 long_hpd ? "long" : "short"); 5155 5174 5156 - power_domain = intel_display_port_power_domain(intel_encoder); 5175 + power_domain = intel_display_port_aux_power_domain(intel_encoder); 5157 5176 intel_display_power_get(dev_priv, power_domain); 5158 5177 5159 5178 if (long_hpd) {

+2 -2

drivers/gpu/drm/i915/intel_drv.h

··· 1169 1169 void hsw_disable_ips(struct intel_crtc *crtc); 1170 1170 enum intel_display_power_domain 1171 1171 intel_display_port_power_domain(struct intel_encoder *intel_encoder); 1172 + enum intel_display_power_domain 1173 + intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); 1172 1174 void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1173 1175 struct intel_crtc_state *pipe_config); 1174 1176 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); ··· 1379 1377 enum intel_display_power_domain domain); 1380 1378 void intel_display_power_put(struct drm_i915_private *dev_priv, 1381 1379 enum intel_display_power_domain domain); 1382 - void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 1383 - void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 1384 1380 void intel_runtime_pm_get(struct drm_i915_private *dev_priv); 1385 1381 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); 1386 1382 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);

+6 -6

drivers/gpu/drm/i915/intel_hdmi.c

··· 1335 1335 { 1336 1336 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1337 1337 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 1338 - struct intel_encoder *intel_encoder = 1339 - &hdmi_to_dig_port(intel_hdmi)->base; 1340 - enum intel_display_power_domain power_domain; 1341 1338 struct edid *edid = NULL; 1342 1339 bool connected = false; 1343 1340 1344 - power_domain = intel_display_port_power_domain(intel_encoder); 1345 - intel_display_power_get(dev_priv, power_domain); 1341 + intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1346 1342 1347 1343 if (force) 1348 1344 edid = drm_get_edid(connector, 1349 1345 intel_gmbus_get_adapter(dev_priv, 1350 1346 intel_hdmi->ddc_bus)); 1351 1347 1352 - intel_display_power_put(dev_priv, power_domain); 1348 + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1353 1349 1354 1350 to_intel_connector(connector)->detect_edid = edid; 1355 1351 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { ··· 1379 1383 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1380 1384 connector->base.id, connector->name); 1381 1385 1386 + intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 1387 + 1382 1388 while (!live_status && --retry) { 1383 1389 live_status = intel_digital_port_connected(dev_priv, 1384 1390 hdmi_to_dig_port(intel_hdmi)); ··· 1399 1401 status = connector_status_connected; 1400 1402 } else 1401 1403 status = connector_status_disconnected; 1404 + 1405 + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 1402 1406 1403 1407 return status; 1404 1408 }

+4 -2

drivers/gpu/drm/i915/intel_i2c.c

··· 483 483 int i = 0, inc, try = 0; 484 484 int ret = 0; 485 485 486 - intel_aux_display_runtime_get(dev_priv); 486 + intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 487 487 mutex_lock(&dev_priv->gmbus_mutex); 488 488 489 489 if (bus->force_bit) { ··· 595 595 596 596 out: 597 597 mutex_unlock(&dev_priv->gmbus_mutex); 598 - intel_aux_display_runtime_put(dev_priv); 598 + 599 + intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 600 + 599 601 return ret; 600 602 } 601 603

+4 -30

drivers/gpu/drm/i915/intel_runtime_pm.c

··· 362 362 BIT(POWER_DOMAIN_AUX_C) | \ 363 363 BIT(POWER_DOMAIN_AUDIO) | \ 364 364 BIT(POWER_DOMAIN_VGA) | \ 365 + BIT(POWER_DOMAIN_GMBUS) | \ 365 366 BIT(POWER_DOMAIN_INIT)) 366 367 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 367 368 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ ··· 1484 1483 BIT(POWER_DOMAIN_AUX_B) | \ 1485 1484 BIT(POWER_DOMAIN_AUX_C) | \ 1486 1485 BIT(POWER_DOMAIN_AUX_D) | \ 1486 + BIT(POWER_DOMAIN_GMBUS) | \ 1487 1487 BIT(POWER_DOMAIN_INIT)) 1488 1488 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1489 1489 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ ··· 1847 1845 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 1848 1846 i915.disable_power_well); 1849 1847 1848 + BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 1849 + 1850 1850 mutex_init(&power_domains->lock); 1851 1851 1852 1852 /* ··· 2065 2061 intel_display_set_init_power(dev_priv, true); 2066 2062 intel_power_domains_resume(dev_priv); 2067 2063 power_domains->initializing = false; 2068 - } 2069 - 2070 - /** 2071 - * intel_aux_display_runtime_get - grab an auxiliary power domain reference 2072 - * @dev_priv: i915 device instance 2073 - * 2074 - * This function grabs a power domain reference for the auxiliary power domain 2075 - * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its 2076 - * parents are powered up. Therefore users should only grab a reference to the 2077 - * innermost power domain they need. 2078 - * 2079 - * Any power domain reference obtained by this function must have a symmetric 2080 - * call to intel_aux_display_runtime_put() to release the reference again. 2081 - */ 2082 - void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 2083 - { 2084 - intel_runtime_pm_get(dev_priv); 2085 - } 2086 - 2087 - /** 2088 - * intel_aux_display_runtime_put - release an auxiliary power domain reference 2089 - * @dev_priv: i915 device instance 2090 - * 2091 - * This function drops the auxiliary power domain reference obtained by 2092 - * intel_aux_display_runtime_get() and might power down the corresponding 2093 - * hardware block right away if this is the last reference. 2094 - */ 2095 - void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 2096 - { 2097 - intel_runtime_pm_put(dev_priv); 2098 2064 } 2099 2065 2100 2066 /**

+3 -4

drivers/gpu/drm/imx/imx-drm-core.c

··· 63 63 #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) 64 64 struct imx_drm_device *imxdrm = drm->dev_private; 65 65 66 - if (imxdrm->fbhelper) 67 - drm_fbdev_cma_restore_mode(imxdrm->fbhelper); 66 + drm_fbdev_cma_restore_mode(imxdrm->fbhelper); 68 67 #endif 69 68 } 70 69 ··· 339 340 * imx_drm_add_crtc - add a new crtc 340 341 */ 341 342 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, 342 - struct imx_drm_crtc **new_crtc, 343 + struct imx_drm_crtc **new_crtc, struct drm_plane *primary_plane, 343 344 const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs, 344 345 struct device_node *port) 345 346 { ··· 378 379 drm_crtc_helper_add(crtc, 379 380 imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); 380 381 381 - drm_crtc_init(drm, crtc, 382 + drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 382 383 imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs); 383 384 384 385 return 0;

+2 -1

drivers/gpu/drm/imx/imx-drm.h

··· 9 9 struct drm_encoder; 10 10 struct drm_fbdev_cma; 11 11 struct drm_framebuffer; 12 + struct drm_plane; 12 13 struct imx_drm_crtc; 13 14 struct platform_device; 14 15 ··· 25 24 }; 26 25 27 26 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, 28 - struct imx_drm_crtc **new_crtc, 27 + struct imx_drm_crtc **new_crtc, struct drm_plane *primary_plane, 29 28 const struct imx_drm_crtc_helper_funcs *imx_helper_funcs, 30 29 struct device_node *port); 31 30 int imx_drm_remove_crtc(struct imx_drm_crtc *);

+1

drivers/gpu/drm/imx/imx-tve.c

··· 721 721 { .compatible = "fsl,imx53-tve", }, 722 722 { /* sentinel */ } 723 723 }; 724 + MODULE_DEVICE_TABLE(of, imx_tve_dt_ids); 724 725 725 726 static struct platform_driver imx_tve_driver = { 726 727 .probe = imx_tve_probe,

+17 -46

drivers/gpu/drm/imx/ipuv3-crtc.c

··· 212 212 213 213 spin_lock_irqsave(&drm->event_lock, flags); 214 214 if (ipu_crtc->page_flip_event) 215 - drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event); 215 + drm_crtc_send_vblank_event(&ipu_crtc->base, 216 + ipu_crtc->page_flip_event); 216 217 ipu_crtc->page_flip_event = NULL; 217 218 imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc); 218 219 spin_unlock_irqrestore(&drm->event_lock, flags); ··· 350 349 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); 351 350 int dp = -EINVAL; 352 351 int ret; 353 - int id; 354 352 355 353 ret = ipu_get_resources(ipu_crtc, pdata); 356 354 if (ret) { ··· 358 358 return ret; 359 359 } 360 360 361 + if (pdata->dp >= 0) 362 + dp = IPU_DP_FLOW_SYNC_BG; 363 + ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0, 364 + DRM_PLANE_TYPE_PRIMARY); 365 + if (IS_ERR(ipu_crtc->plane[0])) { 366 + ret = PTR_ERR(ipu_crtc->plane[0]); 367 + goto err_put_resources; 368 + } 369 + 361 370 ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc, 362 - &ipu_crtc_helper_funcs, ipu_crtc->dev->of_node); 371 + &ipu_crtc->plane[0]->base, &ipu_crtc_helper_funcs, 372 + ipu_crtc->dev->of_node); 363 373 if (ret) { 364 374 dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret); 365 375 goto err_put_resources; 366 376 } 367 377 368 - if (pdata->dp >= 0) 369 - dp = IPU_DP_FLOW_SYNC_BG; 370 - id = imx_drm_crtc_id(ipu_crtc->imx_crtc); 371 - ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu, 372 - pdata->dma[0], dp, BIT(id), true); 373 378 ret = ipu_plane_get_resources(ipu_crtc->plane[0]); 374 379 if (ret) { 375 380 dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n", ··· 384 379 385 380 /* If this crtc is using the DP, add an overlay plane */ 386 381 if (pdata->dp >= 0 && pdata->dma[1] > 0) { 387 - ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu, 388 - pdata->dma[1], 389 - IPU_DP_FLOW_SYNC_FG, 390 - BIT(id), false); 382 + ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1], 383 + IPU_DP_FLOW_SYNC_FG, 384 + drm_crtc_mask(&ipu_crtc->base), 385 + DRM_PLANE_TYPE_OVERLAY); 391 386 if (IS_ERR(ipu_crtc->plane[1])) 392 387 ipu_crtc->plane[1] = NULL; 393 388 } ··· 410 405 ipu_put_resources(ipu_crtc); 411 406 412 407 return ret; 413 - } 414 - 415 - static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent, 416 - int port_id) 417 - { 418 - struct device_node *port; 419 - int id, ret; 420 - 421 - port = of_get_child_by_name(parent, "port"); 422 - while (port) { 423 - ret = of_property_read_u32(port, "reg", &id); 424 - if (!ret && id == port_id) 425 - return port; 426 - 427 - do { 428 - port = of_get_next_child(parent, port); 429 - if (!port) 430 - return NULL; 431 - } while (of_node_cmp(port->name, "port")); 432 - } 433 - 434 - return NULL; 435 408 } 436 409 437 410 static int ipu_drm_bind(struct device *dev, struct device *master, void *data) ··· 453 470 static int ipu_drm_probe(struct platform_device *pdev) 454 471 { 455 472 struct device *dev = &pdev->dev; 456 - struct ipu_client_platformdata *pdata = dev->platform_data; 457 473 int ret; 458 474 459 475 if (!dev->platform_data) 460 476 return -EINVAL; 461 - 462 - if (!dev->of_node) { 463 - /* Associate crtc device with the corresponding DI port node */ 464 - dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node, 465 - pdata->di + 2); 466 - if (!dev->of_node) { 467 - dev_err(dev, "missing port@%d node in %s\n", 468 - pdata->di + 2, dev->parent->of_node->full_name); 469 - return -ENODEV; 470 - } 471 - } 472 477 473 478 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 474 479 if (ret)

+4 -5

drivers/gpu/drm/imx/ipuv3-plane.c

··· 381 381 382 382 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, 383 383 int dma, int dp, unsigned int possible_crtcs, 384 - bool priv) 384 + enum drm_plane_type type) 385 385 { 386 386 struct ipu_plane *ipu_plane; 387 387 int ret; ··· 399 399 ipu_plane->dma = dma; 400 400 ipu_plane->dp_flow = dp; 401 401 402 - ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs, 403 - &ipu_plane_funcs, ipu_plane_formats, 404 - ARRAY_SIZE(ipu_plane_formats), 405 - priv); 402 + ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs, 403 + &ipu_plane_funcs, ipu_plane_formats, 404 + ARRAY_SIZE(ipu_plane_formats), type); 406 405 if (ret) { 407 406 DRM_ERROR("failed to initialize plane\n"); 408 407 kfree(ipu_plane);

+1 -1

drivers/gpu/drm/imx/ipuv3-plane.h

··· 34 34 35 35 struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, 36 36 int dma, int dp, unsigned int possible_crtcs, 37 - bool priv); 37 + enum drm_plane_type type); 38 38 39 39 /* Init IDMAC, DMFC, DP */ 40 40 int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,

+4

drivers/gpu/drm/imx/parallel-display.c

··· 54 54 55 55 if (imxpd->panel && imxpd->panel->funcs && 56 56 imxpd->panel->funcs->get_modes) { 57 + struct drm_display_info *di = &connector->display_info; 58 + 57 59 num_modes = imxpd->panel->funcs->get_modes(imxpd->panel); 60 + if (!imxpd->bus_format && di->num_bus_formats) 61 + imxpd->bus_format = di->bus_formats[0]; 58 62 if (num_modes > 0) 59 63 return num_modes; 60 64 }

+11 -8

drivers/gpu/drm/nouveau/nouveau_display.c

··· 829 829 struct drm_device *dev = drm->dev; 830 830 struct nouveau_page_flip_state *s; 831 831 unsigned long flags; 832 - int crtcid = -1; 833 832 834 833 spin_lock_irqsave(&dev->event_lock, flags); 835 834 ··· 840 841 841 842 s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); 842 843 if (s->event) { 843 - /* Vblank timestamps/counts are only correct on >= NV-50 */ 844 - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) 845 - crtcid = s->crtc; 844 + if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { 845 + drm_arm_vblank_event(dev, s->crtc, s->event); 846 + } else { 847 + drm_send_vblank_event(dev, s->crtc, s->event); 846 848 847 - drm_send_vblank_event(dev, crtcid, s->event); 849 + /* Give up ownership of vblank for page-flipped crtc */ 850 + drm_vblank_put(dev, s->crtc); 851 + } 848 852 } 849 - 850 - /* Give up ownership of vblank for page-flipped crtc */ 851 - drm_vblank_put(dev, s->crtc); 853 + else { 854 + /* Give up ownership of vblank for page-flipped crtc */ 855 + drm_vblank_put(dev, s->crtc); 856 + } 852 857 853 858 list_del(&s->head); 854 859 if (ps)

+4 -1

drivers/gpu/drm/radeon/cik.c

··· 8472 8472 if (queue_dp) 8473 8473 schedule_work(&rdev->dp_work); 8474 8474 if (queue_hotplug) 8475 - schedule_work(&rdev->hotplug_work); 8475 + schedule_delayed_work(&rdev->hotplug_work, 0); 8476 8476 if (queue_reset) { 8477 8477 rdev->needs_reset = true; 8478 8478 wake_up_all(&rdev->fence_queue); ··· 9630 9630 (rdev->disp_priority == 2)) { 9631 9631 DRM_DEBUG_KMS("force priority to high\n"); 9632 9632 } 9633 + 9634 + /* Save number of lines the linebuffer leads before the scanout */ 9635 + radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 9633 9636 } 9634 9637 9635 9638 /* select wm A */

+4 -1

drivers/gpu/drm/radeon/evergreen.c

··· 2372 2372 c.full = dfixed_div(c, a); 2373 2373 priority_b_mark = dfixed_trunc(c); 2374 2374 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 2375 + 2376 + /* Save number of lines the linebuffer leads before the scanout */ 2377 + radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 2375 2378 } 2376 2379 2377 2380 /* select wm A */ ··· 5347 5344 if (queue_dp) 5348 5345 schedule_work(&rdev->dp_work); 5349 5346 if (queue_hotplug) 5350 - schedule_work(&rdev->hotplug_work); 5347 + schedule_delayed_work(&rdev->hotplug_work, 0); 5351 5348 if (queue_hdmi) 5352 5349 schedule_work(&rdev->audio_work); 5353 5350 if (queue_thermal && rdev->pm.dpm_enabled)

+11 -1

drivers/gpu/drm/radeon/r100.c

··· 806 806 status = r100_irq_ack(rdev); 807 807 } 808 808 if (queue_hotplug) 809 - schedule_work(&rdev->hotplug_work); 809 + schedule_delayed_work(&rdev->hotplug_work, 0); 810 810 if (rdev->msi_enabled) { 811 811 switch (rdev->family) { 812 812 case CHIP_RS400: ··· 3217 3217 uint32_t pixel_bytes1 = 0; 3218 3218 uint32_t pixel_bytes2 = 0; 3219 3219 3220 + /* Guess line buffer size to be 8192 pixels */ 3221 + u32 lb_size = 8192; 3222 + 3220 3223 if (!rdev->mode_info.mode_config_initialized) 3221 3224 return; 3222 3225 ··· 3634 3631 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3635 3632 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3636 3633 } 3634 + 3635 + /* Save number of lines the linebuffer leads before the scanout */ 3636 + if (mode1) 3637 + rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 3638 + 3639 + if (mode2) 3640 + rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 3637 3641 } 3638 3642 3639 3643 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)

+1 -1

drivers/gpu/drm/radeon/r600.c

··· 4276 4276 WREG32(IH_RB_RPTR, rptr); 4277 4277 } 4278 4278 if (queue_hotplug) 4279 - schedule_work(&rdev->hotplug_work); 4279 + schedule_delayed_work(&rdev->hotplug_work, 0); 4280 4280 if (queue_hdmi) 4281 4281 schedule_work(&rdev->audio_work); 4282 4282 if (queue_thermal && rdev->pm.dpm_enabled)

+1 -1

drivers/gpu/drm/radeon/radeon.h

··· 2414 2414 struct r600_ih ih; /* r6/700 interrupt ring */ 2415 2415 struct radeon_rlc rlc; 2416 2416 struct radeon_mec mec; 2417 - struct work_struct hotplug_work; 2417 + struct delayed_work hotplug_work; 2418 2418 struct work_struct dp_work; 2419 2419 struct work_struct audio_work; 2420 2420 int num_crtc; /* number of crtcs */

+3

drivers/gpu/drm/radeon/radeon_agp.c

··· 54 54 /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */ 55 55 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50, 56 56 PCI_VENDOR_ID_IBM, 0x0550, 1}, 57 + /* Intel 82855PM host bridge / RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] needs AGPMode 1 (Thinkpad T40p) */ 58 + { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, 59 + PCI_VENDOR_ID_IBM, 0x054d, 1}, 57 60 /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */ 58 61 { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57, 59 62 PCI_VENDOR_ID_IBM, 0x0530, 1},

+20 -1

drivers/gpu/drm/radeon/radeon_connectors.c

··· 1234 1234 if (r < 0) 1235 1235 return connector_status_disconnected; 1236 1236 1237 + if (radeon_connector->detected_hpd_without_ddc) { 1238 + force = true; 1239 + radeon_connector->detected_hpd_without_ddc = false; 1240 + } 1241 + 1237 1242 if (!force && radeon_check_hpd_status_unchanged(connector)) { 1238 1243 ret = connector->status; 1239 1244 goto exit; 1240 1245 } 1241 1246 1242 - if (radeon_connector->ddc_bus) 1247 + if (radeon_connector->ddc_bus) { 1243 1248 dret = radeon_ddc_probe(radeon_connector, false); 1249 + 1250 + /* Sometimes the pins required for the DDC probe on DVI 1251 + * connectors don't make contact at the same time that the ones 1252 + * for HPD do. If the DDC probe fails even though we had an HPD 1253 + * signal, try again later */ 1254 + if (!dret && !force && 1255 + connector->status != connector_status_connected) { 1256 + DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); 1257 + radeon_connector->detected_hpd_without_ddc = true; 1258 + schedule_delayed_work(&rdev->hotplug_work, 1259 + msecs_to_jiffies(1000)); 1260 + goto exit; 1261 + } 1262 + } 1244 1263 if (dret) { 1245 1264 radeon_connector->detected_by_load = false; 1246 1265 radeon_connector_free_edid(connector);

+79 -27

drivers/gpu/drm/radeon/radeon_display.c

··· 322 322 * to complete in this vblank? 323 323 */ 324 324 if (update_pending && 325 - (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0, 325 + (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, 326 + crtc_id, 327 + USE_REAL_VBLANKSTART, 326 328 &vpos, &hpos, NULL, NULL, 327 329 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && 328 330 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || ··· 403 401 struct drm_crtc *crtc = &radeon_crtc->base; 404 402 unsigned long flags; 405 403 int r; 404 + int vpos, hpos, stat, min_udelay; 405 + struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 406 406 407 407 down_read(&rdev->exclusive_lock); 408 408 if (work->fence) { ··· 440 436 441 437 /* set the proper interrupt */ 442 438 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); 439 + 440 + /* If this happens to execute within the "virtually extended" vblank 441 + * interval before the start of the real vblank interval then it needs 442 + * to delay programming the mmio flip until the real vblank is entered. 443 + * This prevents completing a flip too early due to the way we fudge 444 + * our vblank counter and vblank timestamps in order to work around the 445 + * problem that the hw fires vblank interrupts before actual start of 446 + * vblank (when line buffer refilling is done for a frame). It 447 + * complements the fudging logic in radeon_get_crtc_scanoutpos() for 448 + * timestamping and radeon_get_vblank_counter_kms() for vblank counts. 449 + * 450 + * In practice this won't execute very often unless on very fast 451 + * machines because the time window for this to happen is very small. 452 + */ 453 + for (;;) { 454 + /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 455 + * start in hpos, and to the "fudged earlier" vblank start in 456 + * vpos. 457 + */ 458 + stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id, 459 + GET_DISTANCE_TO_VBLANKSTART, 460 + &vpos, &hpos, NULL, NULL, 461 + &crtc->hwmode); 462 + 463 + if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 464 + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 465 + !(vpos >= 0 && hpos <= 0)) 466 + break; 467 + 468 + /* Sleep at least until estimated real start of hw vblank */ 469 + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 470 + min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 471 + usleep_range(min_udelay, 2 * min_udelay); 472 + spin_lock_irqsave(&crtc->dev->event_lock, flags); 473 + }; 443 474 444 475 /* do the flip (mmio) */ 445 476 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); ··· 1807 1768 * \param dev Device to query. 1808 1769 * \param crtc Crtc to query. 1809 1770 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1771 + * For driver internal use only also supports these flags: 1772 + * 1773 + * USE_REAL_VBLANKSTART to use the real start of vblank instead 1774 + * of a fudged earlier start of vblank. 1775 + * 1776 + * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1777 + * fudged earlier start of vblank in *vpos and the distance 1778 + * to true start of vblank in *hpos. 1779 + * 1810 1780 * \param *vpos Location where vertical scanout position should be stored. 1811 1781 * \param *hpos Location where horizontal scanout position should go. 1812 1782 * \param *stime Target location for timestamp taken immediately before ··· 1959 1911 vbl_end = 0; 1960 1912 } 1961 1913 1914 + /* Called from driver internal vblank counter query code? */ 1915 + if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1916 + /* Caller wants distance from real vbl_start in *hpos */ 1917 + *hpos = *vpos - vbl_start; 1918 + } 1919 + 1920 + /* Fudge vblank to start a few scanlines earlier to handle the 1921 + * problem that vblank irqs fire a few scanlines before start 1922 + * of vblank. Some driver internal callers need the true vblank 1923 + * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1924 + * 1925 + * The cause of the "early" vblank irq is that the irq is triggered 1926 + * by the line buffer logic when the line buffer read position enters 1927 + * the vblank, whereas our crtc scanout position naturally lags the 1928 + * line buffer read position. 1929 + */ 1930 + if (!(flags & USE_REAL_VBLANKSTART)) 1931 + vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1932 + 1962 1933 /* Test scanout position against vblank region. */ 1963 1934 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1964 1935 in_vbl = false; 1936 + 1937 + /* In vblank? */ 1938 + if (in_vbl) 1939 + ret |= DRM_SCANOUTPOS_IN_VBLANK; 1940 + 1941 + /* Called from driver internal vblank counter query code? */ 1942 + if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1943 + /* Caller wants distance from fudged earlier vbl_start */ 1944 + *vpos -= vbl_start; 1945 + return ret; 1946 + } 1965 1947 1966 1948 /* Check if inside vblank area and apply corrective offsets: 1967 1949 * vpos will then be >=0 in video scanout area, but negative ··· 2007 1929 2008 1930 /* Correct for shifted end of vbl at vbl_end. */ 2009 1931 *vpos = *vpos - vbl_end; 2010 - 2011 - /* In vblank? */ 2012 - if (in_vbl) 2013 - ret |= DRM_SCANOUTPOS_IN_VBLANK; 2014 - 2015 - /* Is vpos outside nominal vblank area, but less than 2016 - * 1/100 of a frame height away from start of vblank? 2017 - * If so, assume this isn't a massively delayed vblank 2018 - * interrupt, but a vblank interrupt that fired a few 2019 - * microseconds before true start of vblank. Compensate 2020 - * by adding a full frame duration to the final timestamp. 2021 - * Happens, e.g., on ATI R500, R600. 2022 - * 2023 - * We only do this if DRM_CALLED_FROM_VBLIRQ. 2024 - */ 2025 - if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { 2026 - vbl_start = mode->crtc_vdisplay; 2027 - vtotal = mode->crtc_vtotal; 2028 - 2029 - if (vbl_start - *vpos < vtotal / 100) { 2030 - *vpos -= vtotal; 2031 - 2032 - /* Signal this correction as "applied". */ 2033 - ret |= 0x8; 2034 - } 2035 - } 2036 1932 2037 1933 return ret; 2038 1934 }

+4 -4

drivers/gpu/drm/radeon/radeon_irq_kms.c

··· 74 74 static void radeon_hotplug_work_func(struct work_struct *work) 75 75 { 76 76 struct radeon_device *rdev = container_of(work, struct radeon_device, 77 - hotplug_work); 77 + hotplug_work.work); 78 78 struct drm_device *dev = rdev->ddev; 79 79 struct drm_mode_config *mode_config = &dev->mode_config; 80 80 struct drm_connector *connector; ··· 302 302 } 303 303 } 304 304 305 - INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); 305 + INIT_DELAYED_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); 306 306 INIT_WORK(&rdev->dp_work, radeon_dp_work_func); 307 307 INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi); 308 308 ··· 310 310 r = drm_irq_install(rdev->ddev, rdev->ddev->pdev->irq); 311 311 if (r) { 312 312 rdev->irq.installed = false; 313 - flush_work(&rdev->hotplug_work); 313 + flush_delayed_work(&rdev->hotplug_work); 314 314 return r; 315 315 } 316 316 ··· 333 333 rdev->irq.installed = false; 334 334 if (rdev->msi_enabled) 335 335 pci_disable_msi(rdev->pdev); 336 - flush_work(&rdev->hotplug_work); 336 + flush_delayed_work(&rdev->hotplug_work); 337 337 } 338 338 } 339 339

+49 -1

drivers/gpu/drm/radeon/radeon_kms.c

··· 755 755 */ 756 756 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 757 757 { 758 + int vpos, hpos, stat; 759 + u32 count; 758 760 struct radeon_device *rdev = dev->dev_private; 759 761 760 762 if (crtc < 0 || crtc >= rdev->num_crtc) { ··· 764 762 return -EINVAL; 765 763 } 766 764 767 - return radeon_get_vblank_counter(rdev, crtc); 765 + /* The hw increments its frame counter at start of vsync, not at start 766 + * of vblank, as is required by DRM core vblank counter handling. 767 + * Cook the hw count here to make it appear to the caller as if it 768 + * incremented at start of vblank. We measure distance to start of 769 + * vblank in vpos. vpos therefore will be >= 0 between start of vblank 770 + * and start of vsync, so vpos >= 0 means to bump the hw frame counter 771 + * result by 1 to give the proper appearance to caller. 772 + */ 773 + if (rdev->mode_info.crtcs[crtc]) { 774 + /* Repeat readout if needed to provide stable result if 775 + * we cross start of vsync during the queries. 776 + */ 777 + do { 778 + count = radeon_get_vblank_counter(rdev, crtc); 779 + /* Ask radeon_get_crtc_scanoutpos to return vpos as 780 + * distance to start of vblank, instead of regular 781 + * vertical scanout pos. 782 + */ 783 + stat = radeon_get_crtc_scanoutpos( 784 + dev, crtc, GET_DISTANCE_TO_VBLANKSTART, 785 + &vpos, &hpos, NULL, NULL, 786 + &rdev->mode_info.crtcs[crtc]->base.hwmode); 787 + } while (count != radeon_get_vblank_counter(rdev, crtc)); 788 + 789 + if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 790 + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 791 + DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 792 + } 793 + else { 794 + DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 795 + crtc, vpos); 796 + 797 + /* Bump counter if we are at >= leading edge of vblank, 798 + * but before vsync where vpos would turn negative and 799 + * the hw counter really increments. 800 + */ 801 + if (vpos >= 0) 802 + count++; 803 + } 804 + } 805 + else { 806 + /* Fallback to use value as is. */ 807 + count = radeon_get_vblank_counter(rdev, crtc); 808 + DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 809 + } 810 + 811 + return count; 768 812 } 769 813 770 814 /**

+5

drivers/gpu/drm/radeon/radeon_mode.h

··· 367 367 u32 line_time; 368 368 u32 wm_low; 369 369 u32 wm_high; 370 + u32 lb_vblank_lead_lines; 370 371 struct drm_display_mode hw_mode; 371 372 enum radeon_output_csc output_csc; 372 373 }; ··· 554 553 void *con_priv; 555 554 bool dac_load_detect; 556 555 bool detected_by_load; /* if the connection status was determined by load */ 556 + bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 557 557 uint16_t connector_object_id; 558 558 struct radeon_hpd hpd; 559 559 struct radeon_router router; ··· 688 686 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 689 687 }; 690 688 689 + /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 690 + #define USE_REAL_VBLANKSTART (1 << 30) 691 + #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 691 692 692 693 extern void 693 694 radeon_add_atom_connector(struct drm_device *dev,

+3 -1

drivers/gpu/drm/radeon/radeon_pm.c

··· 1756 1756 */ 1757 1757 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1758 1758 if (rdev->pm.active_crtcs & (1 << crtc)) { 1759 - vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, 1759 + vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1760 + crtc, 1761 + USE_REAL_VBLANKSTART, 1760 1762 &vpos, &hpos, NULL, NULL, 1761 1763 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1762 1764 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&

+1 -1

drivers/gpu/drm/radeon/rs600.c

··· 813 813 status = rs600_irq_ack(rdev); 814 814 } 815 815 if (queue_hotplug) 816 - schedule_work(&rdev->hotplug_work); 816 + schedule_delayed_work(&rdev->hotplug_work, 0); 817 817 if (queue_hdmi) 818 818 schedule_work(&rdev->audio_work); 819 819 if (rdev->msi_enabled) {

+10

drivers/gpu/drm/radeon/rs690.c

··· 207 207 { 208 208 u32 tmp; 209 209 210 + /* Guess line buffer size to be 8192 pixels */ 211 + u32 lb_size = 8192; 212 + 210 213 /* 211 214 * Line Buffer Setup 212 215 * There is a single line buffer shared by both display controllers. ··· 246 243 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 247 244 } 248 245 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 246 + 247 + /* Save number of lines the linebuffer leads before the scanout */ 248 + if (mode1) 249 + rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); 250 + 251 + if (mode2) 252 + rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); 249 253 } 250 254 251 255 struct rs690_watermark {

+4 -1

drivers/gpu/drm/radeon/si.c

··· 2376 2376 c.full = dfixed_div(c, a); 2377 2377 priority_b_mark = dfixed_trunc(c); 2378 2378 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 2379 + 2380 + /* Save number of lines the linebuffer leads before the scanout */ 2381 + radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 2379 2382 } 2380 2383 2381 2384 /* select wm A */ ··· 6851 6848 if (queue_dp) 6852 6849 schedule_work(&rdev->dp_work); 6853 6850 if (queue_hotplug) 6854 - schedule_work(&rdev->hotplug_work); 6851 + schedule_delayed_work(&rdev->hotplug_work, 0); 6855 6852 if (queue_thermal && rdev->pm.dpm_enabled) 6856 6853 schedule_work(&rdev->pm.dpm.thermal.work); 6857 6854 rdev->ih.rptr = rptr;

+1

drivers/gpu/drm/rockchip/rockchip_drm_gem.c

··· 67 67 * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). 68 68 */ 69 69 vma->vm_flags &= ~VM_PFNMAP; 70 + vma->vm_pgoff = 0; 70 71 71 72 ret = dma_mmap_attrs(drm->dev, vma, rk_obj->kvaddr, rk_obj->dma_addr, 72 73 obj->size, &rk_obj->dma_attrs);

+18 -25

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

··· 374 374 .data = &rk3288_vop }, 375 375 {}, 376 376 }; 377 + MODULE_DEVICE_TABLE(of, vop_driver_dt_match); 377 378 378 379 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v) 379 380 { ··· 960 959 val = (dest.y2 - dest.y1 - 1) << 16; 961 960 val |= (dest.x2 - dest.x1 - 1) & 0xffff; 962 961 VOP_WIN_SET(vop, win, dsp_info, val); 963 - val = (dsp_sty - 1) << 16; 964 - val |= (dsp_stx - 1) & 0xffff; 962 + val = dsp_sty << 16; 963 + val |= dsp_stx & 0xffff; 965 964 VOP_WIN_SET(vop, win, dsp_st, val); 966 965 VOP_WIN_SET(vop, win, rb_swap, rb_swap); 967 966 ··· 1290 1289 1291 1290 if (state->event) { 1292 1291 spin_lock_irqsave(&drm->event_lock, flags); 1293 - drm_send_vblank_event(drm, -1, state->event); 1292 + drm_crtc_send_vblank_event(crtc, state->event); 1294 1293 spin_unlock_irqrestore(&drm->event_lock, flags); 1295 1294 } 1296 1295 ··· 1576 1575 return PTR_ERR(vop->dclk); 1577 1576 } 1578 1577 1579 - ret = clk_prepare(vop->hclk); 1580 - if (ret < 0) { 1581 - dev_err(vop->dev, "failed to prepare hclk\n"); 1582 - return ret; 1583 - } 1584 - 1585 1578 ret = clk_prepare(vop->dclk); 1586 1579 if (ret < 0) { 1587 1580 dev_err(vop->dev, "failed to prepare dclk\n"); 1588 - goto err_unprepare_hclk; 1581 + return ret; 1589 1582 } 1590 1583 1591 - ret = clk_prepare(vop->aclk); 1584 + /* Enable both the hclk and aclk to setup the vop */ 1585 + ret = clk_prepare_enable(vop->hclk); 1592 1586 if (ret < 0) { 1593 - dev_err(vop->dev, "failed to prepare aclk\n"); 1587 + dev_err(vop->dev, "failed to prepare/enable hclk\n"); 1594 1588 goto err_unprepare_dclk; 1595 1589 } 1596 1590 1597 - /* 1598 - * enable hclk, so that we can config vop register. 1599 - */ 1600 - ret = clk_enable(vop->hclk); 1591 + ret = clk_prepare_enable(vop->aclk); 1601 1592 if (ret < 0) { 1602 - dev_err(vop->dev, "failed to prepare aclk\n"); 1603 - goto err_unprepare_aclk; 1593 + dev_err(vop->dev, "failed to prepare/enable aclk\n"); 1594 + goto err_disable_hclk; 1604 1595 } 1596 + 1605 1597 /* 1606 1598 * do hclk_reset, reset all vop registers. 1607 1599 */ ··· 1602 1608 if (IS_ERR(ahb_rst)) { 1603 1609 dev_err(vop->dev, "failed to get ahb reset\n"); 1604 1610 ret = PTR_ERR(ahb_rst); 1605 - goto err_disable_hclk; 1611 + goto err_disable_aclk; 1606 1612 } 1607 1613 reset_control_assert(ahb_rst); 1608 1614 usleep_range(10, 20); ··· 1628 1634 if (IS_ERR(vop->dclk_rst)) { 1629 1635 dev_err(vop->dev, "failed to get dclk reset\n"); 1630 1636 ret = PTR_ERR(vop->dclk_rst); 1631 - goto err_unprepare_aclk; 1637 + goto err_disable_aclk; 1632 1638 } 1633 1639 reset_control_assert(vop->dclk_rst); 1634 1640 usleep_range(10, 20); 1635 1641 reset_control_deassert(vop->dclk_rst); 1636 1642 1637 1643 clk_disable(vop->hclk); 1644 + clk_disable(vop->aclk); 1638 1645 1639 1646 vop->is_enabled = false; 1640 1647 1641 1648 return 0; 1642 1649 1650 + err_disable_aclk: 1651 + clk_disable_unprepare(vop->aclk); 1643 1652 err_disable_hclk: 1644 - clk_disable(vop->hclk); 1645 - err_unprepare_aclk: 1646 - clk_unprepare(vop->aclk); 1653 + clk_disable_unprepare(vop->hclk); 1647 1654 err_unprepare_dclk: 1648 1655 clk_unprepare(vop->dclk); 1649 - err_unprepare_hclk: 1650 - clk_unprepare(vop->hclk); 1651 1656 return ret; 1652 1657 } 1653 1658

+1 -1

drivers/gpu/drm/virtio/virtgpu_display.c

··· 412 412 .save = virtio_gpu_conn_save, 413 413 .restore = virtio_gpu_conn_restore, 414 414 .detect = virtio_gpu_conn_detect, 415 - .fill_modes = drm_helper_probe_single_connector_modes, 415 + .fill_modes = drm_helper_probe_single_connector_modes_nomerge, 416 416 .destroy = virtio_gpu_conn_destroy, 417 417 .reset = drm_atomic_helper_connector_reset, 418 418 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,

+37 -30

drivers/gpu/ipu-v3/ipu-common.c

··· 28 28 #include <linux/irqchip/chained_irq.h> 29 29 #include <linux/irqdomain.h> 30 30 #include <linux/of_device.h> 31 + #include <linux/of_graph.h> 31 32 32 33 #include <drm/drm_fourcc.h> 33 34 ··· 994 993 struct ipu_platform_reg { 995 994 struct ipu_client_platformdata pdata; 996 995 const char *name; 997 - int reg_offset; 998 996 }; 999 997 998 + /* These must be in the order of the corresponding device tree port nodes */ 1000 999 static const struct ipu_platform_reg client_reg[] = { 1001 1000 { 1001 + .pdata = { 1002 + .csi = 0, 1003 + .dma[0] = IPUV3_CHANNEL_CSI0, 1004 + .dma[1] = -EINVAL, 1005 + }, 1006 + .name = "imx-ipuv3-camera", 1007 + }, { 1008 + .pdata = { 1009 + .csi = 1, 1010 + .dma[0] = IPUV3_CHANNEL_CSI1, 1011 + .dma[1] = -EINVAL, 1012 + }, 1013 + .name = "imx-ipuv3-camera", 1014 + }, { 1002 1015 .pdata = { 1003 1016 .di = 0, 1004 1017 .dc = 5, ··· 1030 1015 .dma[1] = -EINVAL, 1031 1016 }, 1032 1017 .name = "imx-ipuv3-crtc", 1033 - }, { 1034 - .pdata = { 1035 - .csi = 0, 1036 - .dma[0] = IPUV3_CHANNEL_CSI0, 1037 - .dma[1] = -EINVAL, 1038 - }, 1039 - .reg_offset = IPU_CM_CSI0_REG_OFS, 1040 - .name = "imx-ipuv3-camera", 1041 - }, { 1042 - .pdata = { 1043 - .csi = 1, 1044 - .dma[0] = IPUV3_CHANNEL_CSI1, 1045 - .dma[1] = -EINVAL, 1046 - }, 1047 - .reg_offset = IPU_CM_CSI1_REG_OFS, 1048 - .name = "imx-ipuv3-camera", 1049 1018 }, 1050 1019 }; 1051 1020 ··· 1050 1051 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1051 1052 const struct ipu_platform_reg *reg = &client_reg[i]; 1052 1053 struct platform_device *pdev; 1053 - struct resource res; 1054 1054 1055 - if (reg->reg_offset) { 1056 - memset(&res, 0, sizeof(res)); 1057 - res.flags = IORESOURCE_MEM; 1058 - res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset; 1059 - res.end = res.start + PAGE_SIZE - 1; 1060 - pdev = platform_device_register_resndata(dev, reg->name, 1061 - id++, &res, 1, &reg->pdata, sizeof(reg->pdata)); 1062 - } else { 1063 - pdev = platform_device_register_data(dev, reg->name, 1064 - id++, &reg->pdata, sizeof(reg->pdata)); 1055 + pdev = platform_device_alloc(reg->name, id++); 1056 + if (!pdev) { 1057 + ret = -ENOMEM; 1058 + goto err_register; 1065 1059 } 1066 1060 1067 - if (IS_ERR(pdev)) { 1068 - ret = PTR_ERR(pdev); 1061 + pdev->dev.parent = dev; 1062 + 1063 + /* Associate subdevice with the corresponding port node */ 1064 + pdev->dev.of_node = of_graph_get_port_by_id(dev->of_node, i); 1065 + if (!pdev->dev.of_node) { 1066 + dev_err(dev, "missing port@%d node in %s\n", i, 1067 + dev->of_node->full_name); 1068 + ret = -ENODEV; 1069 + goto err_register; 1070 + } 1071 + 1072 + ret = platform_device_add_data(pdev, &reg->pdata, 1073 + sizeof(reg->pdata)); 1074 + if (!ret) 1075 + ret = platform_device_add(pdev); 1076 + if (ret) { 1077 + platform_device_put(pdev); 1069 1078 goto err_register; 1070 1079 } 1071 1080 }

+10

include/drm/drmP.h

··· 309 309 unsigned universal_planes:1; 310 310 /* true if client understands atomic properties */ 311 311 unsigned atomic:1; 312 + /* 313 + * This client is allowed to gain master privileges for @master. 314 + * Protected by struct drm_device::master_mutex. 315 + */ 316 + unsigned allowed_master:1; 312 317 313 318 struct pid *pid; 314 319 kuid_t uid; ··· 915 910 extern ssize_t drm_read(struct file *filp, char __user *buffer, 916 911 size_t count, loff_t *offset); 917 912 extern int drm_release(struct inode *inode, struct file *filp); 913 + extern int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv); 918 914 919 915 /* Mapping support (drm_vm.h) */ 920 916 extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); ··· 953 947 struct drm_pending_vblank_event *e); 954 948 extern void drm_crtc_send_vblank_event(struct drm_crtc *crtc, 955 949 struct drm_pending_vblank_event *e); 950 + extern void drm_arm_vblank_event(struct drm_device *dev, unsigned int pipe, 951 + struct drm_pending_vblank_event *e); 952 + extern void drm_crtc_arm_vblank_event(struct drm_crtc *crtc, 953 + struct drm_pending_vblank_event *e); 956 954 extern bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe); 957 955 extern bool drm_crtc_handle_vblank(struct drm_crtc *crtc); 958 956 extern int drm_vblank_get(struct drm_device *dev, unsigned int pipe);

-1

include/video/imx-ipu-v3.h

··· 343 343 int di; 344 344 int dc; 345 345 int dp; 346 - int dmfc; 347 346 int dma[2]; 348 347 }; 349 348

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