Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/psr: further conversions to struct intel_display
intel_psr.c still uses the old platform identification macros. Convert
them and some other stragglers to struct intel_display.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/7d032bd621a56536b4d53c5c415cad624e5dc628.1742906146.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+30
-55
+30
-55
drivers/gpu/drm/i915/display/intel_psr.c
+30
-55
drivers/gpu/drm/i915/display/intel_psr.c
···
464
464
if (DISPLAY_VER(display) >= 9) {
465
465
u32 val;
466
466
467
-
val = intel_de_rmw(dev_priv,
468
-
PSR_EVENT(dev_priv, cpu_transcoder),
467
+
val = intel_de_rmw(display,
468
+
PSR_EVENT(display, cpu_transcoder),
469
469
0, 0);
470
470
471
471
psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
···
690
690
static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
691
691
{
692
692
struct intel_display *display = to_intel_display(intel_dp);
693
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
694
693
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
695
694
u32 aux_clock_divider, aux_ctl;
696
695
/* write DP_SET_POWER=D0 */
···
704
705
705
706
BUILD_BUG_ON(sizeof(aux_msg) > 20);
706
707
for (i = 0; i < sizeof(aux_msg); i += 4)
707
-
intel_de_write(dev_priv,
708
+
intel_de_write(display,
708
709
psr_aux_data_reg(display, cpu_transcoder, i >> 2),
709
710
intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i));
710
711
···
839
840
{
840
841
struct intel_display *display = to_intel_display(intel_dp);
841
842
struct intel_connector *connector = intel_dp->attached_connector;
842
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
843
843
u32 val = 0;
844
844
845
845
if (DISPLAY_VER(display) >= 11)
···
872
874
* WA 0479: hsw,bdw
873
875
* "Do not skip both TP1 and TP2/TP3"
874
876
*/
875
-
if (DISPLAY_VER(dev_priv) < 9 &&
877
+
if (DISPLAY_VER(display) < 9 &&
876
878
connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
877
879
connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
878
880
val |= EDP_PSR_TP2_TP3_TIME_100us;
···
908
910
static void hsw_activate_psr1(struct intel_dp *intel_dp)
909
911
{
910
912
struct intel_display *display = to_intel_display(intel_dp);
911
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
912
913
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
913
914
u32 max_sleep_time = 0x1f;
914
915
u32 val = EDP_PSR_ENABLE;
···
917
920
if (DISPLAY_VER(display) < 20)
918
921
val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
919
922
920
-
if (IS_HASWELL(dev_priv))
923
+
if (display->platform.haswell)
921
924
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
922
925
923
926
if (intel_dp->psr.link_standby)
···
1011
1014
static void hsw_activate_psr2(struct intel_dp *intel_dp)
1012
1015
{
1013
1016
struct intel_display *display = to_intel_display(intel_dp);
1014
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1015
1017
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1016
1018
u32 val = EDP_PSR2_ENABLE;
1017
1019
u32 psr_val = 0;
1018
1020
1019
1021
val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
1020
1022
1021
-
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
1023
+
if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)
1022
1024
val |= EDP_SU_TRACK_ENABLE;
1023
1025
1024
1026
if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)
···
1035
1039
}
1036
1040
1037
1041
/* Wa_22012278275:adl-p */
1038
-
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {
1042
+
if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {
1039
1043
static const u8 map[] = {
1040
1044
2, /* 5 lines */
1041
1045
1, /* 6 lines */
···
1100
1104
static bool
1101
1105
transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)
1102
1106
{
1103
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1104
-
1105
-
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)
1107
+
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1106
1108
return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B;
1107
1109
else if (DISPLAY_VER(display) >= 12)
1108
1110
return cpu_transcoder == TRANSCODER_A;
···
1178
1184
struct intel_display *display = to_intel_display(intel_dp);
1179
1185
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1180
1186
enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1181
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1182
1187
enum port port = dig_port->base.port;
1183
1188
1184
-
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)
1189
+
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1185
1190
return pipe <= PIPE_B && port <= PORT_B;
1186
1191
else
1187
1192
return pipe == PIPE_A && port == PORT_A;
···
1191
1198
struct intel_crtc_state *crtc_state)
1192
1199
{
1193
1200
struct intel_display *display = to_intel_display(intel_dp);
1194
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1195
1201
const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
1196
1202
struct i915_power_domains *power_domains = &display->power.domains;
1197
1203
u32 exit_scanlines;
···
1216
1224
return;
1217
1225
1218
1226
/* Wa_16011303918:adl-p */
1219
-
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
1227
+
if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
1220
1228
return;
1221
1229
1222
1230
/*
···
1257
1265
struct intel_crtc_state *crtc_state)
1258
1266
{
1259
1267
struct intel_display *display = to_intel_display(intel_dp);
1260
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1261
1268
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1262
1269
const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
1263
1270
const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
···
1278
1287
* For other platforms with SW tracking we can adjust the y coordinates
1279
1288
* to match sink requirement if multiple of 4.
1280
1289
*/
1281
-
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14)
1290
+
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1282
1291
y_granularity = intel_dp->psr.su_y_granularity;
1283
1292
else if (intel_dp->psr.su_y_granularity <= 2)
1284
1293
y_granularity = 4;
···
1404
1413
struct intel_crtc_state *crtc_state)
1405
1414
{
1406
1415
struct intel_display *display = to_intel_display(intel_dp);
1407
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1408
1416
int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
1409
1417
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1410
1418
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
···
1412
1422
return false;
1413
1423
1414
1424
/* JSL and EHL only supports eDP 1.3 */
1415
-
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
1425
+
if (display->platform.jasperlake || display->platform.elkhartlake) {
1416
1426
drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");
1417
1427
return false;
1418
1428
}
1419
1429
1420
1430
/* Wa_16011181250 */
1421
-
if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
1422
-
IS_DG2(dev_priv)) {
1431
+
if (display->platform.rocketlake || display->platform.alderlake_s ||
1432
+
display->platform.dg2) {
1423
1433
drm_dbg_kms(display->drm,
1424
1434
"PSR2 is defeatured for this platform\n");
1425
1435
return false;
1426
1436
}
1427
1437
1428
-
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1438
+
if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1429
1439
drm_dbg_kms(display->drm,
1430
1440
"PSR2 not completely functional in this stepping\n");
1431
1441
return false;
···
1444
1454
* over PSR2.
1445
1455
*/
1446
1456
if (crtc_state->dsc.compression_enable &&
1447
-
(DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))) {
1457
+
(DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) {
1448
1458
drm_dbg_kms(display->drm,
1449
1459
"PSR2 cannot be enabled since DSC is enabled\n");
1450
1460
return false;
···
1477
1487
1478
1488
/* Wa_16011303918:adl-p */
1479
1489
if (crtc_state->vrr.enable &&
1480
-
IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1490
+
display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1481
1491
drm_dbg_kms(display->drm,
1482
1492
"PSR2 not enabled, not compatible with HW stepping + VRR\n");
1483
1493
return false;
···
1818
1828
const struct intel_crtc_state *crtc_state)
1819
1829
{
1820
1830
struct intel_display *display = to_intel_display(intel_dp);
1821
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
1822
1831
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1823
1832
u32 mask = 0;
1824
1833
···
1856
1867
* As a workaround leave LPSP unmasked to prevent PSR entry
1857
1868
* when external displays are active.
1858
1869
*/
1859
-
if (DISPLAY_VER(display) >= 8 || IS_HASWELL_ULT(dev_priv))
1870
+
if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult)
1860
1871
mask |= EDP_PSR_DEBUG_MASK_LPSP;
1861
1872
1862
1873
if (DISPLAY_VER(display) < 20)
···
1870
1881
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1871
1882
1872
1883
/* allow PSR with sprite enabled */
1873
-
if (IS_HASWELL(dev_priv))
1884
+
if (display->platform.haswell)
1874
1885
mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE;
1875
1886
}
1876
1887
···
1915
1926
*/
1916
1927
if (!intel_dp->psr.panel_replay_enabled &&
1917
1928
(IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
1918
-
IS_ALDERLAKE_P(dev_priv)))
1929
+
display->platform.alderlake_p))
1919
1930
intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
1920
1931
0, ADLP_1_BASED_X_GRANULARITY);
1921
1932
···
1926
1937
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
1927
1938
0,
1928
1939
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
1929
-
else if (IS_ALDERLAKE_P(dev_priv))
1940
+
else if (display->platform.alderlake_p)
1930
1941
intel_de_rmw(display, CLKGATE_DIS_MISC, 0,
1931
1942
CLKGATE_DIS_MISC_DMASC_GATING_DIS);
1932
1943
}
···
2094
2105
static void intel_psr_disable_locked(struct intel_dp *intel_dp)
2095
2106
{
2096
2107
struct intel_display *display = to_intel_display(intel_dp);
2097
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
2098
2108
enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2099
2109
2100
2110
lockdep_assert_held(&intel_dp->psr.lock);
···
2125
2137
intel_de_rmw(display,
2126
2138
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
2127
2139
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
2128
-
else if (IS_ALDERLAKE_P(dev_priv))
2140
+
else if (display->platform.alderlake_p)
2129
2141
intel_de_rmw(display, CLKGATE_DIS_MISC,
2130
2142
CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
2131
2143
}
···
2303
2315
2304
2316
static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
2305
2317
{
2306
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
2307
-
2308
-
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ? 0 :
2318
+
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 :
2309
2319
PSR2_MAN_TRK_CTL_ENABLE;
2310
2320
}
2311
2321
2312
2322
static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)
2313
2323
{
2314
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
2315
-
2316
-
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?
2324
+
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2317
2325
ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
2318
2326
PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
2319
2327
}
2320
2328
2321
2329
static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)
2322
2330
{
2323
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
2324
-
2325
-
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?
2331
+
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2326
2332
ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
2327
2333
PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
2328
2334
}
2329
2335
2330
2336
static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)
2331
2337
{
2332
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
2333
-
2334
-
return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14 ?
2338
+
return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2335
2339
ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
2336
2340
PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
2337
2341
}
···
2386
2406
bool full_update)
2387
2407
{
2388
2408
struct intel_display *display = to_intel_display(crtc_state);
2389
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2390
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2391
2409
u32 val = man_trk_ctl_enable_bit_get(display);
2392
2410
2393
2411
/* SF partial frame enable has to be set even on full update */
···
2399
2421
if (crtc_state->psr2_su_area.y1 == -1)
2400
2422
goto exit;
2401
2423
2402
-
if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) {
2424
+
if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) {
2403
2425
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);
2404
2426
val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);
2405
2427
} else {
···
2453
2475
static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
2454
2476
{
2455
2477
struct intel_display *display = to_intel_display(crtc_state);
2456
-
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2457
2478
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2458
2479
u16 y_alignment;
2459
2480
2460
2481
/* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
2461
2482
if (crtc_state->dsc.compression_enable &&
2462
-
(IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14))
2483
+
(display->platform.alderlake_p || DISPLAY_VER(display) >= 14))
2463
2484
y_alignment = vdsc_cfg->slice_height;
2464
2485
else
2465
2486
y_alignment = crtc_state->su_y_granularity;
···
2579
2602
intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
2580
2603
{
2581
2604
struct intel_display *display = to_intel_display(crtc_state);
2582
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2583
2605
2584
2606
/* Wa_14014971492 */
2585
2607
if (!crtc_state->has_panel_replay &&
2586
2608
((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
2587
-
IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) &&
2609
+
display->platform.alderlake_p || display->platform.tigerlake)) &&
2588
2610
crtc_state->splitter.enable)
2589
2611
crtc_state->psr2_su_area.y1 = 0;
2590
2612
···
2784
2808
struct intel_crtc *crtc)
2785
2809
{
2786
2810
struct intel_display *display = to_intel_display(state);
2787
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2788
2811
const struct intel_crtc_state *old_crtc_state =
2789
2812
intel_atomic_get_old_crtc_state(state, crtc);
2790
2813
const struct intel_crtc_state *new_crtc_state =
···
2815
2840
new_crtc_state->has_sel_update != psr->sel_update_enabled ||
2816
2841
new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||
2817
2842
new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||
2818
-
(DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled))
2843
+
(DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled))
2819
2844
intel_psr_disable_locked(intel_dp);
2820
2845
else if (new_crtc_state->wm_level_disabled)
2821
2846
/* Wa_14015648006 */