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drm/msm/a5xx: workaround early ring-buffer emptiness check

There is another cause for soft lock-up of GPU in empty ring-buffer:
race between GPU executing last commands and CPU checking ring for
emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS
event and RPTR shadow (which is used to check ring emptiness) is updated
a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its
last commands slow enough or we check that ring too fast we will miss a
chance to trigger switch to lower priority ring because current ring isn't
empty just yet. This can escalate to lock-up situation described in
previous patch.
To work-around this issue we keep track of last submit sequence number
for each ring and compare it with one written to memptrs from GPU during
execution of CACHE_FLUSH_TS event.

Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612047/
Signed-off-by: Rob Clark <robdclark@chromium.org>

authored by

Vladimir Lypak and committed by
Rob Clark a30f9f65 ce050f30

+9
+4
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
··· 65 65 66 66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) 67 67 { 68 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 69 + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); 68 70 struct msm_ringbuffer *ring = submit->ring; 69 71 struct drm_gem_object *obj; 70 72 uint32_t *ptr, dwords; ··· 111 109 } 112 110 } 113 111 112 + a5xx_gpu->last_seqno[ring->id] = submit->seqno; 114 113 a5xx_flush(gpu, ring, true); 115 114 a5xx_preempt_trigger(gpu); 116 115 ··· 213 210 /* Write the fence to the scratch register */ 214 211 OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1); 215 212 OUT_RING(ring, submit->seqno); 213 + a5xx_gpu->last_seqno[ring->id] = submit->seqno; 216 214 217 215 /* 218 216 * Execute a CACHE_FLUSH_TS event. This will ensure that the
+1
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
··· 34 34 struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS]; 35 35 struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS]; 36 36 uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; 37 + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; 37 38 38 39 atomic_t preempt_state; 39 40 spinlock_t preempt_start_lock;
+4
drivers/gpu/drm/msm/adreno/a5xx_preempt.c
··· 55 55 /* Return the highest priority ringbuffer with something in it */ 56 56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) 57 57 { 58 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 59 + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); 58 60 unsigned long flags; 59 61 int i; 60 62 ··· 66 64 67 65 spin_lock_irqsave(&ring->preempt_lock, flags); 68 66 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); 67 + if (!empty && ring == a5xx_gpu->cur_ring) 68 + empty = ring->memptrs->fence == a5xx_gpu->last_seqno[i]; 69 69 spin_unlock_irqrestore(&ring->preempt_lock, flags); 70 70 71 71 if (!empty)