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drm/xe: Implement recent spec updates to Wa_16025250150

The hardware teams noticed that the originally documented workaround
steps for Wa_16025250150 may not be sufficient to fully avoid a hardware
issue. The workaround documentation has been augmented to suggest
programming one additional register; make the corresponding change in
the driver.

Fixes: 7654d51f1fd8 ("drm/xe/xe2hpg: Add Wa_16025250150")
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20260319-wa_16025250150_part2-v1-1-46b1de1a31b2@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Matt Roper a3156676 e8c3a913

+3 -1
+1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
··· 578 578 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 579 579 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 580 580 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 581 + #define L3_128B_256B_WRT_DIS REG_BIT(40 - 32) 581 582 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 582 583 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 583 584 #define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32)
+2 -1
drivers/gpu/drm/xe/xe_wa.c
··· 260 260 LSN_DIM_Z_WGT_MASK, 261 261 LSN_LNI_WGT(1) | LSN_LNE_WGT(1) | 262 262 LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) | 263 - LSN_DIM_Z_WGT(1))) 263 + LSN_DIM_Z_WGT(1)), 264 + SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS)) 264 265 }, 265 266 266 267 /* Xe3_LPG */