···8383 spinlock_t lock;8484 int irq;8585 bool cs_flag;8686+ bool abort_failed;8687};87888889static int get_spi_clk_cfg(unsigned int speed_hz,···142141 spin_unlock_irq(&mas->lock);143142144143 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);145145- if (!time_left)144144+ if (!time_left) {146145 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");146146+147147+ /*148148+ * No need for a lock since SPI core has a lock and we never149149+ * access this from an interrupt.150150+ */151151+ mas->abort_failed = true;152152+ }153153+}154154+155155+static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)156156+{157157+ struct geni_se *se = &mas->se;158158+ u32 m_irq, m_irq_en;159159+160160+ if (!mas->abort_failed)161161+ return false;162162+163163+ /*164164+ * The only known case where a transfer times out and then a cancel165165+ * times out then an abort times out is if something is blocking our166166+ * interrupt handler from running. Avoid starting any new transfers167167+ * until that sorts itself out.168168+ */169169+ spin_lock_irq(&mas->lock);170170+ m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);171171+ m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);172172+ spin_unlock_irq(&mas->lock);173173+174174+ if (m_irq & m_irq_en) {175175+ dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",176176+ m_irq & m_irq_en);177177+ return true;178178+ }179179+180180+ /*181181+ * If we're here the problem resolved itself so no need to check more182182+ * on future transfers.183183+ */184184+ mas->abort_failed = false;185185+186186+ return false;147187}148188149189static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)···200158 if (set_flag == mas->cs_flag)201159 return;202160203203- mas->cs_flag = set_flag;204204-205161 pm_runtime_get_sync(mas->dev);162162+163163+ if (spi_geni_is_abort_still_pending(mas)) {164164+ dev_err(mas->dev, "Can't set chip select\n");165165+ goto exit;166166+ }167167+206168 spin_lock_irq(&mas->lock);169169+ if (mas->cur_xfer) {170170+ dev_err(mas->dev, "Can't set CS when prev xfer running\n");171171+ spin_unlock_irq(&mas->lock);172172+ goto exit;173173+ }174174+175175+ mas->cs_flag = set_flag;207176 reinit_completion(&mas->cs_done);208177 if (set_flag)209178 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);···223170 spin_unlock_irq(&mas->lock);224171225172 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);226226- if (!time_left)173173+ if (!time_left) {174174+ dev_warn(mas->dev, "Timeout setting chip select\n");227175 handle_fifo_timeout(spi, NULL);176176+ }228177178178+exit:229179 pm_runtime_put(mas->dev);230180}231181···336280 int ret;337281 struct spi_geni_master *mas = spi_master_get_devdata(spi);338282283283+ if (spi_geni_is_abort_still_pending(mas))284284+ return -EBUSY;285285+339286 ret = setup_fifo_params(spi_msg->spi, spi);340287 if (ret)341288 dev_err(mas->dev, "Couldn't select mode %d\n", ret);···413354 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);414355 unsigned int i = 0;415356357357+ /* Stop the watermark IRQ if nothing to send */358358+ if (!mas->cur_xfer) {359359+ writel(0, se->base + SE_GENI_TX_WATERMARK_REG);360360+ return false;361361+ }362362+416363 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;417364 if (mas->tx_rem_bytes < max_bytes)418365 max_bytes = mas->tx_rem_bytes;···461396 if (rx_last_byte_valid && rx_last_byte_valid < 4)462397 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;463398 }399399+400400+ /* Clear out the FIFO and bail if nowhere to put it */401401+ if (!mas->cur_xfer) {402402+ for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)403403+ readl(se->base + SE_GENI_RX_FIFOn);404404+ return;405405+ }406406+464407 if (mas->rx_rem_bytes < rx_bytes)465408 rx_bytes = mas->rx_rem_bytes;466409···567494 struct spi_transfer *xfer)568495{569496 struct spi_geni_master *mas = spi_master_get_devdata(spi);497497+498498+ if (spi_geni_is_abort_still_pending(mas))499499+ return -EBUSY;570500571501 /* Terminate and return success for 0 byte length transfer */572502 if (!xfer->len)