Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A few more fixes for clk drivers causing regressions this release.
Two Allwinner index fixes for A31 and V3 and two Microchip AT91 fixes
for an incorrect clk parent linkage and a miscalculated number of
clks"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: at91: fix masterck name
clk: at91: fix at91sam9x5 peripheral clock number
clk: sunxi: A31: Fix wrong AHB gate number
clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
+8
-9
+2
-3
drivers/clk/at91/at91sam9x5.c
+2
-3
drivers/clk/at91/at91sam9x5.c
···
144
144
return;
145
145
146
146
at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
147
-
nck(at91sam9x5_systemck),
148
-
nck(at91sam9x35_periphck), 0);
147
+
nck(at91sam9x5_systemck), 31, 0);
149
148
if (!at91sam9x5_pmc)
150
149
return;
151
150
···
209
210
parent_names[1] = "mainck";
210
211
parent_names[2] = "plladivck";
211
212
parent_names[3] = "utmick";
212
-
parent_names[4] = "mck";
213
+
parent_names[4] = "masterck";
213
214
for (i = 0; i < 2; i++) {
214
215
char name[6];
215
216
+2
-2
drivers/clk/at91/sama5d2.c
+2
-2
drivers/clk/at91/sama5d2.c
···
240
240
parent_names[1] = "mainck";
241
241
parent_names[2] = "plladivck";
242
242
parent_names[3] = "utmick";
243
-
parent_names[4] = "mck";
243
+
parent_names[4] = "masterck";
244
244
for (i = 0; i < 3; i++) {
245
245
char name[6];
246
246
···
291
291
parent_names[1] = "mainck";
292
292
parent_names[2] = "plladivck";
293
293
parent_names[3] = "utmick";
294
-
parent_names[4] = "mck";
294
+
parent_names[4] = "masterck";
295
295
parent_names[5] = "audiopll_pmcck";
296
296
for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
297
297
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+1
-1
drivers/clk/at91/sama5d4.c
+1
-1
drivers/clk/at91/sama5d4.c
+2
-2
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+2
-2
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
···
264
264
static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
265
265
0x060, BIT(10), 0);
266
266
static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
267
-
0x060, BIT(12), 0);
267
+
0x060, BIT(11), 0);
268
268
static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
269
-
0x060, BIT(13), 0);
269
+
0x060, BIT(12), 0);
270
270
static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
271
271
0x060, BIT(13), 0);
272
272
static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
+1
-1
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+1
-1
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
···
542
542
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
543
543
544
544
[RST_BUS_VE] = { 0x2c4, BIT(0) },
545
-
[RST_BUS_TCON0] = { 0x2c4, BIT(3) },
545
+
[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
546
546
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
547
547
[RST_BUS_DE] = { 0x2c4, BIT(12) },
548
548
[RST_BUS_DBG] = { 0x2c4, BIT(31) },