Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Regular fixes pull, some amdkfd, amdgpu, etnaviv, sun4i, qxl, tegra
fixes.
I've got an outstanding pull for i915 but it wasn't on an rc2 base so
I wanted to ship these out first, I might get to it before rc3 or I
might not"
* tag 'drm-fixes-for-v4.14-rc3' of git://people.freedesktop.org/~airlied/linux:
drm/tegra: trace: Fix path to include
qxl: fix framebuffer unpinning
drm/sun4i: cec: Enable back CEC-pin framework
drm/amdkfd: Print event limit messages only once per process
drm/amdkfd: Fix kernel-queue wrapping bugs
drm/amdkfd: Fix incorrect destroy_mqd parameter
drm/radeon: disable hard reset in hibernate for APUs
drm/amdgpu: revert tile table update for oland
etnaviv: fix gem object list corruption
etnaviv: fix submit error path
qxl: fix primary surface handling
drm/amdkfd: check for null dev to avoid a null pointer dereference
+246
-31
+188
-1
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+188
-1
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
···
636
636
NUM_BANKS(ADDR_SURF_2_BANK);
637
637
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
638
638
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
639
-
} else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) {
639
+
} else if (adev->asic_type == CHIP_OLAND) {
640
+
tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
641
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
643
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
644
+
NUM_BANKS(ADDR_SURF_16_BANK) |
645
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
646
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
647
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
648
+
tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
649
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
650
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
651
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
652
+
NUM_BANKS(ADDR_SURF_16_BANK) |
653
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
654
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
655
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
656
+
tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
657
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
658
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
659
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
660
+
NUM_BANKS(ADDR_SURF_16_BANK) |
661
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
662
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
663
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
664
+
tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
665
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
666
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
667
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
668
+
NUM_BANKS(ADDR_SURF_16_BANK) |
669
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
670
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
671
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
672
+
tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
673
+
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
674
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
675
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
676
+
NUM_BANKS(ADDR_SURF_16_BANK) |
677
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
678
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
679
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
680
+
tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
681
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
682
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
683
+
TILE_SPLIT(split_equal_to_row_size) |
684
+
NUM_BANKS(ADDR_SURF_16_BANK) |
685
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
686
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
687
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
688
+
tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
689
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
690
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
691
+
TILE_SPLIT(split_equal_to_row_size) |
692
+
NUM_BANKS(ADDR_SURF_16_BANK) |
693
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
694
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
695
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
696
+
tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
697
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
698
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
699
+
TILE_SPLIT(split_equal_to_row_size) |
700
+
NUM_BANKS(ADDR_SURF_16_BANK) |
701
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
702
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
703
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
704
+
tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
705
+
ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
706
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
707
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
708
+
NUM_BANKS(ADDR_SURF_16_BANK) |
709
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
710
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
711
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
712
+
tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
713
+
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
714
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
715
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
716
+
NUM_BANKS(ADDR_SURF_16_BANK) |
717
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
718
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
719
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
720
+
tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
721
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
722
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
723
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
724
+
NUM_BANKS(ADDR_SURF_16_BANK) |
725
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
726
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
727
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
728
+
tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
729
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
730
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
731
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
732
+
NUM_BANKS(ADDR_SURF_16_BANK) |
733
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
734
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
735
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
736
+
tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
737
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
738
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
739
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
740
+
NUM_BANKS(ADDR_SURF_16_BANK) |
741
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
742
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
743
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
744
+
tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
745
+
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
746
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
747
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
748
+
NUM_BANKS(ADDR_SURF_16_BANK) |
749
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
750
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
751
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
752
+
tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
753
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
754
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
755
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
756
+
NUM_BANKS(ADDR_SURF_16_BANK) |
757
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
758
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
759
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
760
+
tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
761
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
762
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
763
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
764
+
NUM_BANKS(ADDR_SURF_16_BANK) |
765
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
766
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
767
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
768
+
tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
769
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
770
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
771
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
772
+
NUM_BANKS(ADDR_SURF_16_BANK) |
773
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
774
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
775
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
776
+
tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
778
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
779
+
TILE_SPLIT(split_equal_to_row_size) |
780
+
NUM_BANKS(ADDR_SURF_16_BANK) |
781
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
782
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
783
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
784
+
tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
785
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
786
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
787
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
788
+
NUM_BANKS(ADDR_SURF_16_BANK) |
789
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
790
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
791
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
792
+
tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
793
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
794
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
795
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
796
+
NUM_BANKS(ADDR_SURF_16_BANK) |
797
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
798
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
799
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
800
+
tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804
+
NUM_BANKS(ADDR_SURF_16_BANK) |
805
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
807
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
808
+
tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
809
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
810
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
812
+
NUM_BANKS(ADDR_SURF_16_BANK) |
813
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
815
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
816
+
tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817
+
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
818
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
819
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
820
+
NUM_BANKS(ADDR_SURF_8_BANK) |
821
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
822
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
823
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
824
+
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
825
+
WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
826
+
} else if (adev->asic_type == CHIP_HAINAN) {
640
827
tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
641
828
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
642
829
PIPE_CONFIG(ADDR_SURF_P2) |
+2
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+2
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+4
-1
drivers/gpu/drm/amd/amdkfd/kfd_events.c
+4
-1
drivers/gpu/drm/amd/amdkfd/kfd_events.c
···
292
292
struct kfd_event *ev)
293
293
{
294
294
if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) {
295
-
pr_warn("Signal event wasn't created because limit was reached\n");
295
+
if (!p->signal_event_limit_reached) {
296
+
pr_warn("Signal event wasn't created because limit was reached\n");
297
+
p->signal_event_limit_reached = true;
298
+
}
296
299
return -ENOMEM;
297
300
}
298
301
+16
-4
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+16
-4
drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
···
184
184
if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ)
185
185
kq->mqd->destroy_mqd(kq->mqd,
186
186
kq->queue->mqd,
187
-
false,
187
+
KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
188
188
QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS,
189
189
kq->queue->pipe,
190
190
kq->queue->queue);
···
210
210
uint32_t wptr, rptr;
211
211
unsigned int *queue_address;
212
212
213
+
/* When rptr == wptr, the buffer is empty.
214
+
* When rptr == wptr + 1, the buffer is full.
215
+
* It is always rptr that advances to the position of wptr, rather than
216
+
* the opposite. So we can only use up to queue_size_dwords - 1 dwords.
217
+
*/
213
218
rptr = *kq->rptr_kernel;
214
219
wptr = *kq->wptr_kernel;
215
220
queue_address = (unsigned int *)kq->pq_kernel_addr;
···
224
219
pr_debug("wptr: %d\n", wptr);
225
220
pr_debug("queue_address 0x%p\n", queue_address);
226
221
227
-
available_size = (rptr - 1 - wptr + queue_size_dwords) %
222
+
available_size = (rptr + queue_size_dwords - 1 - wptr) %
228
223
queue_size_dwords;
229
224
230
-
if (packet_size_in_dwords >= queue_size_dwords ||
231
-
packet_size_in_dwords >= available_size) {
225
+
if (packet_size_in_dwords > available_size) {
232
226
/*
233
227
* make sure calling functions know
234
228
* acquire_packet_buffer() failed
···
237
233
}
238
234
239
235
if (wptr + packet_size_in_dwords >= queue_size_dwords) {
236
+
/* make sure after rolling back to position 0, there is
237
+
* still enough space.
238
+
*/
239
+
if (packet_size_in_dwords >= rptr) {
240
+
*buffer_ptr = NULL;
241
+
return -ENOMEM;
242
+
}
243
+
/* fill nops, roll back and start at position 0 */
240
244
while (wptr > 0) {
241
245
queue_address[wptr] = kq->nop_packet;
242
246
wptr = (wptr + 1) % queue_size_dwords;
+1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+24
-19
drivers/gpu/drm/qxl/qxl_display.c
+24
-19
drivers/gpu/drm/qxl/qxl_display.c
···
509
509
.y2 = qfb->base.height
510
510
};
511
511
512
-
if (!old_state->fb) {
513
-
qxl_io_log(qdev,
514
-
"create primary fb: %dx%d,%d,%d\n",
515
-
bo->surf.width, bo->surf.height,
516
-
bo->surf.stride, bo->surf.format);
517
-
518
-
qxl_io_create_primary(qdev, 0, bo);
519
-
bo->is_primary = true;
520
-
return;
521
-
522
-
} else {
512
+
if (old_state->fb) {
523
513
qfb_old = to_qxl_framebuffer(old_state->fb);
524
514
bo_old = gem_to_qxl_bo(qfb_old->obj);
515
+
} else {
516
+
bo_old = NULL;
517
+
}
518
+
519
+
if (bo == bo_old)
520
+
return;
521
+
522
+
if (bo_old && bo_old->is_primary) {
523
+
qxl_io_destroy_primary(qdev);
525
524
bo_old->is_primary = false;
526
525
}
527
526
528
-
bo->is_primary = true;
527
+
if (!bo->is_primary) {
528
+
qxl_io_create_primary(qdev, 0, bo);
529
+
bo->is_primary = true;
530
+
}
529
531
qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1);
530
532
}
531
533
···
536
534
{
537
535
struct qxl_device *qdev = plane->dev->dev_private;
538
536
539
-
if (old_state->fb)
540
-
{ struct qxl_framebuffer *qfb =
537
+
if (old_state->fb) {
538
+
struct qxl_framebuffer *qfb =
541
539
to_qxl_framebuffer(old_state->fb);
542
540
struct qxl_bo *bo = gem_to_qxl_bo(qfb->obj);
543
541
544
-
qxl_io_destroy_primary(qdev);
545
-
bo->is_primary = false;
542
+
if (bo->is_primary) {
543
+
qxl_io_destroy_primary(qdev);
544
+
bo->is_primary = false;
545
+
}
546
546
}
547
547
}
548
548
···
702
698
struct drm_gem_object *obj;
703
699
struct qxl_bo *user_bo;
704
700
705
-
if (!plane->state->fb) {
706
-
/* we never executed prepare_fb, so there's nothing to
701
+
if (!old_state->fb) {
702
+
/*
703
+
* we never executed prepare_fb, so there's nothing to
707
704
* unpin.
708
705
*/
709
706
return;
710
707
}
711
708
712
-
obj = to_qxl_framebuffer(plane->state->fb)->obj;
709
+
obj = to_qxl_framebuffer(old_state->fb)->obj;
713
710
user_bo = gem_to_qxl_bo(obj);
714
711
qxl_bo_unpin(user_bo);
715
712
}
+1
-1
drivers/gpu/drm/radeon/radeon_device.c
+1
-1
drivers/gpu/drm/radeon/radeon_device.c
···
1663
1663
radeon_agp_suspend(rdev);
1664
1664
1665
1665
pci_save_state(dev->pdev);
1666
-
if (freeze && rdev->family >= CHIP_CEDAR) {
1666
+
if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1667
1667
rdev->asic->asic_reset(rdev, true);
1668
1668
pci_restore_state(dev->pdev);
1669
1669
} else if (suspend) {
+1
-1
drivers/gpu/drm/sun4i/Kconfig
+1
-1
drivers/gpu/drm/sun4i/Kconfig
+1
-1
drivers/gpu/drm/sun4i/sun4i_hdmi.h
+1
-1
drivers/gpu/drm/sun4i/sun4i_hdmi.h