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drm/panel: sitronix-st7789v: Clarify a definition

The Sitronix datasheet explains BIT(1) of the RGBCTRL register as the
DOTCLK/PCLK edge used to sample the data lines:

“0” The data is input on the positive edge of DOTCLK
“1” The data is input on the negative edge of DOTCLK

IOW, this bit implies a falling edge and not a high state. Correct the
definition to ease the comparison with the datasheet.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Sebastian Reichel <sre@kernel.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230714013756.1546769-18-sre@kernel.org

authored by

Miquel Raynal and committed by
Neil Armstrong a368b408 6b00e72e

+2 -2
+2 -2
drivers/gpu/drm/panel/panel-sitronix-st7789v.c
··· 27 27 #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) 28 28 #define ST7789V_RGBCTRL_VSYNC_HIGH BIT(3) 29 29 #define ST7789V_RGBCTRL_HSYNC_HIGH BIT(2) 30 - #define ST7789V_RGBCTRL_PCLK_HIGH BIT(1) 30 + #define ST7789V_RGBCTRL_PCLK_FALLING BIT(1) 31 31 #define ST7789V_RGBCTRL_DE_LOW BIT(0) 32 32 #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) 33 33 #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) ··· 259 259 if (ctx->info->mode->flags & DRM_MODE_FLAG_PHSYNC) 260 260 polarity |= ST7789V_RGBCTRL_HSYNC_HIGH; 261 261 if (ctx->info->bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE) 262 - polarity |= ST7789V_RGBCTRL_PCLK_HIGH; 262 + polarity |= ST7789V_RGBCTRL_PCLK_FALLING; 263 263 if (ctx->info->bus_flags & DRM_BUS_FLAG_DE_LOW) 264 264 polarity |= ST7789V_RGBCTRL_DE_LOW; 265 265