Merge branch 'parisc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc fixes from Helge Deller:
"Three important fixes for the parisc architecture.

Dave provided two patches: One which purges the TLB before setting a
PTE entry and a second one which drops unnecessary TLB flushes. Both
patches have been tested for one week on the debian buildd servers and
prevent random segmentation faults.

The patch from me fixes a crash at boot inside the TLB measuring code
on SMP machines with PA8000-PA8700 CPUs (specifically A500-44 and
J5000 servers)"

* 'parisc-4.9-5' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Fix TLB related boot crash on SMP machines
parisc: Remove unnecessary TLB purges from flush_dcache_page_asm and flush_icache_page_asm
parisc: Purge TLB before setting PTE

Linus Torvalds 9 years ago a37102dc b4aafe77

+16 -25

3 changed files

expand all

arch

parisc

include

asm

pgtable.h

kernel

cache.c

pacache.S

+4 -4

arch/parisc/include/asm/pgtable.h

··· 65 65 unsigned long flags; \ 66 66 spin_lock_irqsave(&pa_tlb_lock, flags); \ 67 67 old_pte = *ptep; \ 68 - set_pte(ptep, pteval); \ 69 68 if (pte_inserted(old_pte)) \ 70 69 purge_tlb_entries(mm, addr); \ 70 + set_pte(ptep, pteval); \ 71 71 spin_unlock_irqrestore(&pa_tlb_lock, flags); \ 72 72 } while (0) 73 73 ··· 478 478 spin_unlock_irqrestore(&pa_tlb_lock, flags); 479 479 return 0; 480 480 } 481 - set_pte(ptep, pte_mkold(pte)); 482 481 purge_tlb_entries(vma->vm_mm, addr); 482 + set_pte(ptep, pte_mkold(pte)); 483 483 spin_unlock_irqrestore(&pa_tlb_lock, flags); 484 484 return 1; 485 485 } ··· 492 492 493 493 spin_lock_irqsave(&pa_tlb_lock, flags); 494 494 old_pte = *ptep; 495 - set_pte(ptep, __pte(0)); 496 495 if (pte_inserted(old_pte)) 497 496 purge_tlb_entries(mm, addr); 497 + set_pte(ptep, __pte(0)); 498 498 spin_unlock_irqrestore(&pa_tlb_lock, flags); 499 499 500 500 return old_pte; ··· 504 504 { 505 505 unsigned long flags; 506 506 spin_lock_irqsave(&pa_tlb_lock, flags); 507 - set_pte(ptep, pte_wrprotect(*ptep)); 508 507 purge_tlb_entries(mm, addr); 508 + set_pte(ptep, pte_wrprotect(*ptep)); 509 509 spin_unlock_irqrestore(&pa_tlb_lock, flags); 510 510 } 511 511

+11

arch/parisc/kernel/cache.c

··· 393 393 394 394 /* calculate TLB flush threshold */ 395 395 396 + /* On SMP machines, skip the TLB measure of kernel text which 397 + * has been mapped as huge pages. */ 398 + if (num_online_cpus() > 1 && !parisc_requires_coherency()) { 399 + threshold = max(cache_info.it_size, cache_info.dt_size); 400 + threshold *= PAGE_SIZE; 401 + threshold /= num_online_cpus(); 402 + goto set_tlb_threshold; 403 + } 404 + 396 405 alltime = mfctl(16); 397 406 flush_tlb_all(); 398 407 alltime = mfctl(16) - alltime; ··· 420 411 alltime, size, rangetime); 421 412 422 413 threshold = PAGE_ALIGN(num_online_cpus() * size * alltime / rangetime); 414 + 415 + set_tlb_threshold: 423 416 if (threshold) 424 417 parisc_tlb_flush_threshold = threshold; 425 418 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",

+1 -21

arch/parisc/kernel/pacache.S

··· 892 892 fdc,m r31(%r28) 893 893 fdc,m r31(%r28) 894 894 fdc,m r31(%r28) 895 - cmpb,COND(<<) %r28, %r25,1b 895 + cmpb,COND(<<) %r28, %r25,1b 896 896 fdc,m r31(%r28) 897 897 898 898 sync 899 - 900 - #ifdef CONFIG_PA20 901 - pdtlb,l %r0(%r25) 902 - #else 903 - tlb_lock %r20,%r21,%r22 904 - pdtlb %r0(%r25) 905 - tlb_unlock %r20,%r21,%r22 906 - #endif 907 - 908 899 bv %r0(%r2) 909 900 nop 910 901 .exit ··· 970 979 fic,m %r31(%sr4,%r28) 971 980 972 981 sync 973 - 974 - #ifdef CONFIG_PA20 975 - pdtlb,l %r0(%r28) 976 - pitlb,l %r0(%sr4,%r25) 977 - #else 978 - tlb_lock %r20,%r21,%r22 979 - pdtlb %r0(%r28) 980 - pitlb %r0(%sr4,%r25) 981 - tlb_unlock %r20,%r21,%r22 982 - #endif 983 - 984 982 bv %r0(%r2) 985 983 nop 986 984 .exit

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