Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2018-09-21' of git://anongit.freedesktop.org/drm/drm
David writes:
"drm fixes for 4.19-rc5:
- core: fix debugfs for atomic, fix the check for atomic for
non-modesetting drivers
- amdgpu: adds a new PCI id, some kfd fixes and a sdma fix
- i915: a bunch of GVT fixes.
- vc4: scaling fix
- vmwgfx: modesetting fixes and a old buffer eviction fix
- udl: framebuffer destruction fix
- sun4i: disable on R40 fix until next kernel
- pl111: NULL termination on table fix"
* tag 'drm-fixes-2018-09-21' of git://anongit.freedesktop.org/drm/drm: (21 commits)
drm/amdkfd: Fix ATS capablity was not reported correctly on some APUs
drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9
drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7
drm/vmwgfx: Fix buffer object eviction
drm/vmwgfx: Don't impose STDU limits on framebuffer size
drm/vmwgfx: limit mode size for all display unit to texture_max
drm/vmwgfx: limit screen size to stdu_max during check_modeset
drm/vmwgfx: don't check for old_crtc_state enable status
drm/amdgpu: add new polaris pci id
drm: sun4i: drop second PLL from A64 HDMI PHY
drm: fix drm_drv_uses_atomic_modeset on non modesetting drivers.
drm/i915/gvt: clear ggtt entries when destroy vgpu
drm/i915/gvt: request srcu_read_lock before checking if one gfn is valid
drm/i915/gvt: Add GEN9_CLKGATE_DIS_4 to default BXT mmio handler
drm/i915/gvt: Init PHY related registers for BXT
drm/atomic: Use drm_drv_uses_atomic_modeset() for debugfs creation
drm/fb-helper: Remove set but not used variable 'connector_funcs'
drm: udl: Destroy framebuffer only if it was initialized
drm/sun4i: Remove R40 display pipeline compatibles
drm/pl111: Make sure of_device_id tables are NULL terminated
...
+152
-117
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
···
272
272
273
273
int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
274
274
void **mem_obj, uint64_t *gpu_addr,
275
-
void **cpu_ptr)
275
+
void **cpu_ptr, bool mqd_gfx9)
276
276
{
277
277
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
278
278
struct amdgpu_bo *bo = NULL;
···
287
287
bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
288
288
bp.type = ttm_bo_type_kernel;
289
289
bp.resv = NULL;
290
+
291
+
if (mqd_gfx9)
292
+
bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
293
+
290
294
r = amdgpu_bo_create(adev, &bp, &bo);
291
295
if (r) {
292
296
dev_err(adev->dev,
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
···
136
136
/* Shared API */
137
137
int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
138
138
void **mem_obj, uint64_t *gpu_addr,
139
-
void **cpu_ptr);
139
+
void **cpu_ptr, bool mqd_gfx9);
140
140
void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
141
141
void get_local_mem_info(struct kgd_dev *kgd,
142
142
struct kfd_local_mem_info *mem_info);
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+8
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+8
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
···
367
367
break;
368
368
case CHIP_POLARIS10:
369
369
if (type == CGS_UCODE_ID_SMU) {
370
-
if ((adev->pdev->device == 0x67df) &&
371
-
((adev->pdev->revision == 0xe0) ||
372
-
(adev->pdev->revision == 0xe3) ||
373
-
(adev->pdev->revision == 0xe4) ||
374
-
(adev->pdev->revision == 0xe5) ||
375
-
(adev->pdev->revision == 0xe7) ||
370
+
if (((adev->pdev->device == 0x67df) &&
371
+
((adev->pdev->revision == 0xe0) ||
372
+
(adev->pdev->revision == 0xe3) ||
373
+
(adev->pdev->revision == 0xe4) ||
374
+
(adev->pdev->revision == 0xe5) ||
375
+
(adev->pdev->revision == 0xe7) ||
376
+
(adev->pdev->revision == 0xef))) ||
377
+
((adev->pdev->device == 0x6fdf) &&
376
378
(adev->pdev->revision == 0xef))) {
377
379
info->is_kicker = true;
378
380
strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
740
740
{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
741
741
{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
742
742
{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
743
+
{0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
743
744
/* Polaris12 */
744
745
{0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
745
746
{0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
+2
-1
drivers/gpu/drm/amd/amdkfd/kfd_device.c
+2
-1
drivers/gpu/drm/amd/amdkfd/kfd_device.c
···
457
457
458
458
if (kfd->kfd2kgd->init_gtt_mem_allocation(
459
459
kfd->kgd, size, &kfd->gtt_mem,
460
-
&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){
460
+
&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
461
+
false)) {
461
462
dev_err(kfd_device, "Could not allocate %d bytes\n", size);
462
463
goto out;
463
464
}
+12
-1
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+12
-1
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
···
62
62
struct amd_iommu_device_info iommu_info;
63
63
unsigned int pasid_limit;
64
64
int err;
65
+
struct kfd_topology_device *top_dev;
65
66
66
-
if (!kfd->device_info->needs_iommu_device)
67
+
top_dev = kfd_topology_device_by_id(kfd->id);
68
+
69
+
/*
70
+
* Overwrite ATS capability according to needs_iommu_device to fix
71
+
* potential missing corresponding bit in CRAT of BIOS.
72
+
*/
73
+
if (!kfd->device_info->needs_iommu_device) {
74
+
top_dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;
67
75
return 0;
76
+
}
77
+
78
+
top_dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
68
79
69
80
iommu_info.flags = 0;
70
81
err = amd_iommu_device_info(kfd->pdev, &iommu_info);
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
···
88
88
ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
89
89
&((*mqd_mem_obj)->gtt_mem),
90
90
&((*mqd_mem_obj)->gpu_addr),
91
-
(void *)&((*mqd_mem_obj)->cpu_ptr));
91
+
(void *)&((*mqd_mem_obj)->cpu_ptr), true);
92
92
} else
93
93
retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
94
94
mqd_mem_obj);
+1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
···
806
806
int kfd_topology_remove_device(struct kfd_dev *gpu);
807
807
struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
808
808
uint32_t proximity_domain);
809
+
struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
809
810
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id);
810
811
struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev);
811
812
int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev);
+16
-5
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+16
-5
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
···
63
63
return device;
64
64
}
65
65
66
-
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id)
66
+
struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)
67
67
{
68
-
struct kfd_topology_device *top_dev;
69
-
struct kfd_dev *device = NULL;
68
+
struct kfd_topology_device *top_dev = NULL;
69
+
struct kfd_topology_device *ret = NULL;
70
70
71
71
down_read(&topology_lock);
72
72
73
73
list_for_each_entry(top_dev, &topology_device_list, list)
74
74
if (top_dev->gpu_id == gpu_id) {
75
-
device = top_dev->gpu;
75
+
ret = top_dev;
76
76
break;
77
77
}
78
78
79
79
up_read(&topology_lock);
80
80
81
-
return device;
81
+
return ret;
82
+
}
83
+
84
+
struct kfd_dev *kfd_device_by_id(uint32_t gpu_id)
85
+
{
86
+
struct kfd_topology_device *top_dev;
87
+
88
+
top_dev = kfd_topology_device_by_id(gpu_id);
89
+
if (!top_dev)
90
+
return NULL;
91
+
92
+
return top_dev->gpu;
82
93
}
83
94
84
95
struct kfd_dev *kfd_device_by_pci_dev(const struct pci_dev *pdev)
+1
-1
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+1
-1
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+1
-1
drivers/gpu/drm/drm_atomic.c
+1
-1
drivers/gpu/drm/drm_atomic.c
···
2067
2067
struct drm_connector *connector;
2068
2068
struct drm_connector_list_iter conn_iter;
2069
2069
2070
-
if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
2070
+
if (!drm_drv_uses_atomic_modeset(dev))
2071
2071
return;
2072
2072
2073
2073
list_for_each_entry(plane, &config->plane_list, head) {
+1
-1
drivers/gpu/drm/drm_debugfs.c
+1
-1
drivers/gpu/drm/drm_debugfs.c
-3
drivers/gpu/drm/drm_fb_helper.c
-3
drivers/gpu/drm/drm_fb_helper.c
···
2370
2370
{
2371
2371
int c, o;
2372
2372
struct drm_connector *connector;
2373
-
const struct drm_connector_helper_funcs *connector_funcs;
2374
2373
int my_score, best_score, score;
2375
2374
struct drm_fb_helper_crtc **crtcs, *crtc;
2376
2375
struct drm_fb_helper_connector *fb_helper_conn;
···
2397
2398
my_score++;
2398
2399
if (drm_has_preferred_mode(fb_helper_conn, width, height))
2399
2400
my_score++;
2400
-
2401
-
connector_funcs = connector->helper_private;
2402
2401
2403
2402
/*
2404
2403
* select a crtc for this connector and then attempt to configure
+1
drivers/gpu/drm/i915/gvt/handlers.c
+1
drivers/gpu/drm/i915/gvt/handlers.c
+6
-1
drivers/gpu/drm/i915/gvt/kvmgt.c
+6
-1
drivers/gpu/drm/i915/gvt/kvmgt.c
···
1833
1833
{
1834
1834
struct kvmgt_guest_info *info;
1835
1835
struct kvm *kvm;
1836
+
int idx;
1837
+
bool ret;
1836
1838
1837
1839
if (!handle_valid(handle))
1838
1840
return false;
···
1842
1840
info = (struct kvmgt_guest_info *)handle;
1843
1841
kvm = info->kvm;
1844
1842
1845
-
return kvm_is_visible_gfn(kvm, gfn);
1843
+
idx = srcu_read_lock(&kvm->srcu);
1844
+
ret = kvm_is_visible_gfn(kvm, gfn);
1845
+
srcu_read_unlock(&kvm->srcu, idx);
1846
1846
1847
+
return ret;
1847
1848
}
1848
1849
1849
1850
struct intel_gvt_mpt kvmgt_mpt = {
+28
drivers/gpu/drm/i915/gvt/mmio.c
+28
drivers/gpu/drm/i915/gvt/mmio.c
···
244
244
245
245
/* set the bit 0:2(Core C-State ) to C0 */
246
246
vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
247
+
248
+
if (IS_BROXTON(vgpu->gvt->dev_priv)) {
249
+
vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
250
+
~(BIT(0) | BIT(1));
251
+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
252
+
~PHY_POWER_GOOD;
253
+
vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
254
+
~PHY_POWER_GOOD;
255
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
256
+
~BIT(30);
257
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
258
+
~BIT(30);
259
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
260
+
~BXT_PHY_LANE_ENABLED;
261
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
262
+
BXT_PHY_CMNLANE_POWERDOWN_ACK |
263
+
BXT_PHY_LANE_POWERDOWN_ACK;
264
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
265
+
~BXT_PHY_LANE_ENABLED;
266
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
267
+
BXT_PHY_CMNLANE_POWERDOWN_ACK |
268
+
BXT_PHY_LANE_POWERDOWN_ACK;
269
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
270
+
~BXT_PHY_LANE_ENABLED;
271
+
vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
272
+
BXT_PHY_CMNLANE_POWERDOWN_ACK |
273
+
BXT_PHY_LANE_POWERDOWN_ACK;
274
+
}
247
275
} else {
248
276
#define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
249
277
/* only reset the engine related, so starting with 0x44200
+1
drivers/gpu/drm/i915/gvt/vgpu.c
+1
drivers/gpu/drm/i915/gvt/vgpu.c
+2
-1
drivers/gpu/drm/pl111/pl111_vexpress.c
+2
-1
drivers/gpu/drm/pl111/pl111_vexpress.c
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
···
418
418
{ .compatible = "allwinner,sun8i-a33-display-engine" },
419
419
{ .compatible = "allwinner,sun8i-a83t-display-engine" },
420
420
{ .compatible = "allwinner,sun8i-h3-display-engine" },
421
-
{ .compatible = "allwinner,sun8i-r40-display-engine" },
422
421
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
423
422
{ .compatible = "allwinner,sun9i-a80-display-engine" },
424
423
{ }
-1
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-1
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-24
drivers/gpu/drm/sun4i/sun8i_mixer.c
-24
drivers/gpu/drm/sun4i/sun8i_mixer.c
···
545
545
.vi_num = 1,
546
546
};
547
547
548
-
static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
549
-
.ccsc = 0,
550
-
.mod_rate = 297000000,
551
-
.scaler_mask = 0xf,
552
-
.ui_num = 3,
553
-
.vi_num = 1,
554
-
};
555
-
556
-
static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
557
-
.ccsc = 1,
558
-
.mod_rate = 297000000,
559
-
.scaler_mask = 0x3,
560
-
.ui_num = 1,
561
-
.vi_num = 1,
562
-
};
563
-
564
548
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
565
549
.vi_num = 2,
566
550
.ui_num = 1,
···
565
581
{
566
582
.compatible = "allwinner,sun8i-h3-de2-mixer-0",
567
583
.data = &sun8i_h3_mixer0_cfg,
568
-
},
569
-
{
570
-
.compatible = "allwinner,sun8i-r40-de2-mixer-0",
571
-
.data = &sun8i_r40_mixer0_cfg,
572
-
},
573
-
{
574
-
.compatible = "allwinner,sun8i-r40-de2-mixer-1",
575
-
.data = &sun8i_r40_mixer1_cfg,
576
584
},
577
585
{
578
586
.compatible = "allwinner,sun8i-v3s-de2-mixer",
-1
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
-1
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
···
253
253
254
254
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
255
255
const struct of_device_id sun8i_tcon_top_of_table[] = {
256
-
{ .compatible = "allwinner,sun8i-r40-tcon-top" },
257
256
{ /* sentinel */ }
258
257
};
259
258
MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
+5
-3
drivers/gpu/drm/udl/udl_fb.c
+5
-3
drivers/gpu/drm/udl/udl_fb.c
···
432
432
{
433
433
drm_fb_helper_unregister_fbi(&ufbdev->helper);
434
434
drm_fb_helper_fini(&ufbdev->helper);
435
-
drm_framebuffer_unregister_private(&ufbdev->ufb.base);
436
-
drm_framebuffer_cleanup(&ufbdev->ufb.base);
437
-
drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base);
435
+
if (ufbdev->ufb.obj) {
436
+
drm_framebuffer_unregister_private(&ufbdev->ufb.base);
437
+
drm_framebuffer_cleanup(&ufbdev->ufb.base);
438
+
drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base);
439
+
}
438
440
}
439
441
440
442
int udl_fbdev_init(struct drm_device *dev)
+12
-13
drivers/gpu/drm/vc4/vc4_plane.c
+12
-13
drivers/gpu/drm/vc4/vc4_plane.c
···
297
297
vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
298
298
vc4_state->crtc_h);
299
299
300
+
vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
301
+
vc4_state->y_scaling[0] == VC4_SCALING_NONE);
302
+
300
303
if (num_planes > 1) {
301
304
vc4_state->is_yuv = true;
302
305
···
315
312
vc4_get_scaling_mode(vc4_state->src_h[1],
316
313
vc4_state->crtc_h);
317
314
318
-
/* YUV conversion requires that scaling be enabled,
319
-
* even on a plane that's otherwise 1:1. Choose TPZ
320
-
* for simplicity.
315
+
/* YUV conversion requires that horizontal scaling be enabled,
316
+
* even on a plane that's otherwise 1:1. Looks like only PPF
317
+
* works in that case, so let's pick that one.
321
318
*/
322
-
if (vc4_state->x_scaling[0] == VC4_SCALING_NONE)
323
-
vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
324
-
if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
325
-
vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
319
+
if (vc4_state->is_unity)
320
+
vc4_state->x_scaling[0] = VC4_SCALING_PPF;
326
321
} else {
327
322
vc4_state->x_scaling[1] = VC4_SCALING_NONE;
328
323
vc4_state->y_scaling[1] = VC4_SCALING_NONE;
329
324
}
330
-
331
-
vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
332
-
vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
333
-
vc4_state->x_scaling[1] == VC4_SCALING_NONE &&
334
-
vc4_state->y_scaling[1] == VC4_SCALING_NONE);
335
325
336
326
/* No configuring scaling on the cursor plane, since it gets
337
327
non-vblank-synced updates, and scaling requires requires
···
668
672
vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
669
673
}
670
674
671
-
if (!vc4_state->is_unity) {
675
+
if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
676
+
vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
677
+
vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
678
+
vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
672
679
/* LBM Base Address. */
673
680
if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
674
681
vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
···
3729
3729
{
3730
3730
struct vmw_buffer_object *vbo =
3731
3731
container_of(bo, struct vmw_buffer_object, base);
3732
-
struct ttm_operation_ctx ctx = { interruptible, true };
3732
+
struct ttm_operation_ctx ctx = { interruptible, false };
3733
3733
int ret;
3734
3734
3735
3735
if (vbo->pin_count > 0)
+30
-12
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+30
-12
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
1512
1512
struct drm_rect *rects)
1513
1513
{
1514
1514
struct vmw_private *dev_priv = vmw_priv(dev);
1515
-
struct drm_mode_config *mode_config = &dev->mode_config;
1516
1515
struct drm_rect bounding_box = {0};
1517
1516
u64 total_pixels = 0, pixel_mem, bb_mem;
1518
1517
int i;
1519
1518
1520
1519
for (i = 0; i < num_rects; i++) {
1521
1520
/*
1522
-
* Currently this check is limiting the topology within max
1523
-
* texture/screentarget size. This should change in future when
1524
-
* user-space support multiple fb with topology.
1521
+
* For STDU only individual screen (screen target) is limited by
1522
+
* SCREENTARGET_MAX_WIDTH/HEIGHT registers.
1525
1523
*/
1526
-
if (rects[i].x1 < 0 || rects[i].y1 < 0 ||
1527
-
rects[i].x2 > mode_config->max_width ||
1528
-
rects[i].y2 > mode_config->max_height) {
1529
-
DRM_ERROR("Invalid GUI layout.\n");
1524
+
if (dev_priv->active_display_unit == vmw_du_screen_target &&
1525
+
(drm_rect_width(&rects[i]) > dev_priv->stdu_max_width ||
1526
+
drm_rect_height(&rects[i]) > dev_priv->stdu_max_height)) {
1527
+
DRM_ERROR("Screen size not supported.\n");
1530
1528
return -EINVAL;
1531
1529
}
1532
1530
···
1613
1615
struct drm_connector_state *conn_state;
1614
1616
struct vmw_connector_state *vmw_conn_state;
1615
1617
1616
-
if (!new_crtc_state->enable && old_crtc_state->enable) {
1618
+
if (!new_crtc_state->enable) {
1617
1619
rects[i].x1 = 0;
1618
1620
rects[i].y1 = 0;
1619
1621
rects[i].x2 = 0;
···
2214
2216
if (dev_priv->assume_16bpp)
2215
2217
assumed_bpp = 2;
2216
2218
2219
+
max_width = min(max_width, dev_priv->texture_max_width);
2220
+
max_height = min(max_height, dev_priv->texture_max_height);
2221
+
2222
+
/*
2223
+
* For STDU extra limit for a mode on SVGA_REG_SCREENTARGET_MAX_WIDTH/
2224
+
* HEIGHT registers.
2225
+
*/
2217
2226
if (dev_priv->active_display_unit == vmw_du_screen_target) {
2218
2227
max_width = min(max_width, dev_priv->stdu_max_width);
2219
-
max_width = min(max_width, dev_priv->texture_max_width);
2220
-
2221
2228
max_height = min(max_height, dev_priv->stdu_max_height);
2222
-
max_height = min(max_height, dev_priv->texture_max_height);
2223
2229
}
2224
2230
2225
2231
/* Add preferred mode */
···
2378
2376
struct drm_file *file_priv)
2379
2377
{
2380
2378
struct vmw_private *dev_priv = vmw_priv(dev);
2379
+
struct drm_mode_config *mode_config = &dev->mode_config;
2381
2380
struct drm_vmw_update_layout_arg *arg =
2382
2381
(struct drm_vmw_update_layout_arg *)data;
2383
2382
void __user *user_rects;
···
2424
2421
drm_rects[i].y1 = curr_rect.y;
2425
2422
drm_rects[i].x2 = curr_rect.x + curr_rect.w;
2426
2423
drm_rects[i].y2 = curr_rect.y + curr_rect.h;
2424
+
2425
+
/*
2426
+
* Currently this check is limiting the topology within
2427
+
* mode_config->max (which actually is max texture size
2428
+
* supported by virtual device). This limit is here to address
2429
+
* window managers that create a big framebuffer for whole
2430
+
* topology.
2431
+
*/
2432
+
if (drm_rects[i].x1 < 0 || drm_rects[i].y1 < 0 ||
2433
+
drm_rects[i].x2 > mode_config->max_width ||
2434
+
drm_rects[i].y2 > mode_config->max_height) {
2435
+
DRM_ERROR("Invalid GUI layout.\n");
2436
+
ret = -EINVAL;
2437
+
goto out_free;
2438
+
}
2427
2439
}
2428
2440
2429
2441
ret = vmw_kms_check_display_memory(dev, arg->num_outputs, drm_rects);
-25
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
-25
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
···
1600
1600
1601
1601
dev_priv->active_display_unit = vmw_du_screen_target;
1602
1602
1603
-
if (dev_priv->capabilities & SVGA_CAP_3D) {
1604
-
/*
1605
-
* For 3D VMs, display (scanout) buffer size is the smaller of
1606
-
* max texture and max STDU
1607
-
*/
1608
-
uint32_t max_width, max_height;
1609
-
1610
-
max_width = min(dev_priv->texture_max_width,
1611
-
dev_priv->stdu_max_width);
1612
-
max_height = min(dev_priv->texture_max_height,
1613
-
dev_priv->stdu_max_height);
1614
-
1615
-
dev->mode_config.max_width = max_width;
1616
-
dev->mode_config.max_height = max_height;
1617
-
} else {
1618
-
/*
1619
-
* Given various display aspect ratios, there's no way to
1620
-
* estimate these using prim_bb_mem. So just set these to
1621
-
* something arbitrarily large and we will reject any layout
1622
-
* that doesn't fit prim_bb_mem later
1623
-
*/
1624
-
dev->mode_config.max_width = 8192;
1625
-
dev->mode_config.max_height = 8192;
1626
-
}
1627
-
1628
1603
vmw_kms_create_implicit_placement_property(dev_priv, false);
1629
1604
1630
1605
for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
+14
-10
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+14
-10
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
···
1404
1404
*srf_out = NULL;
1405
1405
1406
1406
if (for_scanout) {
1407
-
uint32_t max_width, max_height;
1408
-
1409
1407
if (!svga3dsurface_is_screen_target_format(format)) {
1410
1408
DRM_ERROR("Invalid Screen Target surface format.");
1411
1409
return -EINVAL;
1412
1410
}
1413
1411
1414
-
max_width = min(dev_priv->texture_max_width,
1415
-
dev_priv->stdu_max_width);
1416
-
max_height = min(dev_priv->texture_max_height,
1417
-
dev_priv->stdu_max_height);
1418
-
1419
-
if (size.width > max_width || size.height > max_height) {
1412
+
if (size.width > dev_priv->texture_max_width ||
1413
+
size.height > dev_priv->texture_max_height) {
1420
1414
DRM_ERROR("%ux%u\n, exceeds max surface size %ux%u",
1421
1415
size.width, size.height,
1422
-
max_width, max_height);
1416
+
dev_priv->texture_max_width,
1417
+
dev_priv->texture_max_height);
1423
1418
return -EINVAL;
1424
1419
}
1425
1420
} else {
···
1490
1495
if (srf->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
1491
1496
srf->res.backup_size += sizeof(SVGA3dDXSOState);
1492
1497
1498
+
/*
1499
+
* Don't set SVGA3D_SURFACE_SCREENTARGET flag for a scanout surface with
1500
+
* size greater than STDU max width/height. This is really a workaround
1501
+
* to support creation of big framebuffer requested by some user-space
1502
+
* for whole topology. That big framebuffer won't really be used for
1503
+
* binding with screen target as during prepare_fb a separate surface is
1504
+
* created so it's safe to ignore SVGA3D_SURFACE_SCREENTARGET flag.
1505
+
*/
1493
1506
if (dev_priv->active_display_unit == vmw_du_screen_target &&
1494
-
for_scanout)
1507
+
for_scanout && size.width <= dev_priv->stdu_max_width &&
1508
+
size.height <= dev_priv->stdu_max_height)
1495
1509
srf->flags |= SVGA3D_SURFACE_SCREENTARGET;
1496
1510
1497
1511
/*
+1
-1
include/drm/drm_drv.h
+1
-1
include/drm/drm_drv.h
···
675
675
static inline bool drm_drv_uses_atomic_modeset(struct drm_device *dev)
676
676
{
677
677
return drm_core_check_feature(dev, DRIVER_ATOMIC) ||
678
-
dev->mode_config.funcs->atomic_commit != NULL;
678
+
(dev->mode_config.funcs && dev->mode_config.funcs->atomic_commit != NULL);
679
679
}
680
680
681
681