Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: aspeed-sgpio: Create llops to handle hardware access
Add low-level operations (llops) to abstract the register access for SGPIO
registers. With this abstraction layer, the driver can separate the
hardware and software logic, making it easier to extend the driver to
support different hardware register layouts.
The llops abstraction changes the programming semantics from bitmask-based
writes to a value-based interface.
Instead of passing a pre-shifted bitmask to the caller, the driver now
passes:
- the GPIO offset, and
- the value to be set (0 or 1),
and the llops helpers are responsible for deriving the correct register
and bit position internally.
As a result, assignments such as:
type0 = 1;
type1 = 1;
type2 = 1;
do not represent a behavioral change. They indicate that the bit
corresponding to the given GPIO offset should be set, with the actual
bit manipulation handled by llops.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20260123-upstream_sgpio-v2-3-69cfd1631400@aspeedtech.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
authored by
Billy Tsai
and committed by
Bartosz Golaszewski
a3d37e0c
5928e0d1
+104
-118
+104
-118
drivers/gpio/gpio-aspeed-sgpio.c
+104
-118
drivers/gpio/gpio-aspeed-sgpio.c
···
27
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struct aspeed_sgpio_pdata {
29
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const u32 pin_mask;
30
+
const struct aspeed_sgpio_llops *llops;
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};
31
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32
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struct aspeed_sgpio {
···
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raw_spinlock_t lock;
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void __iomem *base;
39
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int irq;
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+
const struct aspeed_sgpio_pdata *pdata;
40
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};
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struct aspeed_sgpio_bank {
···
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reg_tolerance,
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};
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+
struct aspeed_sgpio_llops {
94
+
void (*reg_bit_set)(struct aspeed_sgpio *gpio, unsigned int offset,
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+
const enum aspeed_sgpio_reg reg, bool val);
96
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bool (*reg_bit_get)(struct aspeed_sgpio *gpio, unsigned int offset,
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+
const enum aspeed_sgpio_reg reg);
98
+
int (*reg_bank_get)(struct aspeed_sgpio *gpio, unsigned int offset,
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const enum aspeed_sgpio_reg reg);
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+
};
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+
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#define GPIO_VAL_VALUE 0x00
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#define GPIO_IRQ_ENABLE 0x00
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#define GPIO_IRQ_TYPE0 0x04
···
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#define GPIO_IRQ_TYPE2 0x0C
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#define GPIO_IRQ_STATUS 0x10
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-
static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
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-
const struct aspeed_sgpio_bank *bank,
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-
const enum aspeed_sgpio_reg reg)
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+
static void __iomem *aspeed_sgpio_g4_bank_reg(struct aspeed_sgpio *gpio,
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const struct aspeed_sgpio_bank *bank,
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const enum aspeed_sgpio_reg reg)
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{
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switch (reg) {
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case reg_val:
···
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static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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-
const struct aspeed_sgpio_bank *bank = to_bank(offset);
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enum aspeed_sgpio_reg reg;
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int rc = 0;
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guard(raw_spinlock_irqsave)(&gpio->lock);
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reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
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rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
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rc = gpio->pdata->llops->reg_bit_get(gpio, offset, reg);
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return rc;
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}
···
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static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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void __iomem *addr_r, *addr_w;
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u32 reg = 0;
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if (aspeed_sgpio_is_input(offset))
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return -EINVAL;
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-
/* Since this is an output, read the cached value from rdata, then
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* update val. */
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addr_r = bank_reg(gpio, bank, reg_rdata);
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addr_w = bank_reg(gpio, bank, reg_val);
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-
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reg = ioread32(addr_r);
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-
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if (val)
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reg |= GPIO_BIT(offset);
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-
else
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reg &= ~GPIO_BIT(offset);
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-
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iowrite32(reg, addr_w);
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gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, val);
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return 0;
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}
···
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return !!aspeed_sgpio_is_input(offset);
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}
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-
static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
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struct aspeed_sgpio **gpio,
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const struct aspeed_sgpio_bank **bank,
239
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u32 *bit, int *offset)
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-
{
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struct aspeed_sgpio *internal;
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-
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*offset = irqd_to_hwirq(d);
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internal = irq_data_get_irq_chip_data(d);
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WARN_ON(!internal);
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-
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*gpio = internal;
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*bank = to_bank(*offset);
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-
*bit = GPIO_BIT(*offset);
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-
}
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static void aspeed_sgpio_irq_ack(struct irq_data *d)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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void __iomem *status_addr;
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int offset;
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u32 bit;
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-
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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-
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-
status_addr = bank_reg(gpio, bank, reg_irq_status);
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struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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guard(raw_spinlock_irqsave)(&gpio->lock);
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-
iowrite32(bit, status_addr);
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gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_status, 1);
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}
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static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
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{
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const struct aspeed_sgpio_bank *bank;
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struct aspeed_sgpio *gpio;
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u32 reg, bit;
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-
void __iomem *addr;
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int offset;
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-
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irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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-
addr = bank_reg(gpio, bank, reg_irq_enable);
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struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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/* Unmasking the IRQ */
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if (set)
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-
gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d));
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-
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-
scoped_guard(raw_spinlock_irqsave, &gpio->lock) {
285
-
reg = ioread32(addr);
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-
if (set)
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-
reg |= bit;
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-
else
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-
reg &= ~bit;
290
-
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-
iowrite32(reg, addr);
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+
gpiochip_enable_irq(&gpio->chip, offset);
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scoped_guard(raw_spinlock_irqsave, &gpio->lock)
261
+
{
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gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_enable,
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+
set);
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}
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/* Masking the IRQ */
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if (!set)
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-
gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d));
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-
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-
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+
gpiochip_disable_irq(&gpio->chip, offset);
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}
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static void aspeed_sgpio_irq_mask(struct irq_data *d)
···
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u32 type0 = 0;
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u32 type1 = 0;
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u32 type2 = 0;
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u32 bit, reg;
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const struct aspeed_sgpio_bank *bank;
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irq_flow_handler_t handler;
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struct aspeed_sgpio *gpio;
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void __iomem *addr;
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int offset;
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-
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-
irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
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struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d);
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int offset = irqd_to_hwirq(d);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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-
type2 |= bit;
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type2 = 1;
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fallthrough;
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case IRQ_TYPE_EDGE_RISING:
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type0 |= bit;
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type0 = 1;
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fallthrough;
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case IRQ_TYPE_EDGE_FALLING:
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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type0 |= bit;
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type0 = 1;
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fallthrough;
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case IRQ_TYPE_LEVEL_LOW:
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-
type1 |= bit;
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+
type1 = 1;
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handler = handle_level_irq;
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break;
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default:
···
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}
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scoped_guard(raw_spinlock_irqsave, &gpio->lock) {
307
-
addr = bank_reg(gpio, bank, reg_irq_type0);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type0;
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iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type1);
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reg = ioread32(addr);
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reg = (reg & ~bit) | type1;
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-
iowrite32(reg, addr);
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addr = bank_reg(gpio, bank, reg_irq_type2);
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-
reg = ioread32(addr);
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-
reg = (reg & ~bit) | type2;
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-
iowrite32(reg, addr);
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+
gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0);
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+
gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1);
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gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2);
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}
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irq_set_handler_locked(d, handler);
···
325
381
chained_irq_enter(ic, desc);
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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-
const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
329
-
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-
reg = ioread32(bank_reg(data, bank, reg_irq_status));
384
+
reg = data->pdata->llops->reg_bank_get(data, i << 6, reg_irq_status);
331
385
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386
for_each_set_bit(p, ®, 32)
333
387
generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
···
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395
static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
338
396
{
339
-
const struct aspeed_sgpio_bank *bank;
340
-
struct aspeed_sgpio *gpio;
341
-
u32 bit;
342
-
int offset;
397
+
struct aspeed_sgpio *gpio = irq_data_get_irq_chip_data(d);
343
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-
irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
345
399
seq_puts(p, dev_name(gpio->dev));
346
400
}
347
401
···
385
447
386
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/* Apply default IRQ settings */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
388
-
bank = &aspeed_sgpio_banks[i];
450
+
bank = &aspeed_sgpio_banks[i];
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/* set falling or level-low irq */
390
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
391
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/* trigger type is edge */
···
397
459
return 0;
398
460
}
399
461
462
+
static void aspeed_sgpio_g4_reg_bit_set(struct aspeed_sgpio *gpio, unsigned int offset,
463
+
const enum aspeed_sgpio_reg reg, bool val)
464
+
{
465
+
const struct aspeed_sgpio_bank *bank = to_bank(offset);
466
+
void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);
467
+
u32 temp;
468
+
469
+
if (reg == reg_val) {
470
+
/* Since this is an output, read the cached value from rdata, then update val. */
471
+
addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_rdata);
472
+
temp = ioread32(addr);
473
+
if (val)
474
+
temp |= GPIO_BIT(offset);
475
+
else
476
+
temp &= ~GPIO_BIT(offset);
477
+
478
+
addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val);
479
+
iowrite32(temp, addr);
480
+
} else if (reg == reg_irq_status) {
481
+
if (val)
482
+
iowrite32(GPIO_BIT(offset), addr);
483
+
} else {
484
+
/* When setting other registers, we read from the register itself */
485
+
temp = ioread32(addr);
486
+
if (val)
487
+
temp |= GPIO_BIT(offset);
488
+
else
489
+
temp &= ~GPIO_BIT(offset);
490
+
iowrite32(temp, addr);
491
+
}
492
+
}
493
+
494
+
static bool aspeed_sgpio_g4_reg_bit_get(struct aspeed_sgpio *gpio, unsigned int offset,
495
+
const enum aspeed_sgpio_reg reg)
496
+
{
497
+
const struct aspeed_sgpio_bank *bank = to_bank(offset);
498
+
void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);
499
+
500
+
return !!(ioread32(addr) & GPIO_BIT(offset));
501
+
}
502
+
503
+
static int aspeed_sgpio_g4_reg_bank_get(struct aspeed_sgpio *gpio, unsigned int offset,
504
+
const enum aspeed_sgpio_reg reg)
505
+
{
506
+
const struct aspeed_sgpio_bank *bank = to_bank(offset);
507
+
void __iomem *addr = aspeed_sgpio_g4_bank_reg(gpio, bank, reg);
508
+
509
+
if (reg == reg_irq_status)
510
+
return ioread32(addr);
511
+
else
512
+
return -EOPNOTSUPP;
513
+
}
514
+
515
+
static const struct aspeed_sgpio_llops aspeed_sgpio_g4_llops = {
516
+
.reg_bit_set = aspeed_sgpio_g4_reg_bit_set,
517
+
.reg_bit_get = aspeed_sgpio_g4_reg_bit_get,
518
+
.reg_bank_get = aspeed_sgpio_g4_reg_bank_get,
519
+
};
520
+
400
521
static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
401
522
.pin_mask = GENMASK(9, 6),
523
+
.llops = &aspeed_sgpio_g4_llops,
402
524
};
403
525
404
526
static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
405
527
unsigned int offset, bool enable)
406
528
{
407
529
struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
408
-
void __iomem *reg;
409
-
u32 val;
410
-
411
-
reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
412
530
413
531
guard(raw_spinlock_irqsave)(&gpio->lock);
414
532
415
-
val = readl(reg);
416
-
417
-
if (enable)
418
-
val |= GPIO_BIT(offset);
419
-
else
420
-
val &= ~GPIO_BIT(offset);
421
-
422
-
writel(val, reg);
533
+
gpio->pdata->llops->reg_bit_set(gpio, offset, reg_tolerance, enable);
423
534
424
535
return 0;
425
536
}
···
487
500
488
501
static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
489
502
.pin_mask = GENMASK(10, 6),
503
+
.llops = &aspeed_sgpio_g4_llops,
490
504
};
491
505
492
506
static const struct of_device_id aspeed_sgpio_of_table[] = {
···
502
514
static int aspeed_sgpio_probe(struct platform_device *pdev)
503
515
{
504
516
u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
505
-
const struct aspeed_sgpio_pdata *pdata;
506
517
struct aspeed_sgpio *gpio;
507
518
unsigned long apb_freq;
508
519
int rc;
···
516
529
517
530
gpio->dev = &pdev->dev;
518
531
519
-
pdata = device_get_match_data(&pdev->dev);
520
-
if (!pdata)
532
+
gpio->pdata = device_get_match_data(&pdev->dev);
533
+
if (!gpio->pdata)
521
534
return -EINVAL;
522
535
523
-
pin_mask = pdata->pin_mask;
524
-
536
+
pin_mask = gpio->pdata->pin_mask;
525
537
rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
526
538
if (rc < 0) {
527
539
dev_err(&pdev->dev, "Could not read ngpios property\n");