Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev:
pata_hpt37x: Further improvements based on the IDE updates and vendor drivers
pata: Trivia
[libata] sata_via, pata_via: Add PCI IDs.
[libata] Fix decoding of 6-byte commands
libata: sata_sis fixes
Fix build failure for drivers/ata/pata_scc.c
[libata] sata_mv: add TODO list
[libata] sata_promise: fix flags typo
+98
-45
+3
-2
drivers/ata/libata-scsi.c
+3
-2
drivers/ata/libata-scsi.c
···
1050
1050
static void scsi_6_lba_len(const u8 *cdb, u64 *plba, u32 *plen)
1051
1051
{
1052
1052
u64 lba = 0;
1053
-
u32 len = 0;
1053
+
u32 len;
1054
1054
1055
1055
VPRINTK("six-byte command\n");
1056
1056
1057
+
lba |= ((u64)(cdb[1] & 0x1f)) << 16;
1057
1058
lba |= ((u64)cdb[2]) << 8;
1058
1059
lba |= ((u64)cdb[3]);
1059
1060
1060
-
len |= ((u32)cdb[4]);
1061
+
len = cdb[4];
1061
1062
1062
1063
*plba = lba;
1063
1064
*plen = len;
+1
-1
drivers/ata/pata_artop.c
+1
-1
drivers/ata/pata_artop.c
···
97
97
* artop6260_cable_detect - identify cable type
98
98
* @ap: Port
99
99
*
100
-
* Identify the cable type for the ARTOp interface in question
100
+
* Identify the cable type for the ARTOP interface in question
101
101
*/
102
102
103
103
static int artop6260_cable_detect(struct ata_port *ap)
+11
-16
drivers/ata/pata_hpt37x.c
+11
-16
drivers/ata/pata_hpt37x.c
···
26
26
#include <linux/libata.h>
27
27
28
28
#define DRV_NAME "pata_hpt37x"
29
-
#define DRV_VERSION "0.6.5"
29
+
#define DRV_VERSION "0.6.6"
30
30
31
31
struct hpt_clock {
32
32
u8 xfer_speed;
···
931
931
.udma_mask = 0x7f,
932
932
.port_ops = &hpt372_port_ops
933
933
};
934
-
/* HPT371, 372 and friends - UDMA100 at 50MHz clock */
935
-
static const struct ata_port_info info_hpt372_50 = {
936
-
.sht = &hpt37x_sht,
937
-
.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
938
-
.pio_mask = 0x1f,
939
-
.mwdma_mask = 0x07,
940
-
.udma_mask = 0x3f,
941
-
.port_ops = &hpt372_port_ops
942
-
};
943
934
/* HPT374 - UDMA133 */
944
935
static const struct ata_port_info info_hpt374 = {
945
936
.sht = &hpt37x_sht,
···
1089
1098
* use a 50MHz DPLL by choice
1090
1099
*/
1091
1100
unsigned int f_low, f_high;
1092
-
int adjust;
1101
+
int dpll, adjust;
1093
1102
1094
-
clock_slot = 2;
1103
+
/* Compute DPLL */
1104
+
dpll = 2;
1095
1105
if (port->udma_mask & 0xE0)
1096
-
clock_slot = 3;
1106
+
dpll = 3;
1097
1107
1098
-
f_low = (MHz[clock_slot] * chip_table->base) / 192;
1108
+
f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1099
1109
f_high = f_low + 2;
1110
+
if (clock_slot > 1)
1111
+
f_high += 2;
1100
1112
1101
1113
/* Select the DPLL clock. */
1102
1114
pci_write_config_byte(dev, 0x5b, 0x21);
1115
+
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1103
1116
1104
1117
for(adjust = 0; adjust < 8; adjust++) {
1105
1118
if (hpt37x_calibrate_dpll(dev))
···
1119
1124
printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1120
1125
return -ENODEV;
1121
1126
}
1122
-
if (clock_slot == 3)
1127
+
if (dpll == 3)
1123
1128
private_data = (void *)hpt37x_timings_66;
1124
1129
else
1125
1130
private_data = (void *)hpt37x_timings_50;
1126
1131
1127
-
printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1132
+
printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[dpll]);
1128
1133
} else {
1129
1134
private_data = (void *)chip_table->clocks[clock_slot];
1130
1135
/*
+1
-2
drivers/ata/pata_it821x.c
+1
-2
drivers/ata/pata_it821x.c
···
1
1
/*
2
-
* ata-it821x.c - IT821x PATA for new ATA layer
2
+
* pata_it821x.c - IT821x PATA for new ATA layer
3
3
* (C) 2005 Red Hat Inc
4
4
* Alan Cox <alan@redhat.com>
5
5
*
···
65
65
*
66
66
* TODO
67
67
* - ATAPI and other speed filtering
68
-
* - Command filter in smart mode
69
68
* - RAID configuration ioctls
70
69
*/
71
70
+28
-18
drivers/ata/pata_scc.c
+28
-18
drivers/ata/pata_scc.c
···
489
489
* Note: Original code is ata_bus_post_reset().
490
490
*/
491
491
492
-
static void scc_bus_post_reset (struct ata_port *ap, unsigned int devmask)
492
+
static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
493
+
unsigned long deadline)
493
494
{
494
495
struct ata_ioports *ioaddr = &ap->ioaddr;
495
496
unsigned int dev0 = devmask & (1 << 0);
496
497
unsigned int dev1 = devmask & (1 << 1);
497
-
unsigned long timeout;
498
+
int rc;
498
499
499
500
/* if device 0 was found in ata_devchk, wait for its
500
501
* BSY bit to clear
501
502
*/
502
-
if (dev0)
503
-
ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
503
+
if (dev0) {
504
+
rc = ata_wait_ready(ap, deadline);
505
+
if (rc && rc != -ENODEV)
506
+
return rc;
507
+
}
504
508
505
509
/* if device 1 was found in ata_devchk, wait for
506
510
* register access, then wait for BSY to clear
507
511
*/
508
-
timeout = jiffies + ATA_TMOUT_BOOT;
509
512
while (dev1) {
510
513
u8 nsect, lbal;
511
514
···
517
514
lbal = in_be32(ioaddr->lbal_addr);
518
515
if ((nsect == 1) && (lbal == 1))
519
516
break;
520
-
if (time_after(jiffies, timeout)) {
521
-
dev1 = 0;
522
-
break;
523
-
}
517
+
if (time_after(jiffies, deadline))
518
+
return -EBUSY;
524
519
msleep(50); /* give drive a breather */
525
520
}
526
-
if (dev1)
527
-
ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
521
+
if (dev1) {
522
+
rc = ata_wait_ready(ap, deadline);
523
+
if (rc && rc != -ENODEV)
524
+
return rc;
525
+
}
528
526
529
527
/* is all this really necessary? */
530
528
ap->ops->dev_select(ap, 0);
···
533
529
ap->ops->dev_select(ap, 1);
534
530
if (dev0)
535
531
ap->ops->dev_select(ap, 0);
532
+
533
+
return 0;
536
534
}
537
535
538
536
/**
···
543
537
* Note: Original code is ata_bus_softreset().
544
538
*/
545
539
546
-
static unsigned int scc_bus_softreset (struct ata_port *ap,
547
-
unsigned int devmask)
540
+
static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
541
+
unsigned long deadline)
548
542
{
549
543
struct ata_ioports *ioaddr = &ap->ioaddr;
550
544
···
576
570
if (scc_check_status(ap) == 0xFF)
577
571
return 0;
578
572
579
-
scc_bus_post_reset(ap, devmask);
573
+
scc_bus_post_reset(ap, devmask, deadline);
580
574
581
575
return 0;
582
576
}
···
585
579
* scc_std_softreset - reset host port via ATA SRST
586
580
* @ap: port to reset
587
581
* @classes: resulting classes of attached devices
582
+
* @deadline: deadline jiffies for the operation
588
583
*
589
584
* Note: Original code is ata_std_softreset().
590
585
*/
591
586
592
-
static int scc_std_softreset (struct ata_port *ap, unsigned int *classes)
587
+
static int scc_std_softreset (struct ata_port *ap, unsigned int *classes,
588
+
unsigned long deadline)
593
589
{
594
590
unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
595
591
unsigned int devmask = 0, err_mask;
···
615
607
616
608
/* issue bus reset */
617
609
DPRINTK("about to softreset, devmask=%x\n", devmask);
618
-
err_mask = scc_bus_softreset(ap, devmask);
610
+
err_mask = scc_bus_softreset(ap, devmask, deadline);
619
611
if (err_mask) {
620
612
ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
621
613
err_mask);
···
684
676
685
677
if (reg & INTSTS_BMSINT) {
686
678
unsigned int classes;
679
+
unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
687
680
printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
688
681
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
689
682
/* TBD: SW reset */
690
-
scc_std_softreset(ap, &classes);
683
+
scc_std_softreset(ap, &classes, deadline);
691
684
continue;
692
685
}
693
686
···
871
862
/**
872
863
* scc_pata_prereset - prepare for reset
873
864
* @ap: ATA port to be reset
865
+
* @deadline: deadline jiffies for the operation
874
866
*/
875
867
876
-
static int scc_pata_prereset (struct ata_port *ap, unsigned long deadline)
868
+
static int scc_pata_prereset(struct ata_port *ap, unsigned long deadline)
877
869
{
878
870
ap->cbl = ATA_CBL_PATA80;
879
871
return ata_std_prereset(ap, deadline);
+5
-4
drivers/ata/pata_via.c
+5
-4
drivers/ata/pata_via.c
···
621
621
#endif
622
622
623
623
static const struct pci_device_id via[] = {
624
-
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
625
-
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
626
-
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
627
-
{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
624
+
{ PCI_VDEVICE(VIA, 0x0571), },
625
+
{ PCI_VDEVICE(VIA, 0x0581), },
626
+
{ PCI_VDEVICE(VIA, 0x1571), },
627
+
{ PCI_VDEVICE(VIA, 0x3164), },
628
+
{ PCI_VDEVICE(VIA, 0x5324), },
628
629
629
630
{ },
630
631
};
+44
drivers/ata/sata_mv.c
+44
drivers/ata/sata_mv.c
···
21
21
*
22
22
*/
23
23
24
+
/*
25
+
sata_mv TODO list:
26
+
27
+
1) Needs a full errata audit for all chipsets. I implemented most
28
+
of the errata workarounds found in the Marvell vendor driver, but
29
+
I distinctly remember a couple workarounds (one related to PCI-X)
30
+
are still needed.
31
+
32
+
2) Convert to LibATA new EH. Required for hotplug, NCQ, and sane
33
+
probing/error handling in general. MUST HAVE.
34
+
35
+
3) Add hotplug support (easy, once new-EH support appears)
36
+
37
+
4) Add NCQ support (easy to intermediate, once new-EH support appears)
38
+
39
+
5) Investigate problems with PCI Message Signalled Interrupts (MSI).
40
+
41
+
6) Add port multiplier support (intermediate)
42
+
43
+
7) Test and verify 3.0 Gbps support
44
+
45
+
8) Develop a low-power-consumption strategy, and implement it.
46
+
47
+
9) [Experiment, low priority] See if ATAPI can be supported using
48
+
"unknown FIS" or "vendor-specific FIS" support, or something creative
49
+
like that.
50
+
51
+
10) [Experiment, low priority] Investigate interrupt coalescing.
52
+
Quite often, especially with PCI Message Signalled Interrupts (MSI),
53
+
the overhead reduced by interrupt mitigation is quite often not
54
+
worth the latency cost.
55
+
56
+
11) [Experiment, Marvell value added] Is it possible to use target
57
+
mode to cross-connect two Linux boxes with Marvell cards? If so,
58
+
creating LibATA target mode support would be very interesting.
59
+
60
+
Target mode, for those without docs, is the ability to directly
61
+
connect two SATA controllers.
62
+
63
+
13) Verify that 7042 is fully supported. I only have a 6042.
64
+
65
+
*/
66
+
67
+
24
68
#include <linux/kernel.h>
25
69
#include <linux/module.h>
26
70
#include <linux/pci.h>
+1
-1
drivers/ata/sata_promise.c
+1
-1
drivers/ata/sata_promise.c
+1
-1
drivers/ata/sata_sis.c
+1
-1
drivers/ata/sata_sis.c
+3
drivers/ata/sata_via.c
+3
drivers/ata/sata_via.c
···
85
85
{ PCI_VDEVICE(VIA, 0x0591), vt6420 },
86
86
{ PCI_VDEVICE(VIA, 0x3149), vt6420 },
87
87
{ PCI_VDEVICE(VIA, 0x3249), vt6421 },
88
+
{ PCI_VDEVICE(VIA, 0x5287), vt6420 },
89
+
{ PCI_VDEVICE(VIA, 0x5372), vt6420 },
90
+
{ PCI_VDEVICE(VIA, 0x7372), vt6420 },
88
91
89
92
{ } /* terminate list */
90
93
};