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drm/amdgpu: Setup Retry based thrashing prevention on GFX 12.1

Enable the new UTCL0 retry-based thrashing prevention on GFX 12.1.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Mukul Joshi and committed by
Alex Deucher a41d94a7 44fc86f2

+21 -1
+21 -1
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
··· 2607 2607 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); 2608 2608 } 2609 2609 2610 + static void gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(struct amdgpu_device *adev, 2611 + int xcc_id) 2612 + { 2613 + uint32_t val; 2614 + 2615 + /* Set the TCP UTCL0 register to enable atomics */ 2616 + val = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2617 + regTCP_UTCL0_THRASHING_CTRL); 2618 + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, THRASHING_EN, 0x2); 2619 + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, 2620 + RETRY_FRAGMENT_THRESHOLD_UP_EN, 0x1); 2621 + val = REG_SET_FIELD(val, TCP_UTCL0_THRASHING_CTRL, 2622 + RETRY_FRAGMENT_THRESHOLD_DOWN_EN, 0x1); 2623 + 2624 + WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2625 + regTCP_UTCL0_THRASHING_CTRL, val); 2626 + } 2627 + 2610 2628 static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, 2611 2629 int xcc_id) 2612 2630 { ··· 2641 2623 { 2642 2624 int i; 2643 2625 2644 - for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) 2626 + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { 2645 2627 gfx_v12_1_xcc_enable_atomics(adev, i); 2628 + gfx_v12_1_xcc_setup_tcp_thrashing_ctrl(adev, i); 2629 + } 2646 2630 } 2647 2631 2648 2632 static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block)