Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdkfd: Improve function get_sdma_rlc_reg_offset() (v2)
The SOC15_REG_OFFSET() macro needs to dereference adev->reg_offset[IP]
pointer, which is sometimes NULL when there are fewer than 8 sdma engines.
Avoid that by not initializing the array regardless.
v2: squash in warning fixes
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Yong Zhao
and committed by
Alex Deucher
a434b94c
1fc636c9
+45
-21
+45
-21
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+45
-21
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
···
71
71
unsigned int engine_id,
72
72
unsigned int queue_id)
73
73
{
74
-
uint32_t sdma_engine_reg_base[8] = {
75
-
SOC15_REG_OFFSET(SDMA0, 0,
76
-
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
77
-
SOC15_REG_OFFSET(SDMA1, 0,
78
-
mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
79
-
SOC15_REG_OFFSET(SDMA2, 0,
80
-
mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
81
-
SOC15_REG_OFFSET(SDMA3, 0,
82
-
mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
83
-
SOC15_REG_OFFSET(SDMA4, 0,
84
-
mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
85
-
SOC15_REG_OFFSET(SDMA5, 0,
86
-
mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
87
-
SOC15_REG_OFFSET(SDMA6, 0,
88
-
mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
89
-
SOC15_REG_OFFSET(SDMA7, 0,
90
-
mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
91
-
};
74
+
uint32_t sdma_engine_reg_base = 0;
75
+
uint32_t sdma_rlc_reg_offset;
92
76
93
-
uint32_t retval = sdma_engine_reg_base[engine_id]
77
+
switch (engine_id) {
78
+
default:
79
+
dev_warn(adev->dev,
80
+
"Invalid sdma engine id (%d), using engine id 0\n",
81
+
engine_id);
82
+
/* fall through */
83
+
case 0:
84
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
85
+
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
86
+
break;
87
+
case 1:
88
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
89
+
mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL;
90
+
break;
91
+
case 2:
92
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
93
+
mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;
94
+
break;
95
+
case 3:
96
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
97
+
mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL;
98
+
break;
99
+
case 4:
100
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
101
+
mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL;
102
+
break;
103
+
case 5:
104
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
105
+
mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL;
106
+
break;
107
+
case 6:
108
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
109
+
mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL;
110
+
break;
111
+
case 7:
112
+
sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
113
+
mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL;
114
+
break;
115
+
}
116
+
117
+
sdma_rlc_reg_offset = sdma_engine_reg_base
94
118
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
95
119
96
120
pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
97
-
queue_id, retval);
121
+
queue_id, sdma_rlc_reg_offset);
98
122
99
-
return retval;
123
+
return sdma_rlc_reg_offset;
100
124
}
101
125
102
126
static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,