Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'coresight-next-v6.18-v2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
Suzuki writes:
coresight: Updates for Linux v6.18, take 2
This is an updated drop for v6.18, fixing the invalid commit
reference in the original tag.
CoreSight selfhosted tracing subsystem updates targeting Linux v6.18, includes:
- Clean up and consolidate clocks handling
- Support for exposing labels via sysfs for better device identification
- Add Qualcomm Trace Network On Chip driver support
- Miscellaneous fixes
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
* tag 'coresight-next-v6.18-v2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux: (27 commits)
coresight: Add label sysfs node support
dt-bindings: arm: Add label in the coresight components
coresight: tnoc: add new AMBA ID to support Trace Noc V2
coresight: Fix incorrect handling for return value of devm_kzalloc
coresight: tpda: fix the logic to setup the element size
coresight: trbe: Return NULL pointer for allocation failures
coresight: Refactor runtime PM
coresight: Make clock sequence consistent
coresight: Refactor driver data allocation
coresight: Consolidate clock enabling
coresight: Avoid enable programming clock duplicately
coresight: Appropriately disable trace bus clocks
coresight: Appropriately disable programming clocks
coresight: etm4x: Support atclk
coresight: catu: Support atclk
coresight: tmc: Support atclk
coresight-etm4x: Conditionally access register TRCEXTINSELR
coresight: fix indentation error in cscfg_remove_owned_csdev_configs()
coresight: tnoc: Fix a NULL vs IS_ERR() bug in probe
coresight: add coresight Trace Network On Chip driver
...
+827
-324
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-cti
···
239
239
KernelVersion: 5.7
240
240
Contact: Mike Leach or Mathieu Poirier
241
241
Description: (Write) Clear all channel / trigger programming.
242
+
243
+
What: /sys/bus/coresight/devices/<cti-name>/label
244
+
Date: Aug 2025
245
+
KernelVersion 6.18
246
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
247
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
···
13
13
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
14
14
Description: (R) Show the trace ID that will appear in the trace stream
15
15
coming from this trace entity.
16
+
17
+
What: /sys/bus/coresight/devices/dummy_source<N>/label
18
+
Date: Aug 2025
19
+
KernelVersion 6.18
20
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
21
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10
···
19
19
into the Trace RAM following the trigger event is equal to the
20
20
value stored in this register+1 (from ARM ETB-TRM).
21
21
22
+
What: /sys/bus/coresight/devices/<memory_map>.etb/label
23
+
Date: Aug 2025
24
+
KernelVersion 6.18
25
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
26
+
Description: (Read) Show hardware context information of device.
27
+
22
28
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
23
29
Date: March 2016
24
30
KernelVersion: 4.7
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x
···
251
251
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
252
252
Description: (RO) Holds the cpu number this tracer is affined to.
253
253
254
+
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/label
255
+
Date: Aug 2025
256
+
KernelVersion 6.18
257
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
258
+
Description: (Read) Show hardware context information of device.
259
+
254
260
What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/mgmt/etmccr
255
261
Date: September 2015
256
262
KernelVersion: 4.4
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
···
329
329
Description: (RW) Access the selected single show PE comparator control
330
330
register.
331
331
332
+
What: /sys/bus/coresight/devices/etm<N>/label
333
+
Date: Aug 2025
334
+
KernelVersion 6.18
335
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
336
+
Description: (Read) Show hardware context information of device.
337
+
332
338
What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr
333
339
Date: April 2015
334
340
KernelVersion: 4.01
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-funnel
···
10
10
KernelVersion: 3.19
11
11
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
12
12
Description: (RW) Defines input port priority order.
13
+
14
+
What: /sys/bus/coresight/devices/<memory_map>.funnel/label
15
+
Date: Aug 2025
16
+
KernelVersion 6.18
17
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
18
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
···
51
51
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
52
52
Description: (RW) Holds the trace ID that will appear in the trace stream
53
53
coming from this trace entity.
54
+
55
+
What: /sys/bus/coresight/devices/<memory_map>.stm/label
56
+
Date: Aug 2025
57
+
KernelVersion 6.18
58
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
59
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
···
107
107
Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
108
108
only provide a mode which is supported for a given ETR device. This
109
109
file is available only for TMC ETR devices.
110
+
111
+
What: /sys/bus/coresight/devices/<memory_map>.tmc/label
112
+
Date: Aug 2025
113
+
KernelVersion 6.18
114
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
115
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
···
272
272
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
273
273
Description:
274
274
(RW) Set/Get the enablement of the individual lane.
275
+
276
+
What: /sys/bus/coresight/devices/<tpdm-name>/label
277
+
Date: Aug 2025
278
+
KernelVersion 6.18
279
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
280
+
Description: (Read) Show hardware context information of device.
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
+6
Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe
···
12
12
Description: (Read) Shows if TRBE updates in the memory are with access
13
13
and dirty flag updates as well. This value is fetched from
14
14
the TRBIDR register.
15
+
16
+
What: /sys/bus/coresight/devices/trbe<cpu>/label
17
+
Date: Aug 2025
18
+
KernelVersion 6.18
19
+
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
20
+
Description: (Read) Show hardware context information of device.
+4
Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
+4
Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
+113
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
+113
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Trace Network On Chip - TNOC
8
+
9
+
maintainers:
10
+
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
11
+
12
+
description: >
13
+
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
14
+
component that integrates the functionalities of TPDA and funnels.
15
+
16
+
It sits in the different subsystem of SOC and aggregates the trace and
17
+
transports it to Aggregation TNOC or to coresight trace sink eventually.
18
+
TNOC embeds bridges for all the interfaces APB, ATB, TPDA and NTS (Narrow
19
+
Time Stamp).
20
+
21
+
TNOC can take inputs from different trace sources i.e. ATB, TPDM.
22
+
23
+
Note this binding is specifically intended for Aggregator TNOC instances.
24
+
25
+
# Need a custom select here or 'arm,primecell' will match on lots of nodes
26
+
select:
27
+
properties:
28
+
compatible:
29
+
contains:
30
+
enum:
31
+
- qcom,coresight-tnoc
32
+
required:
33
+
- compatible
34
+
35
+
properties:
36
+
$nodename:
37
+
pattern: "^tn(@[0-9a-f]+)$"
38
+
39
+
compatible:
40
+
items:
41
+
- const: qcom,coresight-tnoc
42
+
- const: arm,primecell
43
+
44
+
reg:
45
+
maxItems: 1
46
+
47
+
clock-names:
48
+
items:
49
+
- const: apb_pclk
50
+
51
+
clocks:
52
+
items:
53
+
- description: APB register access clock
54
+
55
+
in-ports:
56
+
$ref: /schemas/graph.yaml#/properties/ports
57
+
58
+
patternProperties:
59
+
'^port(@[0-9a-f]{1,2})?$':
60
+
description: Input connections from CoreSight Trace Bus
61
+
$ref: /schemas/graph.yaml#/properties/port
62
+
63
+
out-ports:
64
+
$ref: /schemas/graph.yaml#/properties/ports
65
+
additionalProperties: false
66
+
67
+
properties:
68
+
port:
69
+
description:
70
+
Output connection to CoreSight Trace Bus
71
+
$ref: /schemas/graph.yaml#/properties/port
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- clocks
77
+
- clock-names
78
+
- in-ports
79
+
- out-ports
80
+
81
+
additionalProperties: false
82
+
83
+
examples:
84
+
- |
85
+
tn@109ab000 {
86
+
compatible = "qcom,coresight-tnoc", "arm,primecell";
87
+
reg = <0x109ab000 0x4200>;
88
+
89
+
clocks = <&aoss_qmp>;
90
+
clock-names = "apb_pclk";
91
+
92
+
in-ports {
93
+
#address-cells = <1>;
94
+
#size-cells = <0>;
95
+
96
+
port@0 {
97
+
reg = <0>;
98
+
99
+
tn_ag_in_tpdm_gcc: endpoint {
100
+
remote-endpoint = <&tpdm_gcc_out_tn_ag>;
101
+
};
102
+
};
103
+
};
104
+
105
+
out-ports {
106
+
port {
107
+
tn_ag_out_funnel_in1: endpoint {
108
+
remote-endpoint = <&funnel_in1_in_tn_ag>;
109
+
};
110
+
};
111
+
};
112
+
};
113
+
...
+4
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+4
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+12
drivers/hwtracing/coresight/Kconfig
+12
drivers/hwtracing/coresight/Kconfig
···
268
268
Enable Coresight unit tests. Only useful for development and not
269
269
intended for production.
270
270
271
+
config CORESIGHT_TNOC
272
+
tristate "Coresight Trace Network On Chip driver"
273
+
help
274
+
This driver provides support for Trace Network On Chip (TNOC) component.
275
+
TNOC is an interconnect used to collect traces from various subsystems
276
+
and transport to a coresight trace sink. It sits in the different
277
+
tiles of SOC and aggregates the trace local to the tile and transports
278
+
it another tile or to coresight trace sink eventually.
279
+
280
+
To compile this driver as a module, choose M here: the module will be
281
+
called coresight-tnoc.
282
+
271
283
endif
+1
drivers/hwtracing/coresight/Makefile
+1
drivers/hwtracing/coresight/Makefile
···
36
36
obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
37
37
obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
38
38
coresight-replicator.o
39
+
obj-$(CONFIG_CORESIGHT_TNOC) += coresight-tnoc.o
39
40
obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
40
41
coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
41
42
coresight-etm3x-sysfs.o
+25
-28
drivers/hwtracing/coresight/coresight-catu.c
+25
-28
drivers/hwtracing/coresight/coresight-catu.c
···
515
515
{
516
516
int ret = 0;
517
517
u32 dma_mask;
518
-
struct catu_drvdata *drvdata = dev_get_drvdata(dev);
518
+
struct catu_drvdata *drvdata;
519
519
struct coresight_desc catu_desc;
520
520
struct coresight_platform_data *pdata = NULL;
521
521
void __iomem *base;
522
+
523
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
524
+
if (!drvdata)
525
+
return -ENOMEM;
526
+
527
+
dev_set_drvdata(dev, drvdata);
528
+
529
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
530
+
if (ret)
531
+
return ret;
522
532
523
533
catu_desc.name = coresight_alloc_device_name(&catu_devs, dev);
524
534
if (!catu_desc.name)
···
586
576
587
577
static int catu_probe(struct amba_device *adev, const struct amba_id *id)
588
578
{
589
-
struct catu_drvdata *drvdata;
590
579
int ret;
591
580
592
-
drvdata = devm_kzalloc(&adev->dev, sizeof(*drvdata), GFP_KERNEL);
593
-
if (!drvdata)
594
-
return -ENOMEM;
595
-
596
-
amba_set_drvdata(adev, drvdata);
597
581
ret = __catu_probe(&adev->dev, &adev->res);
598
582
if (!ret)
599
583
pm_runtime_put(&adev->dev);
···
627
623
static int catu_platform_probe(struct platform_device *pdev)
628
624
{
629
625
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
630
-
struct catu_drvdata *drvdata;
631
626
int ret = 0;
632
-
633
-
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
634
-
if (!drvdata)
635
-
return -ENOMEM;
636
-
637
-
drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
638
-
if (IS_ERR(drvdata->pclk))
639
-
return -ENODEV;
640
627
641
628
pm_runtime_get_noresume(&pdev->dev);
642
629
pm_runtime_set_active(&pdev->dev);
643
630
pm_runtime_enable(&pdev->dev);
644
631
645
-
dev_set_drvdata(&pdev->dev, drvdata);
646
632
ret = __catu_probe(&pdev->dev, res);
647
633
pm_runtime_put(&pdev->dev);
648
-
if (ret) {
634
+
if (ret)
649
635
pm_runtime_disable(&pdev->dev);
650
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
651
-
clk_put(drvdata->pclk);
652
-
}
653
636
654
637
return ret;
655
638
}
···
650
659
651
660
__catu_remove(&pdev->dev);
652
661
pm_runtime_disable(&pdev->dev);
653
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
654
-
clk_put(drvdata->pclk);
655
662
}
656
663
657
664
#ifdef CONFIG_PM
···
657
668
{
658
669
struct catu_drvdata *drvdata = dev_get_drvdata(dev);
659
670
660
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
661
-
clk_disable_unprepare(drvdata->pclk);
671
+
clk_disable_unprepare(drvdata->atclk);
672
+
clk_disable_unprepare(drvdata->pclk);
673
+
662
674
return 0;
663
675
}
664
676
665
677
static int catu_runtime_resume(struct device *dev)
666
678
{
667
679
struct catu_drvdata *drvdata = dev_get_drvdata(dev);
680
+
int ret;
668
681
669
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
670
-
clk_prepare_enable(drvdata->pclk);
671
-
return 0;
682
+
ret = clk_prepare_enable(drvdata->pclk);
683
+
if (ret)
684
+
return ret;
685
+
686
+
ret = clk_prepare_enable(drvdata->atclk);
687
+
if (ret)
688
+
clk_disable_unprepare(drvdata->pclk);
689
+
690
+
return ret;
672
691
}
673
692
#endif
674
693
+1
drivers/hwtracing/coresight/coresight-catu.h
+1
drivers/hwtracing/coresight/coresight-catu.h
+52
-2
drivers/hwtracing/coresight/coresight-core.c
+52
-2
drivers/hwtracing/coresight/coresight-core.c
···
3
3
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4
4
*/
5
5
6
+
#include <linux/acpi.h>
7
+
#include <linux/bitfield.h>
6
8
#include <linux/build_bug.h>
7
9
#include <linux/kernel.h>
8
10
#include <linux/init.h>
···
1376
1374
goto out_unlock;
1377
1375
}
1378
1376
1379
-
if (csdev->type == CORESIGHT_DEV_TYPE_SINK ||
1380
-
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) {
1377
+
if ((csdev->type == CORESIGHT_DEV_TYPE_SINK ||
1378
+
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) &&
1379
+
sink_ops(csdev)->alloc_buffer) {
1381
1380
ret = etm_perf_add_symlink_sink(csdev);
1382
1381
1383
1382
if (ret) {
···
1700
1697
return trace_id;
1701
1698
}
1702
1699
EXPORT_SYMBOL_GPL(coresight_etm_get_trace_id);
1700
+
1701
+
/*
1702
+
* Attempt to find and enable programming clock (pclk) and trace clock (atclk)
1703
+
* for the given device.
1704
+
*
1705
+
* For ACPI devices, clocks are controlled by firmware, so bail out early in
1706
+
* this case. Also, skip enabling pclk if the clock is managed by the AMBA
1707
+
* bus driver instead.
1708
+
*
1709
+
* atclk is an optional clock, it will be only enabled when it is existed.
1710
+
* Otherwise, a NULL pointer will be returned to caller.
1711
+
*
1712
+
* Returns: '0' on Success; Error code otherwise.
1713
+
*/
1714
+
int coresight_get_enable_clocks(struct device *dev, struct clk **pclk,
1715
+
struct clk **atclk)
1716
+
{
1717
+
WARN_ON(!pclk);
1718
+
1719
+
if (has_acpi_companion(dev))
1720
+
return 0;
1721
+
1722
+
if (!dev_is_amba(dev)) {
1723
+
/*
1724
+
* "apb_pclk" is the default clock name for an Arm Primecell
1725
+
* peripheral, while "apb" is used only by the CTCU driver.
1726
+
*
1727
+
* For easier maintenance, CoreSight drivers should use
1728
+
* "apb_pclk" as the programming clock name.
1729
+
*/
1730
+
*pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
1731
+
if (!*pclk)
1732
+
*pclk = devm_clk_get_optional_enabled(dev, "apb");
1733
+
if (IS_ERR(*pclk))
1734
+
return PTR_ERR(*pclk);
1735
+
}
1736
+
1737
+
/* Initialization of atclk is skipped if it is a NULL pointer. */
1738
+
if (atclk) {
1739
+
*atclk = devm_clk_get_optional_enabled(dev, "atclk");
1740
+
if (IS_ERR(*atclk))
1741
+
return PTR_ERR(*atclk);
1742
+
}
1743
+
1744
+
return 0;
1745
+
}
1746
+
EXPORT_SYMBOL_GPL(coresight_get_enable_clocks);
1703
1747
1704
1748
MODULE_LICENSE("GPL v2");
1705
1749
MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
+14
-27
drivers/hwtracing/coresight/coresight-cpu-debug.c
+14
-27
drivers/hwtracing/coresight/coresight-cpu-debug.c
···
562
562
563
563
static int __debug_probe(struct device *dev, struct resource *res)
564
564
{
565
-
struct debug_drvdata *drvdata = dev_get_drvdata(dev);
565
+
struct debug_drvdata *drvdata;
566
566
void __iomem *base;
567
567
int ret;
568
+
569
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
570
+
if (!drvdata)
571
+
return -ENOMEM;
572
+
573
+
dev_set_drvdata(dev, drvdata);
574
+
575
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, NULL);
576
+
if (ret)
577
+
return ret;
568
578
569
579
drvdata->cpu = coresight_get_cpu(dev);
570
580
if (drvdata->cpu < 0)
···
635
625
636
626
static int debug_probe(struct amba_device *adev, const struct amba_id *id)
637
627
{
638
-
struct debug_drvdata *drvdata;
639
-
640
-
drvdata = devm_kzalloc(&adev->dev, sizeof(*drvdata), GFP_KERNEL);
641
-
if (!drvdata)
642
-
return -ENOMEM;
643
-
644
-
amba_set_drvdata(adev, drvdata);
645
628
return __debug_probe(&adev->dev, &adev->res);
646
629
}
647
630
···
693
690
static int debug_platform_probe(struct platform_device *pdev)
694
691
{
695
692
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
696
-
struct debug_drvdata *drvdata;
697
693
int ret = 0;
698
694
699
-
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
700
-
if (!drvdata)
701
-
return -ENOMEM;
702
-
703
-
drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
704
-
if (IS_ERR(drvdata->pclk))
705
-
return -ENODEV;
706
-
707
-
dev_set_drvdata(&pdev->dev, drvdata);
708
695
pm_runtime_get_noresume(&pdev->dev);
709
696
pm_runtime_set_active(&pdev->dev);
710
697
pm_runtime_enable(&pdev->dev);
···
703
710
if (ret) {
704
711
pm_runtime_put_noidle(&pdev->dev);
705
712
pm_runtime_disable(&pdev->dev);
706
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
707
-
clk_put(drvdata->pclk);
708
713
}
709
714
return ret;
710
715
}
···
716
725
717
726
__debug_remove(&pdev->dev);
718
727
pm_runtime_disable(&pdev->dev);
719
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
720
-
clk_put(drvdata->pclk);
721
728
}
722
729
723
730
#ifdef CONFIG_ACPI
···
731
742
{
732
743
struct debug_drvdata *drvdata = dev_get_drvdata(dev);
733
744
734
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
735
-
clk_disable_unprepare(drvdata->pclk);
745
+
clk_disable_unprepare(drvdata->pclk);
746
+
736
747
return 0;
737
748
}
738
749
···
740
751
{
741
752
struct debug_drvdata *drvdata = dev_get_drvdata(dev);
742
753
743
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
744
-
clk_prepare_enable(drvdata->pclk);
745
-
return 0;
754
+
return clk_prepare_enable(drvdata->pclk);
746
755
}
747
756
#endif
748
757
+7
-17
drivers/hwtracing/coresight/coresight-ctcu-core.c
+7
-17
drivers/hwtracing/coresight/coresight-ctcu-core.c
···
188
188
const struct ctcu_config *cfgs;
189
189
struct ctcu_drvdata *drvdata;
190
190
void __iomem *base;
191
-
int i;
191
+
int i, ret;
192
192
193
193
desc.name = coresight_alloc_device_name(&ctcu_devs, dev);
194
194
if (!desc.name)
···
207
207
if (IS_ERR(base))
208
208
return PTR_ERR(base);
209
209
210
-
drvdata->apb_clk = coresight_get_enable_apb_pclk(dev);
211
-
if (IS_ERR(drvdata->apb_clk))
212
-
return -ENODEV;
210
+
ret = coresight_get_enable_clocks(dev, &drvdata->apb_clk, NULL);
211
+
if (ret)
212
+
return ret;
213
213
214
214
cfgs = of_device_get_match_data(dev);
215
215
if (cfgs) {
···
233
233
desc.access = CSDEV_ACCESS_IOMEM(base);
234
234
235
235
drvdata->csdev = coresight_register(&desc);
236
-
if (IS_ERR(drvdata->csdev)) {
237
-
if (!IS_ERR_OR_NULL(drvdata->apb_clk))
238
-
clk_put(drvdata->apb_clk);
239
-
236
+
if (IS_ERR(drvdata->csdev))
240
237
return PTR_ERR(drvdata->csdev);
241
-
}
242
238
243
239
return 0;
244
240
}
···
271
275
272
276
ctcu_remove(pdev);
273
277
pm_runtime_disable(&pdev->dev);
274
-
if (!IS_ERR_OR_NULL(drvdata->apb_clk))
275
-
clk_put(drvdata->apb_clk);
276
278
}
277
279
278
280
#ifdef CONFIG_PM
···
278
284
{
279
285
struct ctcu_drvdata *drvdata = dev_get_drvdata(dev);
280
286
281
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->apb_clk))
282
-
clk_disable_unprepare(drvdata->apb_clk);
287
+
clk_disable_unprepare(drvdata->apb_clk);
283
288
284
289
return 0;
285
290
}
···
287
294
{
288
295
struct ctcu_drvdata *drvdata = dev_get_drvdata(dev);
289
296
290
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->apb_clk))
291
-
clk_prepare_enable(drvdata->apb_clk);
292
-
293
-
return 0;
297
+
return clk_prepare_enable(drvdata->apb_clk);
294
298
}
295
299
#endif
296
300
+6
-12
drivers/hwtracing/coresight/coresight-etb10.c
+6
-12
drivers/hwtracing/coresight/coresight-etb10.c
···
730
730
if (!drvdata)
731
731
return -ENOMEM;
732
732
733
-
drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
734
-
if (!IS_ERR(drvdata->atclk)) {
735
-
ret = clk_prepare_enable(drvdata->atclk);
736
-
if (ret)
737
-
return ret;
738
-
}
733
+
drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
734
+
if (IS_ERR(drvdata->atclk))
735
+
return PTR_ERR(drvdata->atclk);
736
+
739
737
dev_set_drvdata(dev, drvdata);
740
738
741
739
/* validity for the resource is already checked by the AMBA core */
···
809
811
{
810
812
struct etb_drvdata *drvdata = dev_get_drvdata(dev);
811
813
812
-
if (drvdata && !IS_ERR(drvdata->atclk))
813
-
clk_disable_unprepare(drvdata->atclk);
814
+
clk_disable_unprepare(drvdata->atclk);
814
815
815
816
return 0;
816
817
}
···
818
821
{
819
822
struct etb_drvdata *drvdata = dev_get_drvdata(dev);
820
823
821
-
if (drvdata && !IS_ERR(drvdata->atclk))
822
-
clk_prepare_enable(drvdata->atclk);
823
-
824
-
return 0;
824
+
return clk_prepare_enable(drvdata->atclk);
825
825
}
826
826
#endif
827
827
+2
-2
drivers/hwtracing/coresight/coresight-etm-perf.c
+2
-2
drivers/hwtracing/coresight/coresight-etm-perf.c
···
851
851
struct dev_ext_attribute *ea;
852
852
853
853
ea = container_of(dattr, struct dev_ext_attribute, attr);
854
-
return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var));
854
+
return scnprintf(buf, PAGE_SIZE, "0x%px\n", ea->var);
855
855
}
856
856
857
857
static struct dev_ext_attribute *
···
943
943
struct dev_ext_attribute *ea;
944
944
945
945
ea = container_of(dattr, struct dev_ext_attribute, attr);
946
-
return scnprintf(buf, PAGE_SIZE, "configid=0x%lx\n", (unsigned long)(ea->var));
946
+
return scnprintf(buf, PAGE_SIZE, "configid=0x%px\n", ea->var);
947
947
}
948
948
949
949
int etm_perf_add_symlink_cscfg(struct device *dev, struct cscfg_config_desc *config_desc)
+5
-12
drivers/hwtracing/coresight/coresight-etm3x-core.c
+5
-12
drivers/hwtracing/coresight/coresight-etm3x-core.c
···
832
832
833
833
spin_lock_init(&drvdata->spinlock);
834
834
835
-
drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
836
-
if (!IS_ERR(drvdata->atclk)) {
837
-
ret = clk_prepare_enable(drvdata->atclk);
838
-
if (ret)
839
-
return ret;
840
-
}
835
+
drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
836
+
if (IS_ERR(drvdata->atclk))
837
+
return PTR_ERR(drvdata->atclk);
841
838
842
839
drvdata->cpu = coresight_get_cpu(dev);
843
840
if (drvdata->cpu < 0)
···
925
928
{
926
929
struct etm_drvdata *drvdata = dev_get_drvdata(dev);
927
930
928
-
if (drvdata && !IS_ERR(drvdata->atclk))
929
-
clk_disable_unprepare(drvdata->atclk);
931
+
clk_disable_unprepare(drvdata->atclk);
930
932
931
933
return 0;
932
934
}
···
934
938
{
935
939
struct etm_drvdata *drvdata = dev_get_drvdata(dev);
936
940
937
-
if (drvdata && !IS_ERR(drvdata->atclk))
938
-
clk_prepare_enable(drvdata->atclk);
939
-
940
-
return 0;
941
+
return clk_prepare_enable(drvdata->atclk);
941
942
}
942
943
#endif
943
944
+26
-18
drivers/hwtracing/coresight/coresight-etm4x-core.c
+26
-18
drivers/hwtracing/coresight/coresight-etm4x-core.c
···
4
4
*/
5
5
6
6
#include <linux/acpi.h>
7
+
#include <linux/bitfield.h>
7
8
#include <linux/bitops.h>
8
9
#include <linux/kernel.h>
9
10
#include <linux/kvm_host.h>
···
529
528
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
530
529
etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
531
530
}
532
-
etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
531
+
if (drvdata->numextinsel)
532
+
etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
533
533
for (i = 0; i < drvdata->nr_cntr; i++) {
534
534
etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
535
535
etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
···
1425
1423
etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1426
1424
/* NUMEXTIN, bits[8:0] number of external inputs implemented */
1427
1425
drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1426
+
drvdata->numextinsel = FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5);
1428
1427
/* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1429
1428
drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1430
1429
/* ATBTRIG, bit[22] implementation can support ATB triggers? */
···
1855
1852
state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1856
1853
state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1857
1854
}
1858
-
state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1855
+
1856
+
if (drvdata->numextinsel)
1857
+
state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1859
1858
1860
1859
for (i = 0; i < drvdata->nr_cntr; i++) {
1861
1860
state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
···
1989
1984
etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1990
1985
etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1991
1986
}
1992
-
etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1987
+
if (drvdata->numextinsel)
1988
+
etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1993
1989
1994
1990
for (i = 0; i < drvdata->nr_cntr; i++) {
1995
1991
etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
···
2217
2211
struct csdev_access access = { 0 };
2218
2212
struct etm4_init_arg init_arg = { 0 };
2219
2213
struct etm4_init_arg *delayed;
2214
+
int ret;
2220
2215
2221
2216
if (WARN_ON(!drvdata))
2222
2217
return -ENOMEM;
2218
+
2219
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
2220
+
if (ret)
2221
+
return ret;
2223
2222
2224
2223
if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2225
2224
pm_save_enable = coresight_loses_context_with_cpu(dev) ?
···
2308
2297
if (!drvdata)
2309
2298
return -ENOMEM;
2310
2299
2311
-
drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2312
-
if (IS_ERR(drvdata->pclk))
2313
-
return -ENODEV;
2314
-
2315
2300
if (res) {
2316
2301
drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2317
-
if (IS_ERR(drvdata->base)) {
2318
-
clk_put(drvdata->pclk);
2302
+
if (IS_ERR(drvdata->base))
2319
2303
return PTR_ERR(drvdata->base);
2320
-
}
2321
2304
}
2322
2305
2323
2306
dev_set_drvdata(&pdev->dev, drvdata);
···
2418
2413
if (drvdata)
2419
2414
etm4_remove_dev(drvdata);
2420
2415
pm_runtime_disable(&pdev->dev);
2421
-
2422
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2423
-
clk_put(drvdata->pclk);
2424
2416
}
2425
2417
2426
2418
static const struct amba_id etm4_ids[] = {
···
2465
2463
{
2466
2464
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2467
2465
2468
-
if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2469
-
clk_disable_unprepare(drvdata->pclk);
2466
+
clk_disable_unprepare(drvdata->atclk);
2467
+
clk_disable_unprepare(drvdata->pclk);
2470
2468
2471
2469
return 0;
2472
2470
}
···
2474
2472
static int etm4_runtime_resume(struct device *dev)
2475
2473
{
2476
2474
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2475
+
int ret;
2477
2476
2478
-
if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2479
-
clk_prepare_enable(drvdata->pclk);
2477
+
ret = clk_prepare_enable(drvdata->pclk);
2478
+
if (ret)
2479
+
return ret;
2480
2480
2481
-
return 0;
2481
+
ret = clk_prepare_enable(drvdata->atclk);
2482
+
if (ret)
2483
+
clk_disable_unprepare(drvdata->pclk);
2484
+
2485
+
return ret;
2482
2486
}
2483
2487
#endif
2484
2488
+1
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+1
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+5
-1
drivers/hwtracing/coresight/coresight-etm4x.h
+5
-1
drivers/hwtracing/coresight/coresight-etm4x.h
···
162
162
#define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28)
163
163
164
164
#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0)
165
+
#define TRCIDR5_NUMEXTINSEL_MASK GENMASK(11, 9)
165
166
#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16)
166
167
#define TRCIDR5_ATBTRIG BIT(22)
167
168
#define TRCIDR5_LPOVERRIDE BIT(23)
···
920
919
921
920
/**
922
921
* struct etm4_drvdata - specifics associated to an ETM component
923
-
* @pclk APB clock if present, otherwise NULL
922
+
* @pclk: APB clock if present, otherwise NULL
923
+
* @atclk: Optional clock for the core parts of the ETMv4.
924
924
* @base: Memory mapped base address for this component.
925
925
* @csdev: Component vitals needed by the framework.
926
926
* @spinlock: Only one at a time pls.
···
990
988
*/
991
989
struct etmv4_drvdata {
992
990
struct clk *pclk;
991
+
struct clk *atclk;
993
992
void __iomem *base;
994
993
struct coresight_device *csdev;
995
994
raw_spinlock_t spinlock;
···
1002
999
u8 nr_cntr;
1003
1000
u8 nr_ext_inp;
1004
1001
u8 numcidc;
1002
+
u8 numextinsel;
1005
1003
u8 numvmidc;
1006
1004
u8 nrseqstate;
1007
1005
u8 nr_event;
+23
-43
drivers/hwtracing/coresight/coresight-funnel.c
+23
-43
drivers/hwtracing/coresight/coresight-funnel.c
···
213
213
214
214
static int funnel_probe(struct device *dev, struct resource *res)
215
215
{
216
-
int ret;
217
216
void __iomem *base;
218
217
struct coresight_platform_data *pdata = NULL;
219
218
struct funnel_drvdata *drvdata;
220
219
struct coresight_desc desc = { 0 };
220
+
int ret;
221
221
222
222
if (is_of_node(dev_fwnode(dev)) &&
223
223
of_device_is_compatible(dev->of_node, "arm,coresight-funnel"))
···
231
231
if (!drvdata)
232
232
return -ENOMEM;
233
233
234
-
drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
235
-
if (!IS_ERR(drvdata->atclk)) {
236
-
ret = clk_prepare_enable(drvdata->atclk);
237
-
if (ret)
238
-
return ret;
239
-
}
240
-
241
-
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
242
-
if (IS_ERR(drvdata->pclk))
243
-
return -ENODEV;
234
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
235
+
if (ret)
236
+
return ret;
244
237
245
238
/*
246
239
* Map the device base for dynamic-funnel, which has been
···
241
248
*/
242
249
if (res) {
243
250
base = devm_ioremap_resource(dev, res);
244
-
if (IS_ERR(base)) {
245
-
ret = PTR_ERR(base);
246
-
goto out_disable_clk;
247
-
}
251
+
if (IS_ERR(base))
252
+
return PTR_ERR(base);
248
253
drvdata->base = base;
249
254
desc.groups = coresight_funnel_groups;
250
255
desc.access = CSDEV_ACCESS_IOMEM(base);
···
252
261
dev_set_drvdata(dev, drvdata);
253
262
254
263
pdata = coresight_get_platform_data(dev);
255
-
if (IS_ERR(pdata)) {
256
-
ret = PTR_ERR(pdata);
257
-
goto out_disable_clk;
258
-
}
264
+
if (IS_ERR(pdata))
265
+
return PTR_ERR(pdata);
266
+
259
267
dev->platform_data = pdata;
260
268
261
269
raw_spin_lock_init(&drvdata->spinlock);
···
264
274
desc.pdata = pdata;
265
275
desc.dev = dev;
266
276
drvdata->csdev = coresight_register(&desc);
267
-
if (IS_ERR(drvdata->csdev)) {
268
-
ret = PTR_ERR(drvdata->csdev);
269
-
goto out_disable_clk;
270
-
}
277
+
if (IS_ERR(drvdata->csdev))
278
+
return PTR_ERR(drvdata->csdev);
271
279
272
-
ret = 0;
273
-
274
-
out_disable_clk:
275
-
if (ret && !IS_ERR_OR_NULL(drvdata->atclk))
276
-
clk_disable_unprepare(drvdata->atclk);
277
-
if (ret && !IS_ERR_OR_NULL(drvdata->pclk))
278
-
clk_disable_unprepare(drvdata->pclk);
279
-
return ret;
280
+
return 0;
280
281
}
281
282
282
283
static int funnel_remove(struct device *dev)
···
284
303
{
285
304
struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
286
305
287
-
if (drvdata && !IS_ERR(drvdata->atclk))
288
-
clk_disable_unprepare(drvdata->atclk);
289
-
290
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
291
-
clk_disable_unprepare(drvdata->pclk);
306
+
clk_disable_unprepare(drvdata->atclk);
307
+
clk_disable_unprepare(drvdata->pclk);
292
308
293
309
return 0;
294
310
}
···
293
315
static int funnel_runtime_resume(struct device *dev)
294
316
{
295
317
struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
318
+
int ret;
296
319
297
-
if (drvdata && !IS_ERR(drvdata->atclk))
298
-
clk_prepare_enable(drvdata->atclk);
320
+
ret = clk_prepare_enable(drvdata->pclk);
321
+
if (ret)
322
+
return ret;
299
323
300
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
301
-
clk_prepare_enable(drvdata->pclk);
302
-
return 0;
324
+
ret = clk_prepare_enable(drvdata->atclk);
325
+
if (ret)
326
+
clk_disable_unprepare(drvdata->pclk);
327
+
328
+
return ret;
303
329
}
304
330
#endif
305
331
···
337
355
338
356
funnel_remove(&pdev->dev);
339
357
pm_runtime_disable(&pdev->dev);
340
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
341
-
clk_put(drvdata->pclk);
342
358
}
343
359
344
360
static const struct of_device_id funnel_match[] = {
+22
-41
drivers/hwtracing/coresight/coresight-replicator.c
+22
-41
drivers/hwtracing/coresight/coresight-replicator.c
···
219
219
220
220
static int replicator_probe(struct device *dev, struct resource *res)
221
221
{
222
-
int ret = 0;
223
222
struct coresight_platform_data *pdata = NULL;
224
223
struct replicator_drvdata *drvdata;
225
224
struct coresight_desc desc = { 0 };
226
225
void __iomem *base;
226
+
int ret;
227
227
228
228
if (is_of_node(dev_fwnode(dev)) &&
229
229
of_device_is_compatible(dev->of_node, "arm,coresight-replicator"))
···
238
238
if (!drvdata)
239
239
return -ENOMEM;
240
240
241
-
drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
242
-
if (!IS_ERR(drvdata->atclk)) {
243
-
ret = clk_prepare_enable(drvdata->atclk);
244
-
if (ret)
245
-
return ret;
246
-
}
247
-
248
-
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
249
-
if (IS_ERR(drvdata->pclk))
250
-
return -ENODEV;
241
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
242
+
if (ret)
243
+
return ret;
251
244
252
245
/*
253
246
* Map the device base for dynamic-replicator, which has been
···
248
255
*/
249
256
if (res) {
250
257
base = devm_ioremap_resource(dev, res);
251
-
if (IS_ERR(base)) {
252
-
ret = PTR_ERR(base);
253
-
goto out_disable_clk;
254
-
}
258
+
if (IS_ERR(base))
259
+
return PTR_ERR(base);
255
260
drvdata->base = base;
256
261
desc.groups = replicator_groups;
257
262
desc.access = CSDEV_ACCESS_IOMEM(base);
···
263
272
dev_set_drvdata(dev, drvdata);
264
273
265
274
pdata = coresight_get_platform_data(dev);
266
-
if (IS_ERR(pdata)) {
267
-
ret = PTR_ERR(pdata);
268
-
goto out_disable_clk;
269
-
}
275
+
if (IS_ERR(pdata))
276
+
return PTR_ERR(pdata);
270
277
dev->platform_data = pdata;
271
278
272
279
raw_spin_lock_init(&drvdata->spinlock);
···
275
286
desc.dev = dev;
276
287
277
288
drvdata->csdev = coresight_register(&desc);
278
-
if (IS_ERR(drvdata->csdev)) {
279
-
ret = PTR_ERR(drvdata->csdev);
280
-
goto out_disable_clk;
281
-
}
289
+
if (IS_ERR(drvdata->csdev))
290
+
return PTR_ERR(drvdata->csdev);
282
291
283
292
replicator_reset(drvdata);
284
-
285
-
out_disable_clk:
286
-
if (ret && !IS_ERR_OR_NULL(drvdata->atclk))
287
-
clk_disable_unprepare(drvdata->atclk);
288
-
if (ret && !IS_ERR_OR_NULL(drvdata->pclk))
289
-
clk_disable_unprepare(drvdata->pclk);
290
-
return ret;
293
+
return 0;
291
294
}
292
295
293
296
static int replicator_remove(struct device *dev)
···
316
335
317
336
replicator_remove(&pdev->dev);
318
337
pm_runtime_disable(&pdev->dev);
319
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
320
-
clk_put(drvdata->pclk);
321
338
}
322
339
323
340
#ifdef CONFIG_PM
···
323
344
{
324
345
struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
325
346
326
-
if (drvdata && !IS_ERR(drvdata->atclk))
327
-
clk_disable_unprepare(drvdata->atclk);
347
+
clk_disable_unprepare(drvdata->atclk);
348
+
clk_disable_unprepare(drvdata->pclk);
328
349
329
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
330
-
clk_disable_unprepare(drvdata->pclk);
331
350
return 0;
332
351
}
333
352
334
353
static int replicator_runtime_resume(struct device *dev)
335
354
{
336
355
struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
356
+
int ret;
337
357
338
-
if (drvdata && !IS_ERR(drvdata->atclk))
339
-
clk_prepare_enable(drvdata->atclk);
358
+
ret = clk_prepare_enable(drvdata->pclk);
359
+
if (ret)
360
+
return ret;
340
361
341
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
342
-
clk_prepare_enable(drvdata->pclk);
343
-
return 0;
362
+
ret = clk_prepare_enable(drvdata->atclk);
363
+
if (ret)
364
+
clk_disable_unprepare(drvdata->pclk);
365
+
366
+
return ret;
344
367
}
345
368
#endif
346
369
+18
-24
drivers/hwtracing/coresight/coresight-stm.c
+18
-24
drivers/hwtracing/coresight/coresight-stm.c
···
342
342
{
343
343
struct stm_drvdata *drvdata = container_of(stm_data,
344
344
struct stm_drvdata, stm);
345
-
if (!drvdata || !drvdata->csdev)
345
+
if (!drvdata->csdev)
346
346
return -EINVAL;
347
347
348
348
return coresight_enable_sysfs(drvdata->csdev);
···
353
353
{
354
354
struct stm_drvdata *drvdata = container_of(stm_data,
355
355
struct stm_drvdata, stm);
356
-
if (!drvdata || !drvdata->csdev)
356
+
if (!drvdata->csdev)
357
357
return;
358
358
359
359
coresight_disable_sysfs(drvdata->csdev);
···
384
384
{
385
385
struct stm_drvdata *drvdata = container_of(stm_data,
386
386
struct stm_drvdata, stm);
387
-
if (!(drvdata && coresight_get_mode(drvdata->csdev)))
387
+
if (!coresight_get_mode(drvdata->csdev))
388
388
return -EINVAL;
389
389
390
390
if (channel >= drvdata->numsp)
···
419
419
struct stm_drvdata, stm);
420
420
unsigned int stm_flags;
421
421
422
-
if (!(drvdata && coresight_get_mode(drvdata->csdev)))
422
+
if (!coresight_get_mode(drvdata->csdev))
423
423
return -EACCES;
424
424
425
425
if (channel >= drvdata->numsp)
···
842
842
if (!drvdata)
843
843
return -ENOMEM;
844
844
845
-
drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
846
-
if (!IS_ERR(drvdata->atclk)) {
847
-
ret = clk_prepare_enable(drvdata->atclk);
848
-
if (ret)
849
-
return ret;
850
-
}
845
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
846
+
if (ret)
847
+
return ret;
851
848
852
-
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
853
-
if (IS_ERR(drvdata->pclk))
854
-
return -ENODEV;
855
849
dev_set_drvdata(dev, drvdata);
856
850
857
851
base = devm_ioremap_resource(dev, res);
···
957
963
{
958
964
struct stm_drvdata *drvdata = dev_get_drvdata(dev);
959
965
960
-
if (drvdata && !IS_ERR(drvdata->atclk))
961
-
clk_disable_unprepare(drvdata->atclk);
966
+
clk_disable_unprepare(drvdata->atclk);
967
+
clk_disable_unprepare(drvdata->pclk);
962
968
963
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
964
-
clk_disable_unprepare(drvdata->pclk);
965
969
return 0;
966
970
}
967
971
968
972
static int stm_runtime_resume(struct device *dev)
969
973
{
970
974
struct stm_drvdata *drvdata = dev_get_drvdata(dev);
975
+
int ret;
971
976
972
-
if (drvdata && !IS_ERR(drvdata->atclk))
973
-
clk_prepare_enable(drvdata->atclk);
977
+
ret = clk_prepare_enable(drvdata->pclk);
978
+
if (ret)
979
+
return ret;
974
980
975
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
976
-
clk_prepare_enable(drvdata->pclk);
977
-
return 0;
981
+
ret = clk_prepare_enable(drvdata->atclk);
982
+
if (ret)
983
+
clk_disable_unprepare(drvdata->pclk);
984
+
985
+
return ret;
978
986
}
979
987
#endif
980
988
···
1029
1033
1030
1034
__stm_remove(&pdev->dev);
1031
1035
pm_runtime_disable(&pdev->dev);
1032
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
1033
-
clk_put(drvdata->pclk);
1034
1036
}
1035
1037
1036
1038
#ifdef CONFIG_ACPI
+1
-1
drivers/hwtracing/coresight/coresight-syscfg.c
+1
-1
drivers/hwtracing/coresight/coresight-syscfg.c
···
395
395
if (list_empty(&csdev->config_csdev_list))
396
396
return;
397
397
398
-
guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock);
398
+
guard(raw_spinlock_irqsave)(&csdev->cscfg_csdev_lock);
399
399
400
400
list_for_each_entry_safe(config_csdev, tmp, &csdev->config_csdev_list, node) {
401
401
if (config_csdev->config_desc->load_owner == load_owner)
+69
-2
drivers/hwtracing/coresight/coresight-sysfs.c
+69
-2
drivers/hwtracing/coresight/coresight-sysfs.c
···
7
7
#include <linux/device.h>
8
8
#include <linux/idr.h>
9
9
#include <linux/kernel.h>
10
+
#include <linux/property.h>
10
11
11
12
#include "coresight-priv.h"
12
13
#include "coresight-trace-id.h"
···
372
371
}
373
372
static DEVICE_ATTR_RW(enable_source);
374
373
374
+
static ssize_t label_show(struct device *dev,
375
+
struct device_attribute *attr, char *buf)
376
+
{
377
+
378
+
const char *str;
379
+
int ret;
380
+
381
+
ret = fwnode_property_read_string(dev_fwnode(dev), "label", &str);
382
+
if (ret == 0)
383
+
return sysfs_emit(buf, "%s\n", str);
384
+
else
385
+
return ret;
386
+
}
387
+
static DEVICE_ATTR_RO(label);
388
+
389
+
static umode_t label_is_visible(struct kobject *kobj,
390
+
struct attribute *attr, int n)
391
+
{
392
+
struct device *dev = kobj_to_dev(kobj);
393
+
394
+
if (attr == &dev_attr_label.attr) {
395
+
if (fwnode_property_present(dev_fwnode(dev), "label"))
396
+
return attr->mode;
397
+
else
398
+
return 0;
399
+
}
400
+
401
+
return attr->mode;
402
+
}
403
+
375
404
static struct attribute *coresight_sink_attrs[] = {
376
405
&dev_attr_enable_sink.attr,
406
+
&dev_attr_label.attr,
377
407
NULL,
378
408
};
379
-
ATTRIBUTE_GROUPS(coresight_sink);
409
+
410
+
static struct attribute_group coresight_sink_group = {
411
+
.attrs = coresight_sink_attrs,
412
+
.is_visible = label_is_visible,
413
+
};
414
+
__ATTRIBUTE_GROUPS(coresight_sink);
380
415
381
416
static struct attribute *coresight_source_attrs[] = {
382
417
&dev_attr_enable_source.attr,
418
+
&dev_attr_label.attr,
383
419
NULL,
384
420
};
385
-
ATTRIBUTE_GROUPS(coresight_source);
421
+
422
+
static struct attribute_group coresight_source_group = {
423
+
.attrs = coresight_source_attrs,
424
+
.is_visible = label_is_visible,
425
+
};
426
+
__ATTRIBUTE_GROUPS(coresight_source);
427
+
428
+
static struct attribute *coresight_link_attrs[] = {
429
+
&dev_attr_label.attr,
430
+
NULL,
431
+
};
432
+
433
+
static struct attribute_group coresight_link_group = {
434
+
.attrs = coresight_link_attrs,
435
+
.is_visible = label_is_visible,
436
+
};
437
+
__ATTRIBUTE_GROUPS(coresight_link);
438
+
439
+
static struct attribute *coresight_helper_attrs[] = {
440
+
&dev_attr_label.attr,
441
+
NULL,
442
+
};
443
+
444
+
static struct attribute_group coresight_helper_group = {
445
+
.attrs = coresight_helper_attrs,
446
+
.is_visible = label_is_visible,
447
+
};
448
+
__ATTRIBUTE_GROUPS(coresight_helper);
386
449
387
450
const struct device_type coresight_dev_type[] = {
388
451
[CORESIGHT_DEV_TYPE_SINK] = {
···
455
390
},
456
391
[CORESIGHT_DEV_TYPE_LINK] = {
457
392
.name = "link",
393
+
.groups = coresight_link_groups,
458
394
},
459
395
[CORESIGHT_DEV_TYPE_LINKSINK] = {
460
396
.name = "linksink",
···
467
401
},
468
402
[CORESIGHT_DEV_TYPE_HELPER] = {
469
403
.name = "helper",
404
+
.groups = coresight_helper_groups,
470
405
}
471
406
};
472
407
/* Ensure the enum matches the names and groups */
+30
-40
drivers/hwtracing/coresight/coresight-tmc-core.c
+30
-40
drivers/hwtracing/coresight/coresight-tmc-core.c
···
24
24
#include <linux/pm_runtime.h>
25
25
#include <linux/of.h>
26
26
#include <linux/of_address.h>
27
+
#include <linux/of_reserved_mem.h>
27
28
#include <linux/coresight.h>
28
29
#include <linux/amba/bus.h>
29
30
#include <linux/platform_device.h>
···
635
634
const char *name,
636
635
struct resource *res)
637
636
{
638
-
int index, rc = -ENODEV;
639
-
struct device_node *node;
637
+
int rc = -ENODEV;
640
638
641
-
if (!is_of_node(dev->fwnode))
642
-
return -ENODEV;
643
-
644
-
index = of_property_match_string(dev->of_node, "memory-region-names",
645
-
name);
646
-
if (index < 0)
639
+
rc = of_reserved_mem_region_to_resource_byname(dev->of_node, name, res);
640
+
if (rc < 0)
647
641
return rc;
648
642
649
-
node = of_parse_phandle(dev->of_node, "memory-region", index);
650
-
if (!node)
651
-
return rc;
652
-
653
-
if (!of_address_to_resource(node, 0, res) &&
654
-
res->start != 0 && resource_size(res) != 0)
655
-
rc = 0;
656
-
of_node_put(node);
643
+
if (res->start == 0 || resource_size(res) == 0)
644
+
rc = -ENODEV;
657
645
658
646
return rc;
659
647
}
···
775
785
u32 devid;
776
786
void __iomem *base;
777
787
struct coresight_platform_data *pdata = NULL;
778
-
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
788
+
struct tmc_drvdata *drvdata;
779
789
struct coresight_desc desc = { 0 };
780
790
struct coresight_dev_list *dev_list = NULL;
791
+
792
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
793
+
if (!drvdata)
794
+
return -ENOMEM;
795
+
796
+
dev_set_drvdata(dev, drvdata);
797
+
798
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
799
+
if (ret)
800
+
return ret;
781
801
782
802
ret = -ENOMEM;
783
803
···
894
894
895
895
static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
896
896
{
897
-
struct tmc_drvdata *drvdata;
898
897
int ret;
899
898
900
-
drvdata = devm_kzalloc(&adev->dev, sizeof(*drvdata), GFP_KERNEL);
901
-
if (!drvdata)
902
-
return -ENOMEM;
903
-
904
-
amba_set_drvdata(adev, drvdata);
905
899
ret = __tmc_probe(&adev->dev, &adev->res);
906
900
if (!ret)
907
901
pm_runtime_put(&adev->dev);
···
972
978
static int tmc_platform_probe(struct platform_device *pdev)
973
979
{
974
980
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975
-
struct tmc_drvdata *drvdata;
976
981
int ret = 0;
977
982
978
-
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
979
-
if (!drvdata)
980
-
return -ENOMEM;
981
-
982
-
drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
983
-
if (IS_ERR(drvdata->pclk))
984
-
return -ENODEV;
985
-
986
-
dev_set_drvdata(&pdev->dev, drvdata);
987
983
pm_runtime_get_noresume(&pdev->dev);
988
984
pm_runtime_set_active(&pdev->dev);
989
985
pm_runtime_enable(&pdev->dev);
···
995
1011
996
1012
__tmc_remove(&pdev->dev);
997
1013
pm_runtime_disable(&pdev->dev);
998
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
999
-
clk_put(drvdata->pclk);
1000
1014
}
1001
1015
1002
1016
#ifdef CONFIG_PM
···
1002
1020
{
1003
1021
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
1004
1022
1005
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
1006
-
clk_disable_unprepare(drvdata->pclk);
1023
+
clk_disable_unprepare(drvdata->atclk);
1024
+
clk_disable_unprepare(drvdata->pclk);
1025
+
1007
1026
return 0;
1008
1027
}
1009
1028
1010
1029
static int tmc_runtime_resume(struct device *dev)
1011
1030
{
1012
1031
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
1032
+
int ret;
1013
1033
1014
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
1015
-
clk_prepare_enable(drvdata->pclk);
1016
-
return 0;
1034
+
ret = clk_prepare_enable(drvdata->pclk);
1035
+
if (ret)
1036
+
return ret;
1037
+
1038
+
ret = clk_prepare_enable(drvdata->atclk);
1039
+
if (ret)
1040
+
clk_disable_unprepare(drvdata->pclk);
1041
+
1042
+
return ret;
1017
1043
}
1018
1044
#endif
1019
1045
+2
drivers/hwtracing/coresight/coresight-tmc.h
+2
drivers/hwtracing/coresight/coresight-tmc.h
···
210
210
211
211
/**
212
212
* struct tmc_drvdata - specifics associated to an TMC component
213
+
* @atclk: optional clock for the core parts of the TMC.
213
214
* @pclk: APB clock if present, otherwise NULL
214
215
* @base: memory mapped base address for this component.
215
216
* @csdev: component vitals needed by the framework.
···
245
244
* Used by ETR/ETF.
246
245
*/
247
246
struct tmc_drvdata {
247
+
struct clk *atclk;
248
248
struct clk *pclk;
249
249
void __iomem *base;
250
250
struct coresight_device *csdev;
+246
drivers/hwtracing/coresight/coresight-tnoc.c
+246
drivers/hwtracing/coresight/coresight-tnoc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/amba/bus.h>
7
+
#include <linux/coresight.h>
8
+
#include <linux/device.h>
9
+
#include <linux/io.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
15
+
#include "coresight-priv.h"
16
+
#include "coresight-trace-id.h"
17
+
18
+
#define TRACE_NOC_CTRL 0x008
19
+
#define TRACE_NOC_XLD 0x010
20
+
#define TRACE_NOC_FREQVAL 0x018
21
+
#define TRACE_NOC_SYNCR 0x020
22
+
23
+
/* Enable generation of output ATB traffic.*/
24
+
#define TRACE_NOC_CTRL_PORTEN BIT(0)
25
+
/* Sets the type of issued ATB FLAG packets.*/
26
+
#define TRACE_NOC_CTRL_FLAGTYPE BIT(7)
27
+
/* Sets the type of issued ATB FREQ packet*/
28
+
#define TRACE_NOC_CTRL_FREQTYPE BIT(8)
29
+
30
+
#define TRACE_NOC_SYNC_INTERVAL 0xFFFF
31
+
32
+
/*
33
+
* struct trace_noc_drvdata - specifics associated to a trace noc component
34
+
* @base: memory mapped base address for this component.
35
+
* @dev: device node for trace_noc_drvdata.
36
+
* @csdev: component vitals needed by the framework.
37
+
* @spinlock: serialize enable/disable operation.
38
+
* @atid: id for the trace packet.
39
+
*/
40
+
struct trace_noc_drvdata {
41
+
void __iomem *base;
42
+
struct device *dev;
43
+
struct coresight_device *csdev;
44
+
spinlock_t spinlock;
45
+
u32 atid;
46
+
};
47
+
48
+
DEFINE_CORESIGHT_DEVLIST(trace_noc_devs, "traceNoc");
49
+
50
+
static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata)
51
+
{
52
+
u32 val;
53
+
54
+
/* Set ATID */
55
+
writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD);
56
+
57
+
/* Set the data word count between 'SYNC' packets */
58
+
writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR);
59
+
60
+
/* Set the Control register:
61
+
* - Set the FLAG packets to 'FLAG' packets
62
+
* - Set the FREQ packets to 'FREQ_TS' packets
63
+
* - Enable generation of output ATB traffic
64
+
*/
65
+
66
+
val = readl_relaxed(drvdata->base + TRACE_NOC_CTRL);
67
+
68
+
val &= ~TRACE_NOC_CTRL_FLAGTYPE;
69
+
val |= TRACE_NOC_CTRL_FREQTYPE;
70
+
val |= TRACE_NOC_CTRL_PORTEN;
71
+
72
+
writel(val, drvdata->base + TRACE_NOC_CTRL);
73
+
}
74
+
75
+
static int trace_noc_enable(struct coresight_device *csdev, struct coresight_connection *inport,
76
+
struct coresight_connection *outport)
77
+
{
78
+
struct trace_noc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
79
+
80
+
scoped_guard(spinlock, &drvdata->spinlock) {
81
+
if (csdev->refcnt == 0)
82
+
trace_noc_enable_hw(drvdata);
83
+
84
+
csdev->refcnt++;
85
+
}
86
+
87
+
dev_dbg(drvdata->dev, "Trace NOC is enabled\n");
88
+
return 0;
89
+
}
90
+
91
+
static void trace_noc_disable(struct coresight_device *csdev, struct coresight_connection *inport,
92
+
struct coresight_connection *outport)
93
+
{
94
+
struct trace_noc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
95
+
96
+
scoped_guard(spinlock, &drvdata->spinlock) {
97
+
if (--csdev->refcnt == 0)
98
+
writel(0x0, drvdata->base + TRACE_NOC_CTRL);
99
+
}
100
+
dev_dbg(drvdata->dev, "Trace NOC is disabled\n");
101
+
}
102
+
103
+
static int trace_noc_id(struct coresight_device *csdev, __maybe_unused enum cs_mode mode,
104
+
__maybe_unused struct coresight_device *sink)
105
+
{
106
+
struct trace_noc_drvdata *drvdata;
107
+
108
+
drvdata = dev_get_drvdata(csdev->dev.parent);
109
+
110
+
return drvdata->atid;
111
+
}
112
+
113
+
static const struct coresight_ops_link trace_noc_link_ops = {
114
+
.enable = trace_noc_enable,
115
+
.disable = trace_noc_disable,
116
+
};
117
+
118
+
static const struct coresight_ops trace_noc_cs_ops = {
119
+
.trace_id = trace_noc_id,
120
+
.link_ops = &trace_noc_link_ops,
121
+
};
122
+
123
+
static int trace_noc_init_default_data(struct trace_noc_drvdata *drvdata)
124
+
{
125
+
int atid;
126
+
127
+
atid = coresight_trace_id_get_system_id();
128
+
if (atid < 0)
129
+
return atid;
130
+
131
+
drvdata->atid = atid;
132
+
133
+
return 0;
134
+
}
135
+
136
+
static ssize_t traceid_show(struct device *dev,
137
+
struct device_attribute *attr, char *buf)
138
+
{
139
+
unsigned long val;
140
+
struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent);
141
+
142
+
val = drvdata->atid;
143
+
return sprintf(buf, "%#lx\n", val);
144
+
}
145
+
static DEVICE_ATTR_RO(traceid);
146
+
147
+
static struct attribute *coresight_tnoc_attrs[] = {
148
+
&dev_attr_traceid.attr,
149
+
NULL,
150
+
};
151
+
152
+
static const struct attribute_group coresight_tnoc_group = {
153
+
.attrs = coresight_tnoc_attrs,
154
+
};
155
+
156
+
static const struct attribute_group *coresight_tnoc_groups[] = {
157
+
&coresight_tnoc_group,
158
+
NULL,
159
+
};
160
+
161
+
static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id)
162
+
{
163
+
struct device *dev = &adev->dev;
164
+
struct coresight_platform_data *pdata;
165
+
struct trace_noc_drvdata *drvdata;
166
+
struct coresight_desc desc = { 0 };
167
+
int ret;
168
+
169
+
desc.name = coresight_alloc_device_name(&trace_noc_devs, dev);
170
+
if (!desc.name)
171
+
return -ENOMEM;
172
+
173
+
pdata = coresight_get_platform_data(dev);
174
+
if (IS_ERR(pdata))
175
+
return PTR_ERR(pdata);
176
+
adev->dev.platform_data = pdata;
177
+
178
+
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
179
+
if (!drvdata)
180
+
return -ENOMEM;
181
+
182
+
drvdata->dev = &adev->dev;
183
+
dev_set_drvdata(dev, drvdata);
184
+
185
+
drvdata->base = devm_ioremap_resource(dev, &adev->res);
186
+
if (IS_ERR(drvdata->base))
187
+
return PTR_ERR(drvdata->base);
188
+
189
+
spin_lock_init(&drvdata->spinlock);
190
+
191
+
ret = trace_noc_init_default_data(drvdata);
192
+
if (ret)
193
+
return ret;
194
+
195
+
desc.ops = &trace_noc_cs_ops;
196
+
desc.type = CORESIGHT_DEV_TYPE_LINK;
197
+
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
198
+
desc.pdata = adev->dev.platform_data;
199
+
desc.dev = &adev->dev;
200
+
desc.access = CSDEV_ACCESS_IOMEM(drvdata->base);
201
+
desc.groups = coresight_tnoc_groups;
202
+
drvdata->csdev = coresight_register(&desc);
203
+
if (IS_ERR(drvdata->csdev)) {
204
+
coresight_trace_id_put_system_id(drvdata->atid);
205
+
return PTR_ERR(drvdata->csdev);
206
+
}
207
+
pm_runtime_put(&adev->dev);
208
+
209
+
return 0;
210
+
}
211
+
212
+
static void trace_noc_remove(struct amba_device *adev)
213
+
{
214
+
struct trace_noc_drvdata *drvdata = dev_get_drvdata(&adev->dev);
215
+
216
+
coresight_unregister(drvdata->csdev);
217
+
coresight_trace_id_put_system_id(drvdata->atid);
218
+
}
219
+
220
+
static struct amba_id trace_noc_ids[] = {
221
+
{
222
+
.id = 0x000f0c00,
223
+
.mask = 0x00ffff00,
224
+
},
225
+
{
226
+
.id = 0x001f0c00,
227
+
.mask = 0x00ffff00,
228
+
},
229
+
{},
230
+
};
231
+
MODULE_DEVICE_TABLE(amba, trace_noc_ids);
232
+
233
+
static struct amba_driver trace_noc_driver = {
234
+
.drv = {
235
+
.name = "coresight-trace-noc",
236
+
.suppress_bind_attrs = true,
237
+
},
238
+
.probe = trace_noc_probe,
239
+
.remove = trace_noc_remove,
240
+
.id_table = trace_noc_ids,
241
+
};
242
+
243
+
module_amba_driver(trace_noc_driver);
244
+
245
+
MODULE_LICENSE("GPL");
246
+
MODULE_DESCRIPTION("Trace NOC driver");
+3
drivers/hwtracing/coresight/coresight-tpda.c
+3
drivers/hwtracing/coresight/coresight-tpda.c
···
71
71
if (tpdm_data->dsb) {
72
72
rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent),
73
73
"qcom,dsb-element-bits", &drvdata->dsb_esize);
74
+
if (rc)
75
+
goto out;
74
76
}
75
77
76
78
if (tpdm_data->cmb) {
···
80
78
"qcom,cmb-element-bits", &drvdata->cmb_esize);
81
79
}
82
80
81
+
out:
83
82
if (rc)
84
83
dev_warn_once(&csdev->dev,
85
84
"Failed to read TPDM Element size: %d\n", rc);
+15
-21
drivers/hwtracing/coresight/coresight-tpiu.c
+15
-21
drivers/hwtracing/coresight/coresight-tpiu.c
···
128
128
129
129
static int __tpiu_probe(struct device *dev, struct resource *res)
130
130
{
131
-
int ret;
132
131
void __iomem *base;
133
132
struct coresight_platform_data *pdata = NULL;
134
133
struct tpiu_drvdata *drvdata;
135
134
struct coresight_desc desc = { 0 };
135
+
int ret;
136
136
137
137
desc.name = coresight_alloc_device_name(&tpiu_devs, dev);
138
138
if (!desc.name)
···
144
144
145
145
spin_lock_init(&drvdata->spinlock);
146
146
147
-
drvdata->atclk = devm_clk_get(dev, "atclk"); /* optional */
148
-
if (!IS_ERR(drvdata->atclk)) {
149
-
ret = clk_prepare_enable(drvdata->atclk);
150
-
if (ret)
151
-
return ret;
152
-
}
147
+
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, &drvdata->atclk);
148
+
if (ret)
149
+
return ret;
153
150
154
-
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
155
-
if (IS_ERR(drvdata->pclk))
156
-
return -ENODEV;
157
151
dev_set_drvdata(dev, drvdata);
158
152
159
153
/* Validity for the resource is already checked by the AMBA core */
···
206
212
{
207
213
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
208
214
209
-
if (drvdata && !IS_ERR(drvdata->atclk))
210
-
clk_disable_unprepare(drvdata->atclk);
215
+
clk_disable_unprepare(drvdata->atclk);
216
+
clk_disable_unprepare(drvdata->pclk);
211
217
212
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
213
-
clk_disable_unprepare(drvdata->pclk);
214
218
return 0;
215
219
}
216
220
217
221
static int tpiu_runtime_resume(struct device *dev)
218
222
{
219
223
struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
224
+
int ret;
220
225
221
-
if (drvdata && !IS_ERR(drvdata->atclk))
222
-
clk_prepare_enable(drvdata->atclk);
226
+
ret = clk_prepare_enable(drvdata->pclk);
227
+
if (ret)
228
+
return ret;
223
229
224
-
if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
225
-
clk_prepare_enable(drvdata->pclk);
226
-
return 0;
230
+
ret = clk_prepare_enable(drvdata->atclk);
231
+
if (ret)
232
+
clk_disable_unprepare(drvdata->pclk);
233
+
234
+
return ret;
227
235
}
228
236
#endif
229
237
···
289
293
290
294
__tpiu_remove(&pdev->dev);
291
295
pm_runtime_disable(&pdev->dev);
292
-
if (!IS_ERR_OR_NULL(drvdata->pclk))
293
-
clk_put(drvdata->pclk);
294
296
}
295
297
296
298
#ifdef CONFIG_ACPI
+5
-4
drivers/hwtracing/coresight/coresight-trbe.c
+5
-4
drivers/hwtracing/coresight/coresight-trbe.c
···
257
257
static void trbe_reset_local(struct trbe_cpudata *cpudata)
258
258
{
259
259
write_sysreg_s(0, SYS_TRBLIMITR_EL1);
260
+
isb();
260
261
trbe_drain_buffer();
261
262
write_sysreg_s(0, SYS_TRBPTR_EL1);
262
263
write_sysreg_s(0, SYS_TRBBASER_EL1);
···
748
747
749
748
buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, trbe_alloc_node(event));
750
749
if (!buf)
751
-
return ERR_PTR(-ENOMEM);
750
+
return NULL;
752
751
753
752
pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
754
753
if (!pglist) {
755
754
kfree(buf);
756
-
return ERR_PTR(-ENOMEM);
755
+
return NULL;
757
756
}
758
757
759
758
for (i = 0; i < nr_pages; i++)
···
763
762
if (!buf->trbe_base) {
764
763
kfree(pglist);
765
764
kfree(buf);
766
-
return ERR_PTR(-ENOMEM);
765
+
return NULL;
767
766
}
768
767
buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
769
768
buf->trbe_write = buf->trbe_base;
···
1280
1279
* into the device for that purpose.
1281
1280
*/
1282
1281
desc.pdata = devm_kzalloc(dev, sizeof(*desc.pdata), GFP_KERNEL);
1283
-
if (IS_ERR(desc.pdata))
1282
+
if (!desc.pdata)
1284
1283
goto cpu_clear;
1285
1284
1286
1285
desc.type = CORESIGHT_DEV_TYPE_SINK;
+1
drivers/hwtracing/coresight/ultrasoc-smb.h
+1
drivers/hwtracing/coresight/ultrasoc-smb.h
+2
-29
include/linux/coresight.h
+2
-29
include/linux/coresight.h
···
474
474
return cid == CORESIGHT_CID;
475
475
}
476
476
477
-
/*
478
-
* Attempt to find and enable "APB clock" for the given device
479
-
*
480
-
* Returns:
481
-
*
482
-
* clk - Clock is found and enabled
483
-
* NULL - clock is not found
484
-
* ERROR - Clock is found but failed to enable
485
-
*/
486
-
static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev)
487
-
{
488
-
struct clk *pclk;
489
-
int ret;
490
-
491
-
pclk = clk_get(dev, "apb_pclk");
492
-
if (IS_ERR(pclk)) {
493
-
pclk = clk_get(dev, "apb");
494
-
if (IS_ERR(pclk))
495
-
return NULL;
496
-
}
497
-
498
-
ret = clk_prepare_enable(pclk);
499
-
if (ret) {
500
-
clk_put(pclk);
501
-
return ERR_PTR(ret);
502
-
}
503
-
return pclk;
504
-
}
505
-
506
477
#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4))
507
478
508
479
static inline u32 coresight_get_pid(struct csdev_access *csa)
···
704
733
struct platform_driver *pdev_drv);
705
734
int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
706
735
struct coresight_device *sink);
736
+
int coresight_get_enable_clocks(struct device *dev, struct clk **pclk,
737
+
struct clk **atclk);
707
738
#endif /* _LINUX_COREISGHT_H */