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clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver

mtk_clk_simple_probe was added by Chun-Jie to simply common flow
of MediaTek clock drivers and ChenYu enhanced the error path of
mtk_clk_simple_probe and added mtk_clk_simple_remove.

Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other
MediaTek clock drivers as well.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220922091841.4099-6-miles.chen@mediatek.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>

authored by

Miles Chen and committed by
Chen-Yu Tsai
a481c6c7 dc6fdd8a

+39 -69
+13 -23
drivers/clk/mediatek/clk-mt6797-img.c
··· 32 32 GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0), 33 33 }; 34 34 35 - static const struct of_device_id of_match_clk_mt6797_img[] = { 36 - { .compatible = "mediatek,mt6797-imgsys", }, 37 - {} 35 + static const struct mtk_clk_desc img_desc = { 36 + .clks = img_clks, 37 + .num_clks = ARRAY_SIZE(img_clks), 38 38 }; 39 39 40 - static int clk_mt6797_img_probe(struct platform_device *pdev) 41 - { 42 - struct clk_hw_onecell_data *clk_data; 43 - int r; 44 - struct device_node *node = pdev->dev.of_node; 45 - 46 - clk_data = mtk_alloc_clk_data(CLK_IMG_NR); 47 - 48 - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), 49 - clk_data); 50 - 51 - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 52 - if (r) 53 - dev_err(&pdev->dev, 54 - "could not register clock provider: %s: %d\n", 55 - pdev->name, r); 56 - 57 - return r; 58 - } 40 + static const struct of_device_id of_match_clk_mt6797_img[] = { 41 + { 42 + .compatible = "mediatek,mt6797-imgsys", 43 + .data = &img_desc, 44 + }, { 45 + /* sentinel */ 46 + } 47 + }; 59 48 60 49 static struct platform_driver clk_mt6797_img_drv = { 61 - .probe = clk_mt6797_img_probe, 50 + .probe = mtk_clk_simple_probe, 51 + .remove = mtk_clk_simple_remove, 62 52 .driver = { 63 53 .name = "clk-mt6797-img", 64 54 .of_match_table = of_match_clk_mt6797_img,
+13 -23
drivers/clk/mediatek/clk-mt6797-vdec.c
··· 49 49 GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0), 50 50 }; 51 51 52 - static const struct of_device_id of_match_clk_mt6797_vdec[] = { 53 - { .compatible = "mediatek,mt6797-vdecsys", }, 54 - {} 52 + static const struct mtk_clk_desc vdec_desc = { 53 + .clks = vdec_clks, 54 + .num_clks = ARRAY_SIZE(vdec_clks), 55 55 }; 56 56 57 - static int clk_mt6797_vdec_probe(struct platform_device *pdev) 58 - { 59 - struct clk_hw_onecell_data *clk_data; 60 - int r; 61 - struct device_node *node = pdev->dev.of_node; 62 - 63 - clk_data = mtk_alloc_clk_data(CLK_VDEC_NR); 64 - 65 - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), 66 - clk_data); 67 - 68 - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 69 - if (r) 70 - dev_err(&pdev->dev, 71 - "could not register clock provider: %s: %d\n", 72 - pdev->name, r); 73 - 74 - return r; 75 - } 57 + static const struct of_device_id of_match_clk_mt6797_vdec[] = { 58 + { 59 + .compatible = "mediatek,mt6797-vdecsys", 60 + .data = &vdec_desc, 61 + }, { 62 + /* sentinel */ 63 + } 64 + }; 76 65 77 66 static struct platform_driver clk_mt6797_vdec_drv = { 78 - .probe = clk_mt6797_vdec_probe, 67 + .probe = mtk_clk_simple_probe, 68 + .remove = mtk_clk_simple_remove, 79 69 .driver = { 80 70 .name = "clk-mt6797-vdec", 81 71 .of_match_table = of_match_clk_mt6797_vdec,
+13 -23
drivers/clk/mediatek/clk-mt6797-venc.c
··· 34 34 GATE_VENC(CLK_VENC_3, "venc_3", "venc_sel", 12), 35 35 }; 36 36 37 - static const struct of_device_id of_match_clk_mt6797_venc[] = { 38 - { .compatible = "mediatek,mt6797-vencsys", }, 39 - {} 37 + static const struct mtk_clk_desc venc_desc = { 38 + .clks = venc_clks, 39 + .num_clks = ARRAY_SIZE(venc_clks), 40 40 }; 41 41 42 - static int clk_mt6797_venc_probe(struct platform_device *pdev) 43 - { 44 - struct clk_hw_onecell_data *clk_data; 45 - int r; 46 - struct device_node *node = pdev->dev.of_node; 47 - 48 - clk_data = mtk_alloc_clk_data(CLK_VENC_NR); 49 - 50 - mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), 51 - clk_data); 52 - 53 - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 54 - if (r) 55 - dev_err(&pdev->dev, 56 - "could not register clock provider: %s: %d\n", 57 - pdev->name, r); 58 - 59 - return r; 60 - } 42 + static const struct of_device_id of_match_clk_mt6797_venc[] = { 43 + { 44 + .compatible = "mediatek,mt6797-vencsys", 45 + .data = &venc_desc, 46 + }, { 47 + /* sentinel */ 48 + } 49 + }; 61 50 62 51 static struct platform_driver clk_mt6797_venc_drv = { 63 - .probe = clk_mt6797_venc_probe, 52 + .probe = mtk_clk_simple_probe, 53 + .remove = mtk_clk_simple_remove, 64 54 .driver = { 65 55 .name = "clk-mt6797-venc", 66 56 .of_match_table = of_match_clk_mt6797_venc,