Merge branch 'enable-multiple-irq-lines-support-in-airoha_eth-driver'

+108 -49

drivers/net/ethernet/airoha/airoha_eth.c

··· 34 34 return val; 35 35 } 36 36 37 - static void airoha_qdma_set_irqmask(struct airoha_qdma *qdma, int index, 38 - u32 clear, u32 set) 37 + static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 38 + int index, u32 clear, u32 set) 39 39 { 40 + struct airoha_qdma *qdma = irq_bank->qdma; 41 + int bank = irq_bank - &qdma->irq_banks[0]; 40 42 unsigned long flags; 41 43 42 - if (WARN_ON_ONCE(index >= ARRAY_SIZE(qdma->irqmask))) 44 + if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 43 45 return; 44 46 45 - spin_lock_irqsave(&qdma->irq_lock, flags); 47 + spin_lock_irqsave(&irq_bank->irq_lock, flags); 46 48 47 - qdma->irqmask[index] &= ~clear; 48 - qdma->irqmask[index] |= set; 49 - airoha_qdma_wr(qdma, REG_INT_ENABLE(index), qdma->irqmask[index]); 49 + irq_bank->irqmask[index] &= ~clear; 50 + irq_bank->irqmask[index] |= set; 51 + airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 52 + irq_bank->irqmask[index]); 50 53 /* Read irq_enable register in order to guarantee the update above 51 54 * completes in the spinlock critical section. 52 55 */ 53 - airoha_qdma_rr(qdma, REG_INT_ENABLE(index)); 56 + airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 54 57 55 - spin_unlock_irqrestore(&qdma->irq_lock, flags); 58 + spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 56 59 } 57 60 58 - static void airoha_qdma_irq_enable(struct airoha_qdma *qdma, int index, 59 - u32 mask) 61 + static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 62 + int index, u32 mask) 60 63 { 61 - airoha_qdma_set_irqmask(qdma, index, 0, mask); 64 + airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 62 65 } 63 66 64 - static void airoha_qdma_irq_disable(struct airoha_qdma *qdma, int index, 65 - u32 mask) 67 + static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 68 + int index, u32 mask) 66 69 { 67 - airoha_qdma_set_irqmask(qdma, index, mask, 0); 70 + airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 68 71 } 69 72 70 73 static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port) ··· 742 739 done += cur; 743 740 } while (cur && done < budget); 744 741 745 - if (done < budget && napi_complete(napi)) 746 - airoha_qdma_irq_enable(q->qdma, QDMA_INT_REG_IDX1, 747 - RX_DONE_INT_MASK); 742 + if (done < budget && napi_complete(napi)) { 743 + struct airoha_qdma *qdma = q->qdma; 744 + int i, qid = q - &qdma->q_rx[0]; 745 + int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 746 + : QDMA_INT_REG_IDX2; 747 + 748 + for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 749 + if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 750 + continue; 751 + 752 + airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 753 + BIT(qid % RX_DONE_HIGH_OFFSET)); 754 + } 755 + } 748 756 749 757 return done; 750 758 } ··· 958 944 } 959 945 960 946 if (done < budget && napi_complete(napi)) 961 - airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX0, 947 + airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 962 948 TX_DONE_INT_MASK(id)); 963 949 964 950 return done; ··· 1188 1174 { 1189 1175 int i; 1190 1176 1191 - /* clear pending irqs */ 1192 - for (i = 0; i < ARRAY_SIZE(qdma->irqmask); i++) 1177 + for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1178 + /* clear pending irqs */ 1193 1179 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1194 - 1195 - /* setup irqs */ 1196 - airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX0, INT_IDX0_MASK); 1197 - airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX1, INT_IDX1_MASK); 1198 - airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX4, INT_IDX4_MASK); 1180 + /* setup rx irqs */ 1181 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1182 + INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1183 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1184 + INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1185 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1186 + INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1187 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1188 + INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1189 + } 1190 + /* setup tx irqs */ 1191 + airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1192 + TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1193 + airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1194 + TX_COHERENT_HIGH_INT_MASK); 1199 1195 1200 1196 /* setup irq binding */ 1201 1197 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { ··· 1250 1226 1251 1227 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1252 1228 { 1253 - struct airoha_qdma *qdma = dev_instance; 1254 - u32 intr[ARRAY_SIZE(qdma->irqmask)]; 1229 + struct airoha_irq_bank *irq_bank = dev_instance; 1230 + struct airoha_qdma *qdma = irq_bank->qdma; 1231 + u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1232 + u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1255 1233 int i; 1256 1234 1257 - for (i = 0; i < ARRAY_SIZE(qdma->irqmask); i++) { 1235 + for (i = 0; i < ARRAY_SIZE(intr); i++) { 1258 1236 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1259 - intr[i] &= qdma->irqmask[i]; 1237 + intr[i] &= irq_bank->irqmask[i]; 1260 1238 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1261 1239 } 1262 1240 1263 1241 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1264 1242 return IRQ_NONE; 1265 1243 1266 - if (intr[1] & RX_DONE_INT_MASK) { 1267 - airoha_qdma_irq_disable(qdma, QDMA_INT_REG_IDX1, 1268 - RX_DONE_INT_MASK); 1244 + rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1245 + if (rx_intr1) { 1246 + airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1247 + rx_intr_mask |= rx_intr1; 1248 + } 1269 1249 1270 - for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1271 - if (!qdma->q_rx[i].ndesc) 1272 - continue; 1250 + rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1251 + if (rx_intr2) { 1252 + airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1253 + rx_intr_mask |= (rx_intr2 << 16); 1254 + } 1273 1255 1274 - if (intr[1] & BIT(i)) 1275 - napi_schedule(&qdma->q_rx[i].napi); 1276 - } 1256 + for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1257 + if (!qdma->q_rx[i].ndesc) 1258 + continue; 1259 + 1260 + if (rx_intr_mask & BIT(i)) 1261 + napi_schedule(&qdma->q_rx[i].napi); 1277 1262 } 1278 1263 1279 1264 if (intr[0] & INT_TX_MASK) { ··· 1290 1257 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1291 1258 continue; 1292 1259 1293 - airoha_qdma_irq_disable(qdma, QDMA_INT_REG_IDX0, 1260 + airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1294 1261 TX_DONE_INT_MASK(i)); 1295 1262 napi_schedule(&qdma->q_tx_irq[i].napi); 1296 1263 } 1297 1264 } 1298 1265 1299 1266 return IRQ_HANDLED; 1267 + } 1268 + 1269 + static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1270 + struct airoha_qdma *qdma) 1271 + { 1272 + struct airoha_eth *eth = qdma->eth; 1273 + int i, id = qdma - &eth->qdma[0]; 1274 + 1275 + for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1276 + struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1277 + int err, irq_index = 4 * id + i; 1278 + const char *name; 1279 + 1280 + spin_lock_init(&irq_bank->irq_lock); 1281 + irq_bank->qdma = qdma; 1282 + 1283 + irq_bank->irq = platform_get_irq(pdev, irq_index); 1284 + if (irq_bank->irq < 0) 1285 + return irq_bank->irq; 1286 + 1287 + name = devm_kasprintf(eth->dev, GFP_KERNEL, 1288 + KBUILD_MODNAME ".%d", irq_index); 1289 + if (!name) 1290 + return -ENOMEM; 1291 + 1292 + err = devm_request_irq(eth->dev, irq_bank->irq, 1293 + airoha_irq_handler, IRQF_SHARED, name, 1294 + irq_bank); 1295 + if (err) 1296 + return err; 1297 + } 1298 + 1299 + return 0; 1300 1300 } 1301 1301 1302 1302 static int airoha_qdma_init(struct platform_device *pdev, ··· 1339 1273 int err, id = qdma - &eth->qdma[0]; 1340 1274 const char *res; 1341 1275 1342 - spin_lock_init(&qdma->irq_lock); 1343 1276 qdma->eth = eth; 1344 - 1345 1277 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1346 1278 if (!res) 1347 1279 return -ENOMEM; ··· 1349 1285 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1350 1286 "failed to iomap qdma%d regs\n", id); 1351 1287 1352 - qdma->irq = platform_get_irq(pdev, 4 * id); 1353 - if (qdma->irq < 0) 1354 - return qdma->irq; 1355 - 1356 - err = devm_request_irq(eth->dev, qdma->irq, airoha_irq_handler, 1357 - IRQF_SHARED, KBUILD_MODNAME, qdma); 1288 + err = airoha_qdma_init_irq_banks(pdev, qdma); 1358 1289 if (err) 1359 1290 return err; 1360 1291 ··· 2843 2784 dev->features |= dev->hw_features; 2844 2785 dev->vlan_features = dev->hw_features; 2845 2786 dev->dev.of_node = np; 2846 - dev->irq = qdma->irq; 2787 + dev->irq = qdma->irq_banks[0].irq; 2847 2788 SET_NETDEV_DEV(dev, eth->dev); 2848 2789 2849 2790 /* reserve hw queues for HTB offloading */

+21 -3

drivers/net/ethernet/airoha/airoha_eth.h

··· 17 17 18 18 #define AIROHA_MAX_NUM_GDM_PORTS 4 19 19 #define AIROHA_MAX_NUM_QDMA 2 20 + #define AIROHA_MAX_NUM_IRQ_BANKS 4 20 21 #define AIROHA_MAX_DSA_PORTS 7 21 22 #define AIROHA_MAX_NUM_RSTS 3 22 23 #define AIROHA_MAX_NUM_XSI_RSTS 5 ··· 453 452 unsigned long cookie; 454 453 }; 455 454 456 - struct airoha_qdma { 457 - struct airoha_eth *eth; 458 - void __iomem *regs; 455 + /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 456 + #define RX_IRQ0_BANK_PIN_MASK 0x839f 457 + #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 458 + #define RX_IRQ2_BANK_PIN_MASK 0x20 459 + #define RX_IRQ3_BANK_PIN_MASK 0x40 460 + #define RX_IRQ_BANK_PIN_MASK(_n) \ 461 + (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 462 + ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 463 + ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 464 + RX_IRQ0_BANK_PIN_MASK) 465 + 466 + struct airoha_irq_bank { 467 + struct airoha_qdma *qdma; 459 468 460 469 /* protect concurrent irqmask accesses */ 461 470 spinlock_t irq_lock; 462 471 u32 irqmask[QDMA_INT_REG_MAX]; 463 472 int irq; 473 + }; 474 + 475 + struct airoha_qdma { 476 + struct airoha_eth *eth; 477 + void __iomem *regs; 464 478 465 479 atomic_t users; 480 + 481 + struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 466 482 467 483 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 468 484

+154 -42

drivers/net/ethernet/airoha/airoha_regs.h

··· 423 423 ((_n) == 2) ? 0x0720 : \ 424 424 ((_n) == 1) ? 0x0024 : 0x0020) 425 425 426 - #define REG_INT_ENABLE(_n) \ 427 - (((_n) == 4) ? 0x0750 : \ 428 - ((_n) == 3) ? 0x0744 : \ 429 - ((_n) == 2) ? 0x0740 : \ 430 - ((_n) == 1) ? 0x002c : 0x0028) 426 + #define REG_INT_ENABLE(_b, _n) \ 427 + (((_n) == 4) ? 0x0750 + ((_b) << 5) : \ 428 + ((_n) == 3) ? 0x0744 + ((_b) << 5) : \ 429 + ((_n) == 2) ? 0x0740 + ((_b) << 5) : \ 430 + ((_n) == 1) ? 0x002c + ((_b) << 3) : \ 431 + 0x0028 + ((_b) << 3)) 431 432 432 433 /* QDMA_CSR_INT_ENABLE1 */ 433 434 #define RX15_COHERENT_INT_MASK BIT(31) ··· 463 462 #define IRQ0_FULL_INT_MASK BIT(1) 464 463 #define IRQ0_INT_MASK BIT(0) 465 464 465 + #define RX_COHERENT_LOW_INT_MASK \ 466 + (RX15_COHERENT_INT_MASK | RX14_COHERENT_INT_MASK | \ 467 + RX13_COHERENT_INT_MASK | RX12_COHERENT_INT_MASK | \ 468 + RX11_COHERENT_INT_MASK | RX10_COHERENT_INT_MASK | \ 469 + RX9_COHERENT_INT_MASK | RX8_COHERENT_INT_MASK | \ 470 + RX7_COHERENT_INT_MASK | RX6_COHERENT_INT_MASK | \ 471 + RX5_COHERENT_INT_MASK | RX4_COHERENT_INT_MASK | \ 472 + RX3_COHERENT_INT_MASK | RX2_COHERENT_INT_MASK | \ 473 + RX1_COHERENT_INT_MASK | RX0_COHERENT_INT_MASK) 474 + 475 + #define RX_COHERENT_LOW_OFFSET __ffs(RX_COHERENT_LOW_INT_MASK) 476 + #define INT_RX0_MASK(_n) \ 477 + (((_n) << RX_COHERENT_LOW_OFFSET) & RX_COHERENT_LOW_INT_MASK) 478 + 479 + #define TX_COHERENT_LOW_INT_MASK \ 480 + (TX7_COHERENT_INT_MASK | TX6_COHERENT_INT_MASK | \ 481 + TX5_COHERENT_INT_MASK | TX4_COHERENT_INT_MASK | \ 482 + TX3_COHERENT_INT_MASK | TX2_COHERENT_INT_MASK | \ 483 + TX1_COHERENT_INT_MASK | TX0_COHERENT_INT_MASK) 484 + 466 485 #define TX_DONE_INT_MASK(_n) \ 467 486 ((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \ 468 487 : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK) ··· 490 469 #define INT_TX_MASK \ 491 470 (IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \ 492 471 IRQ0_INT_MASK | IRQ0_FULL_INT_MASK) 493 - 494 - #define INT_IDX0_MASK \ 495 - (TX0_COHERENT_INT_MASK | TX1_COHERENT_INT_MASK | \ 496 - TX2_COHERENT_INT_MASK | TX3_COHERENT_INT_MASK | \ 497 - TX4_COHERENT_INT_MASK | TX5_COHERENT_INT_MASK | \ 498 - TX6_COHERENT_INT_MASK | TX7_COHERENT_INT_MASK | \ 499 - RX0_COHERENT_INT_MASK | RX1_COHERENT_INT_MASK | \ 500 - RX2_COHERENT_INT_MASK | RX3_COHERENT_INT_MASK | \ 501 - RX4_COHERENT_INT_MASK | RX7_COHERENT_INT_MASK | \ 502 - RX8_COHERENT_INT_MASK | RX9_COHERENT_INT_MASK | \ 503 - RX15_COHERENT_INT_MASK | INT_TX_MASK) 504 472 505 473 /* QDMA_CSR_INT_ENABLE2 */ 506 474 #define RX15_NO_CPU_DSCP_INT_MASK BIT(31) ··· 525 515 #define RX1_DONE_INT_MASK BIT(1) 526 516 #define RX0_DONE_INT_MASK BIT(0) 527 517 528 - #define RX_DONE_INT_MASK \ 529 - (RX0_DONE_INT_MASK | RX1_DONE_INT_MASK | \ 530 - RX2_DONE_INT_MASK | RX3_DONE_INT_MASK | \ 531 - RX4_DONE_INT_MASK | RX7_DONE_INT_MASK | \ 532 - RX8_DONE_INT_MASK | RX9_DONE_INT_MASK | \ 533 - RX15_DONE_INT_MASK) 534 - #define INT_IDX1_MASK \ 535 - (RX_DONE_INT_MASK | \ 536 - RX0_NO_CPU_DSCP_INT_MASK | RX1_NO_CPU_DSCP_INT_MASK | \ 537 - RX2_NO_CPU_DSCP_INT_MASK | RX3_NO_CPU_DSCP_INT_MASK | \ 538 - RX4_NO_CPU_DSCP_INT_MASK | RX7_NO_CPU_DSCP_INT_MASK | \ 539 - RX8_NO_CPU_DSCP_INT_MASK | RX9_NO_CPU_DSCP_INT_MASK | \ 540 - RX15_NO_CPU_DSCP_INT_MASK) 518 + #define RX_NO_CPU_DSCP_LOW_INT_MASK \ 519 + (RX15_NO_CPU_DSCP_INT_MASK | RX14_NO_CPU_DSCP_INT_MASK | \ 520 + RX13_NO_CPU_DSCP_INT_MASK | RX12_NO_CPU_DSCP_INT_MASK | \ 521 + RX11_NO_CPU_DSCP_INT_MASK | RX10_NO_CPU_DSCP_INT_MASK | \ 522 + RX9_NO_CPU_DSCP_INT_MASK | RX8_NO_CPU_DSCP_INT_MASK | \ 523 + RX7_NO_CPU_DSCP_INT_MASK | RX6_NO_CPU_DSCP_INT_MASK | \ 524 + RX5_NO_CPU_DSCP_INT_MASK | RX4_NO_CPU_DSCP_INT_MASK | \ 525 + RX3_NO_CPU_DSCP_INT_MASK | RX2_NO_CPU_DSCP_INT_MASK | \ 526 + RX1_NO_CPU_DSCP_INT_MASK | RX0_NO_CPU_DSCP_INT_MASK) 527 + 528 + #define RX_DONE_LOW_INT_MASK \ 529 + (RX15_DONE_INT_MASK | RX14_DONE_INT_MASK | \ 530 + RX13_DONE_INT_MASK | RX12_DONE_INT_MASK | \ 531 + RX11_DONE_INT_MASK | RX10_DONE_INT_MASK | \ 532 + RX9_DONE_INT_MASK | RX8_DONE_INT_MASK | \ 533 + RX7_DONE_INT_MASK | RX6_DONE_INT_MASK | \ 534 + RX5_DONE_INT_MASK | RX4_DONE_INT_MASK | \ 535 + RX3_DONE_INT_MASK | RX2_DONE_INT_MASK | \ 536 + RX1_DONE_INT_MASK | RX0_DONE_INT_MASK) 537 + 538 + #define RX_NO_CPU_DSCP_LOW_OFFSET __ffs(RX_NO_CPU_DSCP_LOW_INT_MASK) 539 + #define INT_RX1_MASK(_n) \ 540 + ((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) | \ 541 + (RX_DONE_LOW_INT_MASK & (_n))) 542 + 543 + /* QDMA_CSR_INT_ENABLE3 */ 544 + #define RX31_NO_CPU_DSCP_INT_MASK BIT(31) 545 + #define RX30_NO_CPU_DSCP_INT_MASK BIT(30) 546 + #define RX29_NO_CPU_DSCP_INT_MASK BIT(29) 547 + #define RX28_NO_CPU_DSCP_INT_MASK BIT(28) 548 + #define RX27_NO_CPU_DSCP_INT_MASK BIT(27) 549 + #define RX26_NO_CPU_DSCP_INT_MASK BIT(26) 550 + #define RX25_NO_CPU_DSCP_INT_MASK BIT(25) 551 + #define RX24_NO_CPU_DSCP_INT_MASK BIT(24) 552 + #define RX23_NO_CPU_DSCP_INT_MASK BIT(23) 553 + #define RX22_NO_CPU_DSCP_INT_MASK BIT(22) 554 + #define RX21_NO_CPU_DSCP_INT_MASK BIT(21) 555 + #define RX20_NO_CPU_DSCP_INT_MASK BIT(20) 556 + #define RX19_NO_CPU_DSCP_INT_MASK BIT(19) 557 + #define RX18_NO_CPU_DSCP_INT_MASK BIT(18) 558 + #define RX17_NO_CPU_DSCP_INT_MASK BIT(17) 559 + #define RX16_NO_CPU_DSCP_INT_MASK BIT(16) 560 + #define RX31_DONE_INT_MASK BIT(15) 561 + #define RX30_DONE_INT_MASK BIT(14) 562 + #define RX29_DONE_INT_MASK BIT(13) 563 + #define RX28_DONE_INT_MASK BIT(12) 564 + #define RX27_DONE_INT_MASK BIT(11) 565 + #define RX26_DONE_INT_MASK BIT(10) 566 + #define RX25_DONE_INT_MASK BIT(9) 567 + #define RX24_DONE_INT_MASK BIT(8) 568 + #define RX23_DONE_INT_MASK BIT(7) 569 + #define RX22_DONE_INT_MASK BIT(6) 570 + #define RX21_DONE_INT_MASK BIT(5) 571 + #define RX20_DONE_INT_MASK BIT(4) 572 + #define RX19_DONE_INT_MASK BIT(3) 573 + #define RX18_DONE_INT_MASK BIT(2) 574 + #define RX17_DONE_INT_MASK BIT(1) 575 + #define RX16_DONE_INT_MASK BIT(0) 576 + 577 + #define RX_NO_CPU_DSCP_HIGH_INT_MASK \ 578 + (RX31_NO_CPU_DSCP_INT_MASK | RX30_NO_CPU_DSCP_INT_MASK | \ 579 + RX29_NO_CPU_DSCP_INT_MASK | RX28_NO_CPU_DSCP_INT_MASK | \ 580 + RX27_NO_CPU_DSCP_INT_MASK | RX26_NO_CPU_DSCP_INT_MASK | \ 581 + RX25_NO_CPU_DSCP_INT_MASK | RX24_NO_CPU_DSCP_INT_MASK | \ 582 + RX23_NO_CPU_DSCP_INT_MASK | RX22_NO_CPU_DSCP_INT_MASK | \ 583 + RX21_NO_CPU_DSCP_INT_MASK | RX20_NO_CPU_DSCP_INT_MASK | \ 584 + RX19_NO_CPU_DSCP_INT_MASK | RX18_NO_CPU_DSCP_INT_MASK | \ 585 + RX17_NO_CPU_DSCP_INT_MASK | RX16_NO_CPU_DSCP_INT_MASK) 586 + 587 + #define RX_DONE_HIGH_INT_MASK \ 588 + (RX31_DONE_INT_MASK | RX30_DONE_INT_MASK | \ 589 + RX29_DONE_INT_MASK | RX28_DONE_INT_MASK | \ 590 + RX27_DONE_INT_MASK | RX26_DONE_INT_MASK | \ 591 + RX25_DONE_INT_MASK | RX24_DONE_INT_MASK | \ 592 + RX23_DONE_INT_MASK | RX22_DONE_INT_MASK | \ 593 + RX21_DONE_INT_MASK | RX20_DONE_INT_MASK | \ 594 + RX19_DONE_INT_MASK | RX18_DONE_INT_MASK | \ 595 + RX17_DONE_INT_MASK | RX16_DONE_INT_MASK) 596 + 597 + #define RX_DONE_INT_MASK (RX_DONE_HIGH_INT_MASK | RX_DONE_LOW_INT_MASK) 598 + #define RX_DONE_HIGH_OFFSET fls(RX_DONE_HIGH_INT_MASK) 599 + 600 + #define INT_RX2_MASK(_n) \ 601 + ((RX_NO_CPU_DSCP_HIGH_INT_MASK & (_n)) | \ 602 + (((_n) >> RX_DONE_HIGH_OFFSET) & RX_DONE_HIGH_INT_MASK)) 603 + 604 + /* QDMA_CSR_INT_ENABLE4 */ 605 + #define RX31_COHERENT_INT_MASK BIT(31) 606 + #define RX30_COHERENT_INT_MASK BIT(30) 607 + #define RX29_COHERENT_INT_MASK BIT(29) 608 + #define RX28_COHERENT_INT_MASK BIT(28) 609 + #define RX27_COHERENT_INT_MASK BIT(27) 610 + #define RX26_COHERENT_INT_MASK BIT(26) 611 + #define RX25_COHERENT_INT_MASK BIT(25) 612 + #define RX24_COHERENT_INT_MASK BIT(24) 613 + #define RX23_COHERENT_INT_MASK BIT(23) 614 + #define RX22_COHERENT_INT_MASK BIT(22) 615 + #define RX21_COHERENT_INT_MASK BIT(21) 616 + #define RX20_COHERENT_INT_MASK BIT(20) 617 + #define RX19_COHERENT_INT_MASK BIT(19) 618 + #define RX18_COHERENT_INT_MASK BIT(18) 619 + #define RX17_COHERENT_INT_MASK BIT(17) 620 + #define RX16_COHERENT_INT_MASK BIT(16) 621 + 622 + #define RX_COHERENT_HIGH_INT_MASK \ 623 + (RX31_COHERENT_INT_MASK | RX30_COHERENT_INT_MASK | \ 624 + RX29_COHERENT_INT_MASK | RX28_COHERENT_INT_MASK | \ 625 + RX27_COHERENT_INT_MASK | RX26_COHERENT_INT_MASK | \ 626 + RX25_COHERENT_INT_MASK | RX24_COHERENT_INT_MASK | \ 627 + RX23_COHERENT_INT_MASK | RX22_COHERENT_INT_MASK | \ 628 + RX21_COHERENT_INT_MASK | RX20_COHERENT_INT_MASK | \ 629 + RX19_COHERENT_INT_MASK | RX18_COHERENT_INT_MASK | \ 630 + RX17_COHERENT_INT_MASK | RX16_COHERENT_INT_MASK) 631 + 632 + #define INT_RX3_MASK(_n) (RX_COHERENT_HIGH_INT_MASK & (_n)) 541 633 542 634 /* QDMA_CSR_INT_ENABLE5 */ 543 635 #define TX31_COHERENT_INT_MASK BIT(31) ··· 667 555 #define TX9_COHERENT_INT_MASK BIT(9) 668 556 #define TX8_COHERENT_INT_MASK BIT(8) 669 557 670 - #define INT_IDX4_MASK \ 671 - (TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK | \ 672 - TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK | \ 673 - TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK | \ 674 - TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK | \ 675 - TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK | \ 676 - TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK | \ 677 - TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK | \ 678 - TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK | \ 679 - TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK | \ 680 - TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK | \ 681 - TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK | \ 682 - TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK) 558 + #define TX_COHERENT_HIGH_INT_MASK \ 559 + (TX31_COHERENT_INT_MASK | TX30_COHERENT_INT_MASK | \ 560 + TX29_COHERENT_INT_MASK | TX28_COHERENT_INT_MASK | \ 561 + TX27_COHERENT_INT_MASK | TX26_COHERENT_INT_MASK | \ 562 + TX25_COHERENT_INT_MASK | TX24_COHERENT_INT_MASK | \ 563 + TX23_COHERENT_INT_MASK | TX22_COHERENT_INT_MASK | \ 564 + TX21_COHERENT_INT_MASK | TX20_COHERENT_INT_MASK | \ 565 + TX19_COHERENT_INT_MASK | TX18_COHERENT_INT_MASK | \ 566 + TX17_COHERENT_INT_MASK | TX16_COHERENT_INT_MASK | \ 567 + TX15_COHERENT_INT_MASK | TX14_COHERENT_INT_MASK | \ 568 + TX13_COHERENT_INT_MASK | TX12_COHERENT_INT_MASK | \ 569 + TX11_COHERENT_INT_MASK | TX10_COHERENT_INT_MASK | \ 570 + TX9_COHERENT_INT_MASK | TX8_COHERENT_INT_MASK) 683 571 684 572 #define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050) 685 573

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