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drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL

Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655395/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-18-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov a4887182 5ef71e18

+2 -12
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
··· 19 19 { 20 20 .name = "top_0", 21 21 .base = 0x0, .len = 0x454, 22 - .features = BIT(DPU_MDP_VSYNC_SEL), 23 22 .clk_ctrls = { 24 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
··· 19 19 { 20 20 .name = "top_0", 21 21 .base = 0x0, .len = 0x454, 22 - .features = BIT(DPU_MDP_VSYNC_SEL), 23 22 .clk_ctrls = { 24 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
··· 19 19 { 20 20 .name = "top_0", 21 21 .base = 0x0, .len = 0x454, 22 - .features = BIT(DPU_MDP_VSYNC_SEL), 23 22 .clk_ctrls = { 24 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 24 [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
··· 22 22 { 23 23 .name = "top_0", 24 24 .base = 0x0, .len = 0x454, 25 - .features = BIT(DPU_MDP_VSYNC_SEL), 26 25 .clk_ctrls = { 27 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
··· 23 23 static const struct dpu_mdp_cfg msm8998_mdp = { 24 24 .name = "top_0", 25 25 .base = 0x0, .len = 0x458, 26 - .features = BIT(DPU_MDP_VSYNC_SEL), 27 26 .clk_ctrls = { 28 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
··· 22 22 static const struct dpu_mdp_cfg sdm660_mdp = { 23 23 .name = "top_0", 24 24 .base = 0x0, .len = 0x458, 25 - .features = BIT(DPU_MDP_VSYNC_SEL), 26 25 .clk_ctrls = { 27 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
··· 22 22 static const struct dpu_mdp_cfg sdm630_mdp = { 23 23 .name = "top_0", 24 24 .base = 0x0, .len = 0x458, 25 - .features = BIT(DPU_MDP_VSYNC_SEL), 26 25 .clk_ctrls = { 27 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
··· 23 23 static const struct dpu_mdp_cfg sdm845_mdp = { 24 24 .name = "top_0", 25 25 .base = 0x0, .len = 0x45c, 26 - .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), 26 + .features = BIT(DPU_MDP_AUDIO_SELECT), 27 27 .clk_ctrls = { 28 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 34 34 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 35 35 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 36 36 * in a failure 37 - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register 38 - * (moved into INTF block since DPU 5.0.0) 39 37 * @DPU_MDP_MAX Maximum value 40 38 41 39 */ ··· 42 44 DPU_MDP_10BIT_SUPPORT, 43 45 DPU_MDP_AUDIO_SELECT, 44 46 DPU_MDP_PERIPH_0_REMOVED, 45 - DPU_MDP_VSYNC_SEL, 46 47 DPU_MDP_MAX 47 48 }; 48 49
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
··· 270 270 ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl; 271 271 ops->get_danger_status = dpu_hw_get_danger_status; 272 272 273 - if (cap & BIT(DPU_MDP_VSYNC_SEL)) 273 + if (mdss_rev->core_major_ver < 5) 274 274 ops->setup_vsync_source = dpu_hw_setup_vsync_sel; 275 275 else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) 276 276 ops->setup_vsync_source = dpu_hw_setup_wd_timer;