tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'x86-cleanups-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 cleanups from Ingo Molnar:
"Miscellaneous x86 cleanups by Arnd Bergmann, Charles Han, Mirsad
Todorovac, Randy Dunlap, Thorsten Blum and Zhang Kunbo"

* tag 'x86-cleanups-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/coco: Replace 'static const cc_mask' with the newly introduced cc_get_mask() function
x86/delay: Fix inconsistent whitespace
selftests/x86/syscall: Fix coccinelle WARNING recommending the use of ARRAY_SIZE()
x86/platform: Fix missing declaration of 'x86_apple_machine'
x86/irq: Fix missing declaration of 'io_apic_irqs'
x86/usercopy: Fix kernel-doc func param name in clean_cache_range()'s description
x86/apic: Use str_disabled_enabled() helper in print_ipi_mode()

Linus Torvalds a49a879f 71b639af

+19 -6
+9 -1
arch/x86/include/asm/coco.h
··· 15 15 extern enum cc_vendor cc_vendor; 16 16 extern u64 cc_mask; 17 17 18 + static inline u64 cc_get_mask(void) 19 + { 20 + return cc_mask; 21 + } 22 + 18 23 static inline void cc_set_mask(u64 mask) 19 24 { 20 25 RIP_REL_REF(cc_mask) = mask; ··· 30 25 void cc_random_init(void); 31 26 #else 32 27 #define cc_vendor (CC_VENDOR_NONE) 33 - static const u64 cc_mask = 0; 28 + static inline u64 cc_get_mask(void) 29 + { 30 + return 0; 31 + } 34 32 35 33 static inline u64 cc_mkenc(u64 val) 36 34 {
+1 -1
arch/x86/include/asm/pgtable_types.h
··· 179 179 }; 180 180 #endif 181 181 182 - #define _PAGE_CC (_AT(pteval_t, cc_mask)) 182 + #define _PAGE_CC (_AT(pteval_t, cc_get_mask())) 183 183 #define _PAGE_ENC (_AT(pteval_t, sme_me_mask)) 184 184 185 185 #define _PAGE_CACHE_MASK (_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)
+2 -1
arch/x86/kernel/apic/ipi.c
··· 3 3 #include <linux/cpumask.h> 4 4 #include <linux/delay.h> 5 5 #include <linux/smp.h> 6 + #include <linux/string_choices.h> 6 7 7 8 #include <asm/io_apic.h> 8 9 ··· 24 23 static int __init print_ipi_mode(void) 25 24 { 26 25 pr_info("IPI shorthand broadcast: %s\n", 27 - apic_ipi_shorthand_off ? "disabled" : "enabled"); 26 + str_disabled_enabled(apic_ipi_shorthand_off)); 28 27 return 0; 29 28 } 30 29 late_initcall(print_ipi_mode);
+1
arch/x86/kernel/i8259.c
··· 23 23 #include <asm/desc.h> 24 24 #include <asm/apic.h> 25 25 #include <asm/i8259.h> 26 + #include <asm/io_apic.h> 26 27 27 28 /* 28 29 * This is the 'legacy' 8259A Programmable Interrupt Controller,
+2
arch/x86/kernel/quirks.c
··· 10 10 #include <asm/setup.h> 11 11 #include <asm/mce.h> 12 12 13 + #include <linux/platform_data/x86/apple.h> 14 + 13 15 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) 14 16 15 17 static void quirk_intel_irqbalance(struct pci_dev *dev)
+1 -1
arch/x86/lib/delay.c
··· 131 131 * Use cpu_tss_rw as a cacheline-aligned, seldom accessed per-cpu 132 132 * variable as the monitor target. 133 133 */ 134 - __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0); 134 + __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0); 135 135 136 136 /* 137 137 * AMD, like Intel, supports the EAX hint and EAX=0xf means, do not
+1 -1
arch/x86/lib/usercopy_64.c
··· 18 18 #ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE 19 19 /** 20 20 * clean_cache_range - write back a cache range with CLWB 21 - * @vaddr: virtual start address 21 + * @addr: virtual start address 22 22 * @size: number of bytes to write back 23 23 * 24 24 * Write back a cache range using the CLWB (cache line write back)
+2 -1
tools/testing/selftests/x86/syscall_numbering.c
··· 25 25 #include <sys/mman.h> 26 26 27 27 #include <linux/ptrace.h> 28 + #include "../kselftest.h" 28 29 29 30 /* Common system call numbers */ 30 31 #define SYS_READ 0 ··· 314 313 * The MSB is supposed to be ignored, so we loop over a few 315 314 * to test that out. 316 315 */ 317 - for (size_t i = 0; i < sizeof(msbs)/sizeof(msbs[0]); i++) { 316 + for (size_t i = 0; i < ARRAY_SIZE(msbs); i++) { 318 317 int msb = msbs[i]; 319 318 run("Checking system calls with msb = %d (0x%x)\n", 320 319 msb, msb);