Merge tag 'drm-fixes-2018-09-07' of git://anongit.freedesktop.org/drm/drm

+26 -7

drivers/gpu/drm/i915/gvt/dmabuf.c

··· 170 170 unsigned int tiling_mode = 0; 171 171 unsigned int stride = 0; 172 172 173 - switch (info->drm_format_mod << 10) { 174 - case PLANE_CTL_TILED_LINEAR: 173 + switch (info->drm_format_mod) { 174 + case DRM_FORMAT_MOD_LINEAR: 175 175 tiling_mode = I915_TILING_NONE; 176 176 break; 177 - case PLANE_CTL_TILED_X: 177 + case I915_FORMAT_MOD_X_TILED: 178 178 tiling_mode = I915_TILING_X; 179 179 stride = info->stride; 180 180 break; 181 - case PLANE_CTL_TILED_Y: 181 + case I915_FORMAT_MOD_Y_TILED: 182 + case I915_FORMAT_MOD_Yf_TILED: 182 183 tiling_mode = I915_TILING_Y; 183 184 stride = info->stride; 184 185 break; 185 186 default: 186 - gvt_dbg_core("not supported tiling mode\n"); 187 + gvt_dbg_core("invalid drm_format_mod %llx for tiling\n", 188 + info->drm_format_mod); 187 189 } 188 190 obj->tiling_and_stride = tiling_mode | stride; 189 191 } else { ··· 224 222 info->height = p.height; 225 223 info->stride = p.stride; 226 224 info->drm_format = p.drm_format; 227 - info->drm_format_mod = p.tiled; 225 + 226 + switch (p.tiled) { 227 + case PLANE_CTL_TILED_LINEAR: 228 + info->drm_format_mod = DRM_FORMAT_MOD_LINEAR; 229 + break; 230 + case PLANE_CTL_TILED_X: 231 + info->drm_format_mod = I915_FORMAT_MOD_X_TILED; 232 + break; 233 + case PLANE_CTL_TILED_Y: 234 + info->drm_format_mod = I915_FORMAT_MOD_Y_TILED; 235 + break; 236 + case PLANE_CTL_TILED_YF: 237 + info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED; 238 + break; 239 + default: 240 + gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled); 241 + } 242 + 228 243 info->size = (((p.stride * p.height * p.bpp) / 8) + 229 - (PAGE_SIZE - 1)) >> PAGE_SHIFT; 244 + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 230 245 } else if (plane_id == DRM_PLANE_TYPE_CURSOR) { 231 246 ret = intel_vgpu_decode_cursor_plane(vgpu, &c); 232 247 if (ret)

+2 -3

drivers/gpu/drm/i915/gvt/fb_decoder.c

··· 220 220 if (IS_SKYLAKE(dev_priv) 221 221 || IS_KABYLAKE(dev_priv) 222 222 || IS_BROXTON(dev_priv)) { 223 - plane->tiled = (val & PLANE_CTL_TILED_MASK) >> 224 - _PLANE_CTL_TILED_SHIFT; 223 + plane->tiled = val & PLANE_CTL_TILED_MASK; 225 224 fmt = skl_format_to_drm( 226 225 val & PLANE_CTL_FORMAT_MASK, 227 226 val & PLANE_CTL_ORDER_RGBX, ··· 259 260 return -EINVAL; 260 261 } 261 262 262 - plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10), 263 + plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, 263 264 (IS_SKYLAKE(dev_priv) 264 265 || IS_KABYLAKE(dev_priv) 265 266 || IS_BROXTON(dev_priv)) ?

+1 -1

drivers/gpu/drm/i915/gvt/fb_decoder.h

··· 101 101 /* color space conversion and gamma correction are not included */ 102 102 struct intel_vgpu_primary_plane_format { 103 103 u8 enabled; /* plane is enabled */ 104 - u8 tiled; /* X-tiled */ 104 + u32 tiled; /* tiling mode: linear, X-tiled, Y tiled, etc */ 105 105 u8 bpp; /* bits per pixel */ 106 106 u32 hw_format; /* format field in the PRI_CTL register */ 107 107 u32 drm_format; /* format in DRM definition */

+27 -6

drivers/gpu/drm/i915/gvt/handlers.c

··· 1296 1296 return 0; 1297 1297 } 1298 1298 1299 + static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1300 + unsigned int offset, void *p_data, unsigned int bytes) 1301 + { 1302 + write_vreg(vgpu, offset, p_data, bytes); 1303 + 1304 + if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1305 + vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1306 + else 1307 + vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1308 + 1309 + return 0; 1310 + } 1311 + 1299 1312 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1300 1313 unsigned int offset, void *p_data, unsigned int bytes) 1301 1314 { ··· 1538 1525 u32 v = *(u32 *)p_data; 1539 1526 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1540 1527 1541 - vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1542 - vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1543 - vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1528 + switch (offset) { 1529 + case _PHY_CTL_FAMILY_EDP: 1530 + vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1531 + break; 1532 + case _PHY_CTL_FAMILY_DDI: 1533 + vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1534 + vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1535 + break; 1536 + } 1544 1537 1545 1538 vgpu_vreg(vgpu, offset) = v; 1546 1539 ··· 2831 2812 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2832 2813 skl_power_well_ctl_write); 2833 2814 2815 + MMIO_DH(DBUF_CTL, D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2816 + 2834 2817 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2835 2818 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2836 2819 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); ··· 3008 2987 NULL, gen9_trtte_write); 3009 2988 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write); 3010 2989 3011 - MMIO_D(_MMIO(0x45008), D_SKL_PLUS); 3012 - 3013 2990 MMIO_D(_MMIO(0x46430), D_SKL_PLUS); 3014 2991 3015 2992 MMIO_D(_MMIO(0x46520), D_SKL_PLUS); ··· 3044 3025 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 3045 3026 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 3046 3027 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3047 - NULL, NULL); 3028 + NULL, NULL); 3029 + MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 3030 + NULL, NULL); 3048 3031 3049 3032 MMIO_D(_MMIO(0x4ab8), D_KBL); 3050 3033 MMIO_D(_MMIO(0x2248), D_KBL | D_SKL);

-2

drivers/gpu/drm/i915/gvt/mmio_context.c

··· 562 562 * performace for batch mmio read/write, so we need 563 563 * handle forcewake mannually. 564 564 */ 565 - intel_runtime_pm_get(dev_priv); 566 565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 567 566 switch_mmio(pre, next, ring_id); 568 567 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 569 - intel_runtime_pm_put(dev_priv); 570 568 } 571 569 572 570 /**

+30 -7

drivers/gpu/drm/i915/gvt/sched_policy.c

··· 47 47 return false; 48 48 } 49 49 50 + /* We give 2 seconds higher prio for vGPU during start */ 51 + #define GVT_SCHED_VGPU_PRI_TIME 2 52 + 50 53 struct vgpu_sched_data { 51 54 struct list_head lru_list; 52 55 struct intel_vgpu *vgpu; 53 56 bool active; 54 - 57 + bool pri_sched; 58 + ktime_t pri_time; 55 59 ktime_t sched_in_time; 56 60 ktime_t sched_time; 57 61 ktime_t left_ts; ··· 187 183 if (!vgpu_has_pending_workload(vgpu_data->vgpu)) 188 184 continue; 189 185 186 + if (vgpu_data->pri_sched) { 187 + if (ktime_before(ktime_get(), vgpu_data->pri_time)) { 188 + vgpu = vgpu_data->vgpu; 189 + break; 190 + } else 191 + vgpu_data->pri_sched = false; 192 + } 193 + 190 194 /* Return the vGPU only if it has time slice left */ 191 195 if (vgpu_data->left_ts > 0) { 192 196 vgpu = vgpu_data->vgpu; ··· 214 202 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 215 203 struct vgpu_sched_data *vgpu_data; 216 204 struct intel_vgpu *vgpu = NULL; 205 + 217 206 /* no active vgpu or has already had a target */ 218 207 if (list_empty(&sched_data->lru_runq_head) || scheduler->next_vgpu) 219 208 goto out; ··· 222 209 vgpu = find_busy_vgpu(sched_data); 223 210 if (vgpu) { 224 211 scheduler->next_vgpu = vgpu; 225 - 226 - /* Move the last used vGPU to the tail of lru_list */ 227 212 vgpu_data = vgpu->sched_data; 228 - list_del_init(&vgpu_data->lru_list); 229 - list_add_tail(&vgpu_data->lru_list, 230 - &sched_data->lru_runq_head); 213 + if (!vgpu_data->pri_sched) { 214 + /* Move the last used vGPU to the tail of lru_list */ 215 + list_del_init(&vgpu_data->lru_list); 216 + list_add_tail(&vgpu_data->lru_list, 217 + &sched_data->lru_runq_head); 218 + } 231 219 } else { 232 220 scheduler->next_vgpu = gvt->idle_vgpu; 233 221 } ··· 342 328 { 343 329 struct gvt_sched_data *sched_data = vgpu->gvt->scheduler.sched_data; 344 330 struct vgpu_sched_data *vgpu_data = vgpu->sched_data; 331 + ktime_t now; 345 332 346 333 if (!list_empty(&vgpu_data->lru_list)) 347 334 return; 348 335 349 - list_add_tail(&vgpu_data->lru_list, &sched_data->lru_runq_head); 336 + now = ktime_get(); 337 + vgpu_data->pri_time = ktime_add(now, 338 + ktime_set(GVT_SCHED_VGPU_PRI_TIME, 0)); 339 + vgpu_data->pri_sched = true; 340 + 341 + list_add(&vgpu_data->lru_list, &sched_data->lru_runq_head); 350 342 351 343 if (!hrtimer_active(&sched_data->timer)) 352 344 hrtimer_start(&sched_data->timer, ktime_add_ns(ktime_get(), ··· 446 426 &vgpu->gvt->scheduler; 447 427 int ring_id; 448 428 struct vgpu_sched_data *vgpu_data = vgpu->sched_data; 429 + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 449 430 450 431 if (!vgpu_data->active) 451 432 return; ··· 465 444 scheduler->current_vgpu = NULL; 466 445 } 467 446 447 + intel_runtime_pm_get(dev_priv); 468 448 spin_lock_bh(&scheduler->mmio_context_lock); 469 449 for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) { 470 450 if (scheduler->engine_owner[ring_id] == vgpu) { ··· 474 452 } 475 453 } 476 454 spin_unlock_bh(&scheduler->mmio_context_lock); 455 + intel_runtime_pm_put(dev_priv); 477 456 mutex_unlock(&vgpu->gvt->sched_lock); 478 457 }

+2 -2

drivers/gpu/drm/i915/i915_reg.h

··· 10422 10422 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 10423 10423 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 10424 10424 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10425 - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 10425 + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 10426 10426 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 10427 10427 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 10428 10428 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) ··· 10437 10437 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 10438 10438 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 10439 10439 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 10440 - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \ 10440 + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 10441 10441 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 10442 10442 #define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16) 10443 10443 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)

+9 -8

drivers/gpu/drm/i915/intel_ddi.c

··· 2708 2708 if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) 2709 2709 intel_dp_stop_link_train(intel_dp); 2710 2710 2711 - intel_ddi_enable_pipe_clock(crtc_state); 2711 + if (!is_mst) 2712 + intel_ddi_enable_pipe_clock(crtc_state); 2712 2713 } 2713 2714 2714 2715 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, ··· 2811 2810 bool is_mst = intel_crtc_has_type(old_crtc_state, 2812 2811 INTEL_OUTPUT_DP_MST); 2813 2812 2814 - intel_ddi_disable_pipe_clock(old_crtc_state); 2815 - 2816 - /* 2817 - * Power down sink before disabling the port, otherwise we end 2818 - * up getting interrupts from the sink on detecting link loss. 2819 - */ 2820 - if (!is_mst) 2813 + if (!is_mst) { 2814 + intel_ddi_disable_pipe_clock(old_crtc_state); 2815 + /* 2816 + * Power down sink before disabling the port, otherwise we end 2817 + * up getting interrupts from the sink on detecting link loss. 2818 + */ 2821 2819 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2820 + } 2822 2821 2823 2822 intel_disable_ddi_buf(encoder); 2824 2823

+19 -14

drivers/gpu/drm/i915/intel_dp.c

··· 4160 4160 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 4161 4161 } 4162 4162 4163 - /* 4164 - * If display is now connected check links status, 4165 - * there has been known issues of link loss triggering 4166 - * long pulse. 4167 - * 4168 - * Some sinks (eg. ASUS PB287Q) seem to perform some 4169 - * weird HPD ping pong during modesets. So we can apparently 4170 - * end up with HPD going low during a modeset, and then 4171 - * going back up soon after. And once that happens we must 4172 - * retrain the link to get a picture. That's in case no 4173 - * userspace component reacted to intermittent HPD dip. 4174 - */ 4175 4163 int intel_dp_retrain_link(struct intel_encoder *encoder, 4176 4164 struct drm_modeset_acquire_ctx *ctx) 4177 4165 { ··· 4649 4661 } 4650 4662 4651 4663 static int 4652 - intel_dp_long_pulse(struct intel_connector *connector) 4664 + intel_dp_long_pulse(struct intel_connector *connector, 4665 + struct drm_modeset_acquire_ctx *ctx) 4653 4666 { 4654 4667 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 4655 4668 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); ··· 4709 4720 */ 4710 4721 status = connector_status_disconnected; 4711 4722 goto out; 4723 + } else { 4724 + /* 4725 + * If display is now connected check links status, 4726 + * there has been known issues of link loss triggering 4727 + * long pulse. 4728 + * 4729 + * Some sinks (eg. ASUS PB287Q) seem to perform some 4730 + * weird HPD ping pong during modesets. So we can apparently 4731 + * end up with HPD going low during a modeset, and then 4732 + * going back up soon after. And once that happens we must 4733 + * retrain the link to get a picture. That's in case no 4734 + * userspace component reacted to intermittent HPD dip. 4735 + */ 4736 + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4737 + 4738 + intel_dp_retrain_link(encoder, ctx); 4712 4739 } 4713 4740 4714 4741 /* ··· 4786 4781 return ret; 4787 4782 } 4788 4783 4789 - status = intel_dp_long_pulse(intel_dp->attached_connector); 4784 + status = intel_dp_long_pulse(intel_dp->attached_connector, ctx); 4790 4785 } 4791 4786 4792 4787 intel_dp->detect_done = false;

+4

drivers/gpu/drm/i915/intel_dp_mst.c

··· 166 166 struct intel_connector *connector = 167 167 to_intel_connector(old_conn_state->connector); 168 168 169 + intel_ddi_disable_pipe_clock(old_crtc_state); 170 + 169 171 /* this can fail */ 170 172 drm_dp_check_act_status(&intel_dp->mst_mgr); 171 173 /* and this can also fail */ ··· 254 252 I915_WRITE(DP_TP_STATUS(port), temp); 255 253 256 254 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); 255 + 256 + intel_ddi_enable_pipe_clock(pipe_config); 257 257 } 258 258 259 259 static void intel_mst_enable_dp(struct intel_encoder *encoder,

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