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crypto: hisilicon/sec2 - fix for aead authsize alignment

The hardware only supports authentication sizes
that are 4-byte aligned. Therefore, the driver
switches to software computation in this case.

Fixes: 2f072d75d1ab ("crypto: hisilicon - Add aead support on SEC2")
Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com>
Signed-off-by: Chenghai Huang <huangchenghai2@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Wenkai Lin and committed by
Herbert Xu
a49cc71e 1b284ffc

+9 -13
+9 -13
drivers/crypto/hisilicon/sec2/sec_crypto.c
··· 57 57 #define SEC_TYPE_MASK 0x0F 58 58 #define SEC_DONE_MASK 0x0001 59 59 #define SEC_ICV_MASK 0x000E 60 - #define SEC_SQE_LEN_RATE_MASK 0x3 61 60 62 61 #define SEC_TOTAL_IV_SZ(depth) (SEC_IV_SIZE * (depth)) 63 62 #define SEC_SGL_SGE_NR 128 ··· 79 80 #define SEC_TOTAL_PBUF_SZ(depth) (PAGE_SIZE * SEC_PBUF_PAGE_NUM(depth) + \ 80 81 SEC_PBUF_LEFT_SZ(depth)) 81 82 82 - #define SEC_SQE_LEN_RATE 4 83 83 #define SEC_SQE_CFLAG 2 84 84 #define SEC_SQE_AEAD_FLAG 3 85 85 #define SEC_SQE_DONE 0x1 86 86 #define SEC_ICV_ERR 0x2 87 - #define MIN_MAC_LEN 4 88 87 #define MAC_LEN_MASK 0x1U 89 88 #define MAX_INPUT_DATA_LEN 0xFFFE00 90 89 #define BITS_MASK 0xFF 90 + #define WORD_MASK 0x3 91 91 #define BYTE_BITS 0x8 92 + #define BYTES_TO_WORDS(bcount) ((bcount) >> 2) 92 93 #define SEC_XTS_NAME_SZ 0x3 93 94 #define IV_CM_CAL_NUM 2 94 95 #define IV_CL_MASK 0x7 ··· 1170 1171 goto bad_key; 1171 1172 } 1172 1173 1173 - if (ctx->a_ctx.a_key_len & SEC_SQE_LEN_RATE_MASK) { 1174 + if (ctx->a_ctx.a_key_len & WORD_MASK) { 1174 1175 ret = -EINVAL; 1175 1176 dev_err(dev, "AUTH key length error!\n"); 1176 1177 goto bad_key; ··· 1578 1579 1579 1580 sec_sqe->type2.a_key_addr = cpu_to_le64(ctx->a_key_dma); 1580 1581 1581 - sec_sqe->type2.mac_key_alg = cpu_to_le32(authsize / SEC_SQE_LEN_RATE); 1582 + sec_sqe->type2.mac_key_alg = cpu_to_le32(BYTES_TO_WORDS(authsize)); 1582 1583 1583 1584 sec_sqe->type2.mac_key_alg |= 1584 - cpu_to_le32((u32)((ctx->a_key_len) / 1585 - SEC_SQE_LEN_RATE) << SEC_AKEY_OFFSET); 1585 + cpu_to_le32((u32)BYTES_TO_WORDS(ctx->a_key_len) << SEC_AKEY_OFFSET); 1586 1586 1587 1587 sec_sqe->type2.mac_key_alg |= 1588 1588 cpu_to_le32((u32)(ctx->a_alg) << SEC_AEAD_ALG_OFFSET); ··· 1633 1635 sqe3->a_key_addr = cpu_to_le64(ctx->a_key_dma); 1634 1636 1635 1637 sqe3->auth_mac_key |= 1636 - cpu_to_le32((u32)(authsize / 1637 - SEC_SQE_LEN_RATE) << SEC_MAC_OFFSET_V3); 1638 + cpu_to_le32(BYTES_TO_WORDS(authsize) << SEC_MAC_OFFSET_V3); 1638 1639 1639 1640 sqe3->auth_mac_key |= 1640 - cpu_to_le32((u32)(ctx->a_key_len / 1641 - SEC_SQE_LEN_RATE) << SEC_AKEY_OFFSET_V3); 1641 + cpu_to_le32((u32)BYTES_TO_WORDS(ctx->a_key_len) << SEC_AKEY_OFFSET_V3); 1642 1642 1643 1643 sqe3->auth_mac_key |= 1644 1644 cpu_to_le32((u32)(ctx->a_alg) << SEC_AUTH_ALG_OFFSET_V3); ··· 2226 2230 struct device *dev = ctx->dev; 2227 2231 int ret; 2228 2232 2229 - /* Hardware does not handle cases where authsize is less than 4 bytes */ 2230 - if (unlikely(sz < MIN_MAC_LEN)) { 2233 + /* Hardware does not handle cases where authsize is not 4 bytes aligned */ 2234 + if (c_mode == SEC_CMODE_CBC && (sz & WORD_MASK)) { 2231 2235 sreq->aead_req.fallback = true; 2232 2236 return -EINVAL; 2233 2237 }