Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
i3c: mipi-i3c-hci: Convert remaining DBG() prints to dev_dbg()
Get rid of local DBG() macro and convert remaining debug prints to
dev_dbg() which can be controlled without code recompile when kernel is
built with dynamic debug support.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20250827103009.243771-6-jarkko.nikula@linux.intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
authored by
Jarkko Nikula
and committed by
Alexandre Belloni
a4ea64ab
a00e15f3
+73
-56
+6
-3
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
+6
-3
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
···
317
317
break;
318
318
next_addr = ret;
319
319
320
-
DBG("next_addr = 0x%02x, DAA using DAT %d", next_addr, dat_idx);
320
+
dev_dbg(&hci->master.dev,
321
+
"next_addr = 0x%02x, DAA using DAT %d",
322
+
next_addr, dat_idx);
321
323
mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dat_idx, next_addr);
322
324
mipi_i3c_hci_dct_index_reset(hci);
323
325
···
351
349
}
352
350
353
351
i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr);
354
-
DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
355
-
next_addr, pid, dcr, bcr);
352
+
dev_dbg(&hci->master.dev,
353
+
"assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
354
+
next_addr, pid, dcr, bcr);
356
355
357
356
mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx);
358
357
dat_idx = -1;
+4
-3
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
+4
-3
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
···
261
261
if (ret < 0)
262
262
break;
263
263
next_addr = ret;
264
-
DBG("next_addr = 0x%02x", next_addr);
264
+
dev_dbg(&hci->master.dev, "next_addr = 0x%02x", next_addr);
265
265
xfer[0].cmd_tid = hci_get_tid();
266
266
xfer[0].cmd_desc[0] =
267
267
CMD_0_ATTR_A |
···
293
293
pid = (pid << 32) | device_id[0];
294
294
bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]);
295
295
dcr = FIELD_GET(W1_MASK(63, 56), device_id[1]);
296
-
DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
297
-
next_addr, pid, dcr, bcr);
296
+
dev_dbg(&hci->master.dev,
297
+
"assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
298
+
next_addr, pid, dcr, bcr);
298
299
/*
299
300
* TODO: Extend the subsystem layer to allow for registering
300
301
* new device and provide BCR/DCR/PID at the same time.
+8
-8
drivers/i3c/master/mipi-i3c-hci/core.c
+8
-8
drivers/i3c/master/mipi-i3c-hci/core.c
···
147
147
amd_set_resp_buf_thld(hci);
148
148
149
149
reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
150
-
DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL));
150
+
dev_dbg(&hci->master.dev, "HC_CONTROL = %#x", reg_read(HC_CONTROL));
151
151
152
152
return 0;
153
153
}
···
192
192
DECLARE_COMPLETION_ONSTACK(done);
193
193
int i, last, ret = 0;
194
194
195
-
DBG("cmd=%#x rnw=%d ndests=%d data[0].len=%d",
196
-
ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len);
195
+
dev_dbg(&hci->master.dev, "cmd=%#x rnw=%d ndests=%d data[0].len=%d",
196
+
ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len);
197
197
198
198
xfer = hci_alloc_xfer(nxfers);
199
199
if (!xfer)
···
251
251
}
252
252
253
253
if (ccc->rnw)
254
-
DBG("got: %*ph",
255
-
ccc->dests[0].payload.len, ccc->dests[0].payload.data);
254
+
dev_dbg(&hci->master.dev, "got: %*ph",
255
+
ccc->dests[0].payload.len, ccc->dests[0].payload.data);
256
256
257
257
out:
258
258
hci_free_xfer(xfer, nxfers);
···
277
277
unsigned int size_limit;
278
278
int i, last, ret = 0;
279
279
280
-
DBG("nxfers = %d", nxfers);
280
+
dev_dbg(&hci->master.dev, "nxfers = %d", nxfers);
281
281
282
282
xfer = hci_alloc_xfer(nxfers);
283
283
if (!xfer)
···
335
335
DECLARE_COMPLETION_ONSTACK(done);
336
336
int i, last, ret = 0;
337
337
338
-
DBG("nxfers = %d", nxfers);
338
+
dev_dbg(&hci->master.dev, "nxfers = %d", nxfers);
339
339
340
340
xfer = hci_alloc_xfer(nxfers);
341
341
if (!xfer)
···
587
587
}
588
588
589
589
hci->caps = reg_read(HC_CAPABILITIES);
590
-
DBG("caps = %#x", hci->caps);
590
+
dev_dbg(&hci->master.dev, "caps = %#x", hci->caps);
591
591
592
592
size_in_dwords = hci->version_major < 1 ||
593
593
(hci->version_major == 1 && hci->version_minor < 1);
+9
-6
drivers/i3c/master/mipi-i3c-hci/dma.c
+9
-6
drivers/i3c/master/mipi-i3c-hci/dma.c
···
248
248
regval = rh_reg_read(CR_SETUP);
249
249
rh->xfer_struct_sz = FIELD_GET(CR_XFER_STRUCT_SIZE, regval);
250
250
rh->resp_struct_sz = FIELD_GET(CR_RESP_STRUCT_SIZE, regval);
251
-
DBG("xfer_struct_sz = %d, resp_struct_sz = %d",
252
-
rh->xfer_struct_sz, rh->resp_struct_sz);
251
+
dev_dbg(&hci->master.dev,
252
+
"xfer_struct_sz = %d, resp_struct_sz = %d",
253
+
rh->xfer_struct_sz, rh->resp_struct_sz);
253
254
xfers_sz = rh->xfer_struct_sz * rh->xfer_entries;
254
255
resps_sz = rh->resp_struct_sz * rh->xfer_entries;
255
256
···
524
523
ring_resp = rh->resp + rh->resp_struct_sz * done_ptr;
525
524
resp = *ring_resp;
526
525
tid = RESP_TID(resp);
527
-
DBG("resp = 0x%08x", resp);
526
+
dev_dbg(&hci->master.dev, "resp = 0x%08x", resp);
528
527
529
528
xfer = rh->src_xfers[done_ptr];
530
529
if (!xfer) {
531
-
DBG("orphaned ring entry");
530
+
dev_dbg(&hci->master.dev, "orphaned ring entry");
532
531
} else {
533
532
hci_dma_unmap_xfer(hci, xfer, 1);
534
533
xfer->ring_entry = -1;
···
631
630
632
631
ring_ibi_status = rh->ibi_status + rh->ibi_status_sz * ptr;
633
632
ibi_status = *ring_ibi_status;
634
-
DBG("status = %#x", ibi_status);
633
+
dev_dbg(&hci->master.dev, "status = %#x", ibi_status);
635
634
636
635
if (ibi_status_error) {
637
636
/* we no longer care */
···
659
658
660
659
if (last_ptr == -1) {
661
660
/* this IBI sequence is not yet complete */
662
-
DBG("no LAST_STATUS available (e=%d d=%d)", enq_ptr, deq_ptr);
661
+
dev_dbg(&hci->master.dev,
662
+
"no LAST_STATUS available (e=%d d=%d)",
663
+
enq_ptr, deq_ptr);
663
664
return;
664
665
}
665
666
deq_ptr = last_ptr + 1;
+7
-4
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
+7
-4
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
···
35
35
switch (hci->vendor_mipi_id) {
36
36
case MIPI_VENDOR_NXP:
37
37
hci->quirks |= HCI_QUIRK_RAW_CCC;
38
-
DBG("raw CCC quirks set");
38
+
dev_dbg(&hci->master.dev, "raw CCC quirks set");
39
39
break;
40
40
}
41
41
···
77
77
for (index = 0; index < entries; index++) {
78
78
u32 mode_entry = readl(base);
79
79
80
-
DBG("mode %d: 0x%08x", index, mode_entry);
80
+
dev_dbg(&hci->master.dev, "mode %d: 0x%08x",
81
+
index, mode_entry);
81
82
/* TODO: will be needed when I3C core does more than SDR */
82
83
base += 4;
83
84
}
···
98
97
dev_info(&hci->master.dev, "available data rates:\n");
99
98
for (index = 0; index < entries; index++) {
100
99
rate_entry = readl(base);
101
-
DBG("entry %d: 0x%08x", index, rate_entry);
100
+
dev_dbg(&hci->master.dev, "entry %d: 0x%08x",
101
+
index, rate_entry);
102
102
rate = FIELD_GET(XFERRATE_ACTUAL_RATE_KHZ, rate_entry);
103
103
rate_id = FIELD_GET(XFERRATE_RATE_ID, rate_entry);
104
104
mode_id = FIELD_GET(XFERRATE_MODE_ID, rate_entry);
···
270
268
cap_header = readl(curr_cap);
271
269
cap_id = FIELD_GET(CAP_HEADER_ID, cap_header);
272
270
cap_length = FIELD_GET(CAP_HEADER_LENGTH, cap_header);
273
-
DBG("id=0x%02x length=%d", cap_id, cap_length);
271
+
dev_dbg(&hci->master.dev, "id=0x%02x length=%d",
272
+
cap_id, cap_length);
274
273
if (!cap_length)
275
274
break;
276
275
if (curr_cap + cap_length * 4 >= end) {
-3
drivers/i3c/master/mipi-i3c-hci/hci.h
-3
drivers/i3c/master/mipi-i3c-hci/hci.h
···
12
12
13
13
#include <linux/io.h>
14
14
15
-
/* Handy logging macro to save on line length */
16
-
#define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__)
17
-
18
15
/* 32-bit word aware bit and mask macros */
19
16
#define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0)
20
17
#define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32)
+39
-29
drivers/i3c/master/mipi-i3c-hci/pio.c
+39
-29
drivers/i3c/master/mipi-i3c-hci/pio.c
···
213
213
pio_reg_write(INTR_SIGNAL_ENABLE, 0x0);
214
214
215
215
if (pio) {
216
-
DBG("status = %#x/%#x",
217
-
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
216
+
dev_dbg(&hci->master.dev, "status = %#x/%#x",
217
+
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
218
218
BUG_ON(pio->curr_xfer);
219
219
BUG_ON(pio->curr_rx);
220
220
BUG_ON(pio->curr_tx);
···
226
226
227
227
static void hci_pio_write_cmd(struct i3c_hci *hci, struct hci_xfer *xfer)
228
228
{
229
-
DBG("cmd_desc[%d] = 0x%08x", 0, xfer->cmd_desc[0]);
230
-
DBG("cmd_desc[%d] = 0x%08x", 1, xfer->cmd_desc[1]);
229
+
dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x",
230
+
0, xfer->cmd_desc[0]);
231
+
dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x",
232
+
1, xfer->cmd_desc[1]);
231
233
pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[0]);
232
234
pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[1]);
233
235
if (hci->cmd == &mipi_i3c_hci_cmd_v2) {
234
-
DBG("cmd_desc[%d] = 0x%08x", 2, xfer->cmd_desc[2]);
235
-
DBG("cmd_desc[%d] = 0x%08x", 3, xfer->cmd_desc[3]);
236
+
dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x",
237
+
2, xfer->cmd_desc[2]);
238
+
dev_dbg(&hci->master.dev, "cmd_desc[%d] = 0x%08x",
239
+
3, xfer->cmd_desc[3]);
236
240
pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[2]);
237
241
pio_reg_write(COMMAND_QUEUE_PORT, xfer->cmd_desc[3]);
238
242
}
···
258
254
nr_words = min(xfer->data_left / 4, pio->rx_thresh_size);
259
255
/* extract data from FIFO */
260
256
xfer->data_left -= nr_words * 4;
261
-
DBG("now %d left %d", nr_words * 4, xfer->data_left);
257
+
dev_dbg(&hci->master.dev, "now %d left %d",
258
+
nr_words * 4, xfer->data_left);
262
259
while (nr_words--)
263
260
*p++ = pio_reg_read(XFER_DATA_PORT);
264
261
}
···
274
269
struct hci_xfer *xfer = pio->curr_rx;
275
270
u32 *p;
276
271
277
-
DBG("%d remaining", count);
272
+
dev_dbg(&hci->master.dev, "%d remaining", count);
278
273
279
274
p = xfer->data;
280
275
p += (xfer->data_len - xfer->data_left) / 4;
···
283
278
unsigned int nr_words = count / 4;
284
279
/* extract data from FIFO */
285
280
xfer->data_left -= nr_words * 4;
286
-
DBG("now %d left %d", nr_words * 4, xfer->data_left);
281
+
dev_dbg(&hci->master.dev, "now %d left %d",
282
+
nr_words * 4, xfer->data_left);
287
283
while (nr_words--)
288
284
*p++ = pio_reg_read(XFER_DATA_PORT);
289
285
}
···
327
321
nr_words = min(xfer->data_left / 4, pio->tx_thresh_size);
328
322
/* push data into the FIFO */
329
323
xfer->data_left -= nr_words * 4;
330
-
DBG("now %d left %d", nr_words * 4, xfer->data_left);
324
+
dev_dbg(&hci->master.dev, "now %d left %d",
325
+
nr_words * 4, xfer->data_left);
331
326
while (nr_words--)
332
327
pio_reg_write(XFER_DATA_PORT, *p++);
333
328
}
···
343
336
*/
344
337
if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD))
345
338
return false;
346
-
DBG("trailing %d", xfer->data_left);
339
+
dev_dbg(&hci->master.dev, "trailing %d", xfer->data_left);
347
340
pio_reg_write(XFER_DATA_PORT, *p);
348
341
xfer->data_left = 0;
349
342
}
···
488
481
u32 resp = pio_reg_read(RESPONSE_QUEUE_PORT);
489
482
unsigned int tid = RESP_TID(resp);
490
483
491
-
DBG("resp = 0x%08x", resp);
484
+
dev_dbg(&hci->master.dev, "resp = 0x%08x", resp);
492
485
if (tid != xfer->cmd_tid) {
493
486
dev_err(&hci->master.dev,
494
487
"response tid=%d when expecting %d\n",
···
529
522
* still exists.
530
523
*/
531
524
if (pio->curr_rx == xfer) {
532
-
DBG("short RX ?");
525
+
dev_dbg(&hci->master.dev, "short RX ?");
533
526
pio->curr_rx = pio->curr_rx->next_data;
534
527
} else if (pio->curr_tx == xfer) {
535
-
DBG("short TX ?");
528
+
dev_dbg(&hci->master.dev, "short TX ?");
536
529
pio->curr_tx = pio->curr_tx->next_data;
537
530
} else if (xfer->data_left) {
538
-
DBG("PIO xfer count = %d after response",
539
-
xfer->data_left);
531
+
dev_dbg(&hci->master.dev,
532
+
"PIO xfer count = %d after response",
533
+
xfer->data_left);
540
534
}
541
535
542
536
pio->curr_resp = xfer->next_resp;
···
599
591
struct hci_xfer *prev_queue_tail;
600
592
int i;
601
593
602
-
DBG("n = %d", n);
594
+
dev_dbg(&hci->master.dev, "n = %d", n);
603
595
604
596
/* link xfer instances together and initialize data count */
605
597
for (i = 0; i < n; i++) {
···
619
611
if (!hci_pio_process_cmd(hci, pio))
620
612
pio->enabled_irqs |= STAT_CMD_QUEUE_READY;
621
613
pio_reg_write(INTR_SIGNAL_ENABLE, pio->enabled_irqs);
622
-
DBG("status = %#x/%#x",
623
-
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
614
+
dev_dbg(&hci->master.dev, "status = %#x/%#x",
615
+
pio_reg_read(INTR_STATUS),
616
+
pio_reg_read(INTR_SIGNAL_ENABLE));
624
617
}
625
618
spin_unlock_irq(&pio->lock);
626
619
return 0;
···
695
686
int ret;
696
687
697
688
spin_lock_irq(&pio->lock);
698
-
DBG("n=%d status=%#x/%#x", n,
699
-
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
700
-
DBG("main_status = %#x/%#x",
701
-
readl(hci->base_regs + 0x20), readl(hci->base_regs + 0x28));
689
+
dev_dbg(&hci->master.dev, "n=%d status=%#x/%#x", n,
690
+
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
691
+
dev_dbg(&hci->master.dev, "main_status = %#x/%#x",
692
+
readl(hci->base_regs + 0x20), readl(hci->base_regs + 0x28));
702
693
703
694
ret = hci_pio_dequeue_xfer_common(hci, pio, xfer, n);
704
695
spin_unlock_irq(&pio->lock);
···
742
733
mipi_i3c_hci_pio_reset(hci);
743
734
mipi_i3c_hci_resume(hci);
744
735
745
-
DBG("status=%#x/%#x",
746
-
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
736
+
dev_dbg(&hci->master.dev, "status=%#x/%#x",
737
+
pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE));
747
738
}
748
739
749
740
static void hci_pio_set_ibi_thresh(struct i3c_hci *hci,
···
758
749
if (regval != pio->reg_queue_thresh) {
759
750
pio_reg_write(QUEUE_THLD_CTRL, regval);
760
751
pio->reg_queue_thresh = regval;
761
-
DBG("%d", thresh_val);
752
+
dev_dbg(&hci->master.dev, "%d", thresh_val);
762
753
}
763
754
}
764
755
···
782
773
/* extract the data from the IBI port */
783
774
nr_words = thresh_val;
784
775
ibi->seg_cnt -= nr_words * 4;
785
-
DBG("now %d left %d", nr_words * 4, ibi->seg_cnt);
776
+
dev_dbg(&hci->master.dev, "now %d left %d",
777
+
nr_words * 4, ibi->seg_cnt);
786
778
while (nr_words--)
787
779
*p++ = pio_reg_read(IBI_PORT);
788
780
}
···
801
791
hci_pio_set_ibi_thresh(hci, pio, 1);
802
792
if (!(pio_reg_read(INTR_STATUS) & STAT_IBI_STATUS_THLD))
803
793
return false;
804
-
DBG("trailing %d", ibi->seg_cnt);
794
+
dev_dbg(&hci->master.dev, "trailing %d", ibi->seg_cnt);
805
795
data = pio_reg_read(IBI_PORT);
806
796
data = (__force u32) cpu_to_le32(data);
807
797
while (ibi->seg_cnt--) {
···
830
820
*/
831
821
832
822
ibi_status = pio_reg_read(IBI_PORT);
833
-
DBG("status = %#x", ibi_status);
823
+
dev_dbg(&hci->master.dev, "status = %#x", ibi_status);
834
824
ibi->addr = FIELD_GET(IBI_TARGET_ADDR, ibi_status);
835
825
if (ibi_status & IBI_ERROR) {
836
826
dev_err(&hci->master.dev, "IBI error from %#x\n", ibi->addr);