Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
The global clock controller on the Nord SoC is partitioned into
GCC, SE_GCC, NE_GCC, and NW_GCC. Introduce driver support for each
of these controllers.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
[Shawn: Drop include of <linux/of.h> as the driver doesn't use any OF APIs]
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-6-018af14979fd@oss.qualcomm.com
[bjorn: Added missing .use_rpm to gcc_nord_desc]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
a4f780cd
cf6e6ac6
+6197
+10
drivers/clk/qcom/Kconfig
+10
drivers/clk/qcom/Kconfig
···
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Say Y if you want to support video devices and functionality such as
146
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video encode/decode.
147
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+
config CLK_NORD_GCC
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tristate "Nord Global Clock Controller"
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depends on ARM64 || COMPILE_TEST
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select QCOM_GDSC
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help
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Support for the global clock controller on Nord devices.
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+
Say Y if you want to use peripheral devices such as UART,
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+
SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination
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of GCC, SE_GCC, NE_GCC and NW_GCC.
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+
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config CLK_X1E80100_CAMCC
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tristate "X1E80100 Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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35
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
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36
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
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obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
38
+
obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
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obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
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obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
+1902
drivers/clk/qcom/gcc-nord.c
+1902
drivers/clk/qcom/gcc-nord.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
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+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
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+
#include <linux/platform_device.h>
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+
#include <linux/regmap.h>
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+
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+
#include <dt-bindings/clock/qcom,nord-gcc.h>
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+
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+
#include "clk-alpha-pll.h"
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+
#include "clk-branch.h"
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+
#include "clk-pll.h"
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+
#include "clk-rcg.h"
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+
#include "clk-regmap.h"
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+
#include "clk-regmap-divider.h"
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+
#include "clk-regmap-mux.h"
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+
#include "clk-regmap-phy-mux.h"
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+
#include "common.h"
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+
#include "gdsc.h"
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+
#include "reset.h"
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+
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enum {
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DT_BI_TCXO,
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DT_SLEEP_CLK,
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DT_PCIE_A_PIPE_CLK,
30
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DT_PCIE_B_PIPE_CLK,
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DT_PCIE_C_PIPE_CLK,
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+
DT_PCIE_D_PIPE_CLK,
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+
};
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+
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enum {
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P_BI_TCXO,
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P_GCC_GPLL0_OUT_EVEN,
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P_GCC_GPLL0_OUT_MAIN,
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+
P_PCIE_A_PIPE_CLK,
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+
P_PCIE_B_PIPE_CLK,
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P_PCIE_C_PIPE_CLK,
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P_PCIE_D_PIPE_CLK,
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P_SLEEP_CLK,
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+
};
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+
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+
static struct clk_alpha_pll gcc_gpll0 = {
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+
.offset = 0x0,
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
49
+
.clkr = {
50
+
.enable_reg = 0x9d020,
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+
.enable_mask = BIT(0),
52
+
.hw.init = &(const struct clk_init_data) {
53
+
.name = "gcc_gpll0",
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+
.parent_data = &(const struct clk_parent_data) {
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+
.index = DT_BI_TCXO,
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+
},
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+
.num_parents = 1,
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+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
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+
},
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+
},
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+
};
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+
63
+
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
64
+
{ 0x1, 2 },
65
+
{ }
66
+
};
67
+
68
+
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
69
+
.offset = 0x0,
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+
.post_div_shift = 10,
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.post_div_table = post_div_table_gcc_gpll0_out_even,
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+
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
73
+
.width = 4,
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+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
75
+
.clkr.hw.init = &(const struct clk_init_data) {
76
+
.name = "gcc_gpll0_out_even",
77
+
.parent_hws = (const struct clk_hw*[]) {
78
+
&gcc_gpll0.clkr.hw,
79
+
},
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+
.num_parents = 1,
81
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
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+
},
83
+
};
84
+
85
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static const struct parent_map gcc_parent_map_0[] = {
86
+
{ P_BI_TCXO, 0 },
87
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
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+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
89
+
};
90
+
91
+
static const struct clk_parent_data gcc_parent_data_0[] = {
92
+
{ .index = DT_BI_TCXO },
93
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{ .hw = &gcc_gpll0.clkr.hw },
94
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
95
+
};
96
+
97
+
static const struct parent_map gcc_parent_map_1[] = {
98
+
{ P_BI_TCXO, 0 },
99
+
{ P_SLEEP_CLK, 5 },
100
+
};
101
+
102
+
static const struct clk_parent_data gcc_parent_data_1[] = {
103
+
{ .index = DT_BI_TCXO },
104
+
{ .index = DT_SLEEP_CLK },
105
+
};
106
+
107
+
static const struct parent_map gcc_parent_map_2[] = {
108
+
{ P_BI_TCXO, 0 },
109
+
{ P_GCC_GPLL0_OUT_MAIN, 1 },
110
+
{ P_SLEEP_CLK, 5 },
111
+
{ P_GCC_GPLL0_OUT_EVEN, 6 },
112
+
};
113
+
114
+
static const struct clk_parent_data gcc_parent_data_2[] = {
115
+
{ .index = DT_BI_TCXO },
116
+
{ .hw = &gcc_gpll0.clkr.hw },
117
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{ .index = DT_SLEEP_CLK },
118
+
{ .hw = &gcc_gpll0_out_even.clkr.hw },
119
+
};
120
+
121
+
static const struct parent_map gcc_parent_map_3[] = {
122
+
{ P_BI_TCXO, 0 },
123
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{ P_GCC_GPLL0_OUT_MAIN, 1 },
124
+
};
125
+
126
+
static const struct clk_parent_data gcc_parent_data_3[] = {
127
+
{ .index = DT_BI_TCXO },
128
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{ .hw = &gcc_gpll0.clkr.hw },
129
+
};
130
+
131
+
static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = {
132
+
.reg = 0x49094,
133
+
.clkr = {
134
+
.hw.init = &(const struct clk_init_data) {
135
+
.name = "gcc_pcie_a_pipe_clk_src",
136
+
.parent_data = &(const struct clk_parent_data){
137
+
.index = DT_PCIE_A_PIPE_CLK,
138
+
},
139
+
.num_parents = 1,
140
+
.ops = &clk_regmap_phy_mux_ops,
141
+
},
142
+
},
143
+
};
144
+
145
+
static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = {
146
+
.reg = 0x4a094,
147
+
.clkr = {
148
+
.hw.init = &(const struct clk_init_data) {
149
+
.name = "gcc_pcie_b_pipe_clk_src",
150
+
.parent_data = &(const struct clk_parent_data){
151
+
.index = DT_PCIE_B_PIPE_CLK,
152
+
},
153
+
.num_parents = 1,
154
+
.ops = &clk_regmap_phy_mux_ops,
155
+
},
156
+
},
157
+
};
158
+
159
+
static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = {
160
+
.reg = 0x4b094,
161
+
.clkr = {
162
+
.hw.init = &(const struct clk_init_data) {
163
+
.name = "gcc_pcie_c_pipe_clk_src",
164
+
.parent_data = &(const struct clk_parent_data){
165
+
.index = DT_PCIE_C_PIPE_CLK,
166
+
},
167
+
.num_parents = 1,
168
+
.ops = &clk_regmap_phy_mux_ops,
169
+
},
170
+
},
171
+
};
172
+
173
+
static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = {
174
+
.reg = 0x4c094,
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+
.clkr = {
176
+
.hw.init = &(const struct clk_init_data) {
177
+
.name = "gcc_pcie_d_pipe_clk_src",
178
+
.parent_data = &(const struct clk_parent_data){
179
+
.index = DT_PCIE_D_PIPE_CLK,
180
+
},
181
+
.num_parents = 1,
182
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.ops = &clk_regmap_phy_mux_ops,
183
+
},
184
+
},
185
+
};
186
+
187
+
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
188
+
F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
189
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
190
+
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
191
+
{ }
192
+
};
193
+
194
+
static struct clk_rcg2 gcc_gp1_clk_src = {
195
+
.cmd_rcgr = 0x30004,
196
+
.mnd_width = 16,
197
+
.hid_width = 5,
198
+
.parent_map = gcc_parent_map_2,
199
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
200
+
.hw_clk_ctrl = true,
201
+
.clkr.hw.init = &(const struct clk_init_data) {
202
+
.name = "gcc_gp1_clk_src",
203
+
.parent_data = gcc_parent_data_2,
204
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
205
+
.flags = CLK_SET_RATE_PARENT,
206
+
.ops = &clk_rcg2_shared_ops,
207
+
},
208
+
};
209
+
210
+
static struct clk_rcg2 gcc_gp2_clk_src = {
211
+
.cmd_rcgr = 0x31004,
212
+
.mnd_width = 16,
213
+
.hid_width = 5,
214
+
.parent_map = gcc_parent_map_2,
215
+
.freq_tbl = ftbl_gcc_gp1_clk_src,
216
+
.hw_clk_ctrl = true,
217
+
.clkr.hw.init = &(const struct clk_init_data) {
218
+
.name = "gcc_gp2_clk_src",
219
+
.parent_data = gcc_parent_data_2,
220
+
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
221
+
.flags = CLK_SET_RATE_PARENT,
222
+
.ops = &clk_rcg2_shared_ops,
223
+
},
224
+
};
225
+
226
+
static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = {
227
+
F(19200000, P_BI_TCXO, 1, 0, 0),
228
+
{ }
229
+
};
230
+
231
+
static struct clk_rcg2 gcc_pcie_a_aux_clk_src = {
232
+
.cmd_rcgr = 0x49098,
233
+
.mnd_width = 16,
234
+
.hid_width = 5,
235
+
.parent_map = gcc_parent_map_1,
236
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
237
+
.hw_clk_ctrl = true,
238
+
.clkr.hw.init = &(const struct clk_init_data) {
239
+
.name = "gcc_pcie_a_aux_clk_src",
240
+
.parent_data = gcc_parent_data_1,
241
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
242
+
.flags = CLK_SET_RATE_PARENT,
243
+
.ops = &clk_rcg2_shared_ops,
244
+
},
245
+
};
246
+
247
+
static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = {
248
+
.cmd_rcgr = 0x4d020,
249
+
.mnd_width = 16,
250
+
.hid_width = 5,
251
+
.parent_map = gcc_parent_map_1,
252
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
253
+
.hw_clk_ctrl = true,
254
+
.clkr.hw.init = &(const struct clk_init_data) {
255
+
.name = "gcc_pcie_a_phy_aux_clk_src",
256
+
.parent_data = gcc_parent_data_1,
257
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
258
+
.flags = CLK_SET_RATE_PARENT,
259
+
.ops = &clk_rcg2_shared_ops,
260
+
},
261
+
};
262
+
263
+
static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = {
264
+
F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
265
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
266
+
{ }
267
+
};
268
+
269
+
static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = {
270
+
.cmd_rcgr = 0x4907c,
271
+
.mnd_width = 0,
272
+
.hid_width = 5,
273
+
.parent_map = gcc_parent_map_0,
274
+
.freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
275
+
.hw_clk_ctrl = true,
276
+
.clkr.hw.init = &(const struct clk_init_data) {
277
+
.name = "gcc_pcie_a_phy_rchng_clk_src",
278
+
.parent_data = gcc_parent_data_0,
279
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
280
+
.flags = CLK_SET_RATE_PARENT,
281
+
.ops = &clk_rcg2_shared_ops,
282
+
},
283
+
};
284
+
285
+
static struct clk_rcg2 gcc_pcie_b_aux_clk_src = {
286
+
.cmd_rcgr = 0x4a098,
287
+
.mnd_width = 16,
288
+
.hid_width = 5,
289
+
.parent_map = gcc_parent_map_1,
290
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
291
+
.hw_clk_ctrl = true,
292
+
.clkr.hw.init = &(const struct clk_init_data) {
293
+
.name = "gcc_pcie_b_aux_clk_src",
294
+
.parent_data = gcc_parent_data_1,
295
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
296
+
.flags = CLK_SET_RATE_PARENT,
297
+
.ops = &clk_rcg2_shared_ops,
298
+
},
299
+
};
300
+
301
+
static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = {
302
+
.cmd_rcgr = 0x4e020,
303
+
.mnd_width = 16,
304
+
.hid_width = 5,
305
+
.parent_map = gcc_parent_map_1,
306
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
307
+
.hw_clk_ctrl = true,
308
+
.clkr.hw.init = &(const struct clk_init_data) {
309
+
.name = "gcc_pcie_b_phy_aux_clk_src",
310
+
.parent_data = gcc_parent_data_1,
311
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
312
+
.flags = CLK_SET_RATE_PARENT,
313
+
.ops = &clk_rcg2_shared_ops,
314
+
},
315
+
};
316
+
317
+
static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = {
318
+
.cmd_rcgr = 0x4a07c,
319
+
.mnd_width = 0,
320
+
.hid_width = 5,
321
+
.parent_map = gcc_parent_map_0,
322
+
.freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
323
+
.hw_clk_ctrl = true,
324
+
.clkr.hw.init = &(const struct clk_init_data) {
325
+
.name = "gcc_pcie_b_phy_rchng_clk_src",
326
+
.parent_data = gcc_parent_data_0,
327
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
328
+
.flags = CLK_SET_RATE_PARENT,
329
+
.ops = &clk_rcg2_shared_ops,
330
+
},
331
+
};
332
+
333
+
static struct clk_rcg2 gcc_pcie_c_aux_clk_src = {
334
+
.cmd_rcgr = 0x4b098,
335
+
.mnd_width = 16,
336
+
.hid_width = 5,
337
+
.parent_map = gcc_parent_map_1,
338
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
339
+
.hw_clk_ctrl = true,
340
+
.clkr.hw.init = &(const struct clk_init_data) {
341
+
.name = "gcc_pcie_c_aux_clk_src",
342
+
.parent_data = gcc_parent_data_1,
343
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
344
+
.flags = CLK_SET_RATE_PARENT,
345
+
.ops = &clk_rcg2_shared_ops,
346
+
},
347
+
};
348
+
349
+
static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = {
350
+
.cmd_rcgr = 0x4f020,
351
+
.mnd_width = 16,
352
+
.hid_width = 5,
353
+
.parent_map = gcc_parent_map_1,
354
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
355
+
.hw_clk_ctrl = true,
356
+
.clkr.hw.init = &(const struct clk_init_data) {
357
+
.name = "gcc_pcie_c_phy_aux_clk_src",
358
+
.parent_data = gcc_parent_data_1,
359
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
360
+
.flags = CLK_SET_RATE_PARENT,
361
+
.ops = &clk_rcg2_shared_ops,
362
+
},
363
+
};
364
+
365
+
static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = {
366
+
.cmd_rcgr = 0x4b07c,
367
+
.mnd_width = 0,
368
+
.hid_width = 5,
369
+
.parent_map = gcc_parent_map_3,
370
+
.freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
371
+
.hw_clk_ctrl = true,
372
+
.clkr.hw.init = &(const struct clk_init_data) {
373
+
.name = "gcc_pcie_c_phy_rchng_clk_src",
374
+
.parent_data = gcc_parent_data_3,
375
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
376
+
.flags = CLK_SET_RATE_PARENT,
377
+
.ops = &clk_rcg2_shared_ops,
378
+
},
379
+
};
380
+
381
+
static struct clk_rcg2 gcc_pcie_d_aux_clk_src = {
382
+
.cmd_rcgr = 0x4c098,
383
+
.mnd_width = 16,
384
+
.hid_width = 5,
385
+
.parent_map = gcc_parent_map_1,
386
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
387
+
.hw_clk_ctrl = true,
388
+
.clkr.hw.init = &(const struct clk_init_data) {
389
+
.name = "gcc_pcie_d_aux_clk_src",
390
+
.parent_data = gcc_parent_data_1,
391
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
392
+
.flags = CLK_SET_RATE_PARENT,
393
+
.ops = &clk_rcg2_shared_ops,
394
+
},
395
+
};
396
+
397
+
static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = {
398
+
.cmd_rcgr = 0x50020,
399
+
.mnd_width = 16,
400
+
.hid_width = 5,
401
+
.parent_map = gcc_parent_map_1,
402
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
403
+
.hw_clk_ctrl = true,
404
+
.clkr.hw.init = &(const struct clk_init_data) {
405
+
.name = "gcc_pcie_d_phy_aux_clk_src",
406
+
.parent_data = gcc_parent_data_1,
407
+
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
408
+
.flags = CLK_SET_RATE_PARENT,
409
+
.ops = &clk_rcg2_shared_ops,
410
+
},
411
+
};
412
+
413
+
static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = {
414
+
.cmd_rcgr = 0x4c07c,
415
+
.mnd_width = 0,
416
+
.hid_width = 5,
417
+
.parent_map = gcc_parent_map_3,
418
+
.freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src,
419
+
.hw_clk_ctrl = true,
420
+
.clkr.hw.init = &(const struct clk_init_data) {
421
+
.name = "gcc_pcie_d_phy_rchng_clk_src",
422
+
.parent_data = gcc_parent_data_3,
423
+
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
424
+
.flags = CLK_SET_RATE_PARENT,
425
+
.ops = &clk_rcg2_shared_ops,
426
+
},
427
+
};
428
+
429
+
static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = {
430
+
.cmd_rcgr = 0x52094,
431
+
.mnd_width = 0,
432
+
.hid_width = 5,
433
+
.parent_map = gcc_parent_map_0,
434
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
435
+
.hw_clk_ctrl = true,
436
+
.clkr.hw.init = &(const struct clk_init_data) {
437
+
.name = "gcc_pcie_noc_refgen_clk_src",
438
+
.parent_data = gcc_parent_data_0,
439
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
440
+
.flags = CLK_SET_RATE_PARENT,
441
+
.ops = &clk_rcg2_shared_ops,
442
+
},
443
+
};
444
+
445
+
static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = {
446
+
.cmd_rcgr = 0x520ac,
447
+
.mnd_width = 0,
448
+
.hid_width = 5,
449
+
.parent_map = gcc_parent_map_0,
450
+
.freq_tbl = ftbl_gcc_pcie_a_aux_clk_src,
451
+
.hw_clk_ctrl = true,
452
+
.clkr.hw.init = &(const struct clk_init_data) {
453
+
.name = "gcc_pcie_noc_safety_clk_src",
454
+
.parent_data = gcc_parent_data_0,
455
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
456
+
.flags = CLK_SET_RATE_PARENT,
457
+
.ops = &clk_rcg2_shared_ops,
458
+
},
459
+
};
460
+
461
+
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
462
+
F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0),
463
+
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
464
+
{ }
465
+
};
466
+
467
+
static struct clk_rcg2 gcc_pdm2_clk_src = {
468
+
.cmd_rcgr = 0x1a010,
469
+
.mnd_width = 0,
470
+
.hid_width = 5,
471
+
.parent_map = gcc_parent_map_0,
472
+
.freq_tbl = ftbl_gcc_pdm2_clk_src,
473
+
.hw_clk_ctrl = true,
474
+
.clkr.hw.init = &(const struct clk_init_data) {
475
+
.name = "gcc_pdm2_clk_src",
476
+
.parent_data = gcc_parent_data_0,
477
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
478
+
.flags = CLK_SET_RATE_PARENT,
479
+
.ops = &clk_rcg2_shared_ops,
480
+
},
481
+
};
482
+
483
+
static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = {
484
+
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
485
+
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
486
+
F(19200000, P_BI_TCXO, 1, 0, 0),
487
+
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
488
+
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
489
+
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
490
+
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
491
+
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
492
+
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
493
+
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
494
+
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
495
+
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
496
+
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
497
+
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
498
+
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
499
+
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
500
+
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
501
+
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
502
+
{ }
503
+
};
504
+
505
+
static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
506
+
.name = "gcc_qupv3_wrap3_qspi_ref_clk_src",
507
+
.parent_data = gcc_parent_data_0,
508
+
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
509
+
.flags = CLK_SET_RATE_PARENT,
510
+
.ops = &clk_rcg2_shared_no_init_park_ops,
511
+
};
512
+
513
+
static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
514
+
.cmd_rcgr = 0x23174,
515
+
.mnd_width = 16,
516
+
.hid_width = 5,
517
+
.parent_map = gcc_parent_map_0,
518
+
.freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src,
519
+
.hw_clk_ctrl = true,
520
+
.clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init,
521
+
};
522
+
523
+
static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = {
524
+
.reg = 0x2316c,
525
+
.shift = 0,
526
+
.width = 4,
527
+
.clkr.hw.init = &(const struct clk_init_data) {
528
+
.name = "gcc_qupv3_wrap3_s0_clk_src",
529
+
.parent_hws = (const struct clk_hw*[]) {
530
+
&gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
531
+
},
532
+
.num_parents = 1,
533
+
.flags = CLK_SET_RATE_PARENT,
534
+
.ops = &clk_regmap_div_ro_ops,
535
+
},
536
+
};
537
+
538
+
static struct clk_branch gcc_boot_rom_ahb_clk = {
539
+
.halt_reg = 0x1f004,
540
+
.halt_check = BRANCH_HALT,
541
+
.clkr = {
542
+
.enable_reg = 0x1f004,
543
+
.enable_mask = BIT(0),
544
+
.hw.init = &(const struct clk_init_data) {
545
+
.name = "gcc_boot_rom_ahb_clk",
546
+
.ops = &clk_branch2_ops,
547
+
},
548
+
},
549
+
};
550
+
551
+
static struct clk_branch gcc_gp1_clk = {
552
+
.halt_reg = 0x30000,
553
+
.halt_check = BRANCH_HALT,
554
+
.clkr = {
555
+
.enable_reg = 0x30000,
556
+
.enable_mask = BIT(0),
557
+
.hw.init = &(const struct clk_init_data) {
558
+
.name = "gcc_gp1_clk",
559
+
.parent_hws = (const struct clk_hw*[]) {
560
+
&gcc_gp1_clk_src.clkr.hw,
561
+
},
562
+
.num_parents = 1,
563
+
.flags = CLK_SET_RATE_PARENT,
564
+
.ops = &clk_branch2_ops,
565
+
},
566
+
},
567
+
};
568
+
569
+
static struct clk_branch gcc_gp2_clk = {
570
+
.halt_reg = 0x31000,
571
+
.halt_check = BRANCH_HALT,
572
+
.clkr = {
573
+
.enable_reg = 0x31000,
574
+
.enable_mask = BIT(0),
575
+
.hw.init = &(const struct clk_init_data) {
576
+
.name = "gcc_gp2_clk",
577
+
.parent_hws = (const struct clk_hw*[]) {
578
+
&gcc_gp2_clk_src.clkr.hw,
579
+
},
580
+
.num_parents = 1,
581
+
.flags = CLK_SET_RATE_PARENT,
582
+
.ops = &clk_branch2_ops,
583
+
},
584
+
},
585
+
};
586
+
587
+
static struct clk_branch gcc_mmu_0_tcu_vote_clk = {
588
+
.halt_reg = 0x7d094,
589
+
.halt_check = BRANCH_HALT_VOTED,
590
+
.clkr = {
591
+
.enable_reg = 0x7d094,
592
+
.enable_mask = BIT(0),
593
+
.hw.init = &(const struct clk_init_data) {
594
+
.name = "gcc_mmu_0_tcu_vote_clk",
595
+
.ops = &clk_branch2_ops,
596
+
},
597
+
},
598
+
};
599
+
600
+
static struct clk_branch gcc_pcie_a_aux_clk = {
601
+
.halt_reg = 0x49058,
602
+
.halt_check = BRANCH_HALT_VOTED,
603
+
.hwcg_reg = 0x49058,
604
+
.hwcg_bit = 1,
605
+
.clkr = {
606
+
.enable_reg = 0x9d008,
607
+
.enable_mask = BIT(14),
608
+
.hw.init = &(const struct clk_init_data) {
609
+
.name = "gcc_pcie_a_aux_clk",
610
+
.parent_hws = (const struct clk_hw*[]) {
611
+
&gcc_pcie_a_aux_clk_src.clkr.hw,
612
+
},
613
+
.num_parents = 1,
614
+
.flags = CLK_SET_RATE_PARENT,
615
+
.ops = &clk_branch2_ops,
616
+
},
617
+
},
618
+
};
619
+
620
+
static struct clk_branch gcc_pcie_a_cfg_ahb_clk = {
621
+
.halt_reg = 0x49054,
622
+
.halt_check = BRANCH_HALT_VOTED,
623
+
.hwcg_reg = 0x49054,
624
+
.hwcg_bit = 1,
625
+
.clkr = {
626
+
.enable_reg = 0x9d008,
627
+
.enable_mask = BIT(13),
628
+
.hw.init = &(const struct clk_init_data) {
629
+
.name = "gcc_pcie_a_cfg_ahb_clk",
630
+
.ops = &clk_branch2_ops,
631
+
},
632
+
},
633
+
};
634
+
635
+
static struct clk_branch gcc_pcie_a_dti_qtc_clk = {
636
+
.halt_reg = 0x49018,
637
+
.halt_check = BRANCH_HALT_SKIP,
638
+
.hwcg_reg = 0x49018,
639
+
.hwcg_bit = 1,
640
+
.clkr = {
641
+
.enable_reg = 0x9d008,
642
+
.enable_mask = BIT(8),
643
+
.hw.init = &(const struct clk_init_data) {
644
+
.name = "gcc_pcie_a_dti_qtc_clk",
645
+
.ops = &clk_branch2_ops,
646
+
},
647
+
},
648
+
};
649
+
650
+
static struct clk_branch gcc_pcie_a_mstr_axi_clk = {
651
+
.halt_reg = 0x49040,
652
+
.halt_check = BRANCH_HALT_SKIP,
653
+
.hwcg_reg = 0x49040,
654
+
.hwcg_bit = 1,
655
+
.clkr = {
656
+
.enable_reg = 0x9d008,
657
+
.enable_mask = BIT(12),
658
+
.hw.init = &(const struct clk_init_data) {
659
+
.name = "gcc_pcie_a_mstr_axi_clk",
660
+
.ops = &clk_branch2_ops,
661
+
},
662
+
},
663
+
};
664
+
665
+
static struct clk_branch gcc_pcie_a_phy_aux_clk = {
666
+
.halt_reg = 0x4d01c,
667
+
.halt_check = BRANCH_HALT_VOTED,
668
+
.clkr = {
669
+
.enable_reg = 0x9d010,
670
+
.enable_mask = BIT(12),
671
+
.hw.init = &(const struct clk_init_data) {
672
+
.name = "gcc_pcie_a_phy_aux_clk",
673
+
.parent_hws = (const struct clk_hw*[]) {
674
+
&gcc_pcie_a_phy_aux_clk_src.clkr.hw,
675
+
},
676
+
.num_parents = 1,
677
+
.flags = CLK_SET_RATE_PARENT,
678
+
.ops = &clk_branch2_ops,
679
+
},
680
+
},
681
+
};
682
+
683
+
static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
684
+
.halt_reg = 0x49078,
685
+
.halt_check = BRANCH_HALT_VOTED,
686
+
.hwcg_reg = 0x49078,
687
+
.hwcg_bit = 1,
688
+
.clkr = {
689
+
.enable_reg = 0x9d008,
690
+
.enable_mask = BIT(16),
691
+
.hw.init = &(const struct clk_init_data) {
692
+
.name = "gcc_pcie_a_phy_rchng_clk",
693
+
.parent_hws = (const struct clk_hw*[]) {
694
+
&gcc_pcie_a_phy_rchng_clk_src.clkr.hw,
695
+
},
696
+
.num_parents = 1,
697
+
.flags = CLK_SET_RATE_PARENT,
698
+
.ops = &clk_branch2_ops,
699
+
},
700
+
},
701
+
};
702
+
703
+
static struct clk_branch gcc_pcie_a_pipe_clk = {
704
+
.halt_reg = 0x49068,
705
+
.halt_check = BRANCH_HALT_VOTED,
706
+
.hwcg_reg = 0x49068,
707
+
.hwcg_bit = 1,
708
+
.clkr = {
709
+
.enable_reg = 0x9d008,
710
+
.enable_mask = BIT(15),
711
+
.hw.init = &(const struct clk_init_data) {
712
+
.name = "gcc_pcie_a_pipe_clk",
713
+
.parent_hws = (const struct clk_hw*[]) {
714
+
&gcc_pcie_a_pipe_clk_src.clkr.hw,
715
+
},
716
+
.num_parents = 1,
717
+
.flags = CLK_SET_RATE_PARENT,
718
+
.ops = &clk_branch2_ops,
719
+
},
720
+
},
721
+
};
722
+
723
+
static struct clk_branch gcc_pcie_a_slv_axi_clk = {
724
+
.halt_reg = 0x4902c,
725
+
.halt_check = BRANCH_HALT_VOTED,
726
+
.hwcg_reg = 0x4902c,
727
+
.hwcg_bit = 1,
728
+
.clkr = {
729
+
.enable_reg = 0x9d008,
730
+
.enable_mask = BIT(11),
731
+
.hw.init = &(const struct clk_init_data) {
732
+
.name = "gcc_pcie_a_slv_axi_clk",
733
+
.ops = &clk_branch2_ops,
734
+
},
735
+
},
736
+
};
737
+
738
+
static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = {
739
+
.halt_reg = 0x49024,
740
+
.halt_check = BRANCH_HALT_VOTED,
741
+
.hwcg_reg = 0x49024,
742
+
.hwcg_bit = 1,
743
+
.clkr = {
744
+
.enable_reg = 0x9d008,
745
+
.enable_mask = BIT(10),
746
+
.hw.init = &(const struct clk_init_data) {
747
+
.name = "gcc_pcie_a_slv_q2a_axi_clk",
748
+
.ops = &clk_branch2_ops,
749
+
},
750
+
},
751
+
};
752
+
753
+
static struct clk_branch gcc_pcie_b_aux_clk = {
754
+
.halt_reg = 0x4a058,
755
+
.halt_check = BRANCH_HALT_VOTED,
756
+
.clkr = {
757
+
.enable_reg = 0x9d008,
758
+
.enable_mask = BIT(23),
759
+
.hw.init = &(const struct clk_init_data) {
760
+
.name = "gcc_pcie_b_aux_clk",
761
+
.parent_hws = (const struct clk_hw*[]) {
762
+
&gcc_pcie_b_aux_clk_src.clkr.hw,
763
+
},
764
+
.num_parents = 1,
765
+
.flags = CLK_SET_RATE_PARENT,
766
+
.ops = &clk_branch2_ops,
767
+
},
768
+
},
769
+
};
770
+
771
+
static struct clk_branch gcc_pcie_b_cfg_ahb_clk = {
772
+
.halt_reg = 0x4a054,
773
+
.halt_check = BRANCH_HALT_VOTED,
774
+
.hwcg_reg = 0x4a054,
775
+
.hwcg_bit = 1,
776
+
.clkr = {
777
+
.enable_reg = 0x9d008,
778
+
.enable_mask = BIT(22),
779
+
.hw.init = &(const struct clk_init_data) {
780
+
.name = "gcc_pcie_b_cfg_ahb_clk",
781
+
.ops = &clk_branch2_ops,
782
+
},
783
+
},
784
+
};
785
+
786
+
static struct clk_branch gcc_pcie_b_dti_qtc_clk = {
787
+
.halt_reg = 0x4a018,
788
+
.halt_check = BRANCH_HALT_SKIP,
789
+
.hwcg_reg = 0x4a018,
790
+
.hwcg_bit = 1,
791
+
.clkr = {
792
+
.enable_reg = 0x9d008,
793
+
.enable_mask = BIT(17),
794
+
.hw.init = &(const struct clk_init_data) {
795
+
.name = "gcc_pcie_b_dti_qtc_clk",
796
+
.ops = &clk_branch2_ops,
797
+
},
798
+
},
799
+
};
800
+
801
+
static struct clk_branch gcc_pcie_b_mstr_axi_clk = {
802
+
.halt_reg = 0x4a040,
803
+
.halt_check = BRANCH_HALT_SKIP,
804
+
.hwcg_reg = 0x4a040,
805
+
.hwcg_bit = 1,
806
+
.clkr = {
807
+
.enable_reg = 0x9d008,
808
+
.enable_mask = BIT(21),
809
+
.hw.init = &(const struct clk_init_data) {
810
+
.name = "gcc_pcie_b_mstr_axi_clk",
811
+
.ops = &clk_branch2_ops,
812
+
},
813
+
},
814
+
};
815
+
816
+
static struct clk_branch gcc_pcie_b_phy_aux_clk = {
817
+
.halt_reg = 0x4e01c,
818
+
.halt_check = BRANCH_HALT_VOTED,
819
+
.clkr = {
820
+
.enable_reg = 0x9d010,
821
+
.enable_mask = BIT(13),
822
+
.hw.init = &(const struct clk_init_data) {
823
+
.name = "gcc_pcie_b_phy_aux_clk",
824
+
.parent_hws = (const struct clk_hw*[]) {
825
+
&gcc_pcie_b_phy_aux_clk_src.clkr.hw,
826
+
},
827
+
.num_parents = 1,
828
+
.flags = CLK_SET_RATE_PARENT,
829
+
.ops = &clk_branch2_ops,
830
+
},
831
+
},
832
+
};
833
+
834
+
static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
835
+
.halt_reg = 0x4a078,
836
+
.halt_check = BRANCH_HALT_VOTED,
837
+
.clkr = {
838
+
.enable_reg = 0x9d008,
839
+
.enable_mask = BIT(25),
840
+
.hw.init = &(const struct clk_init_data) {
841
+
.name = "gcc_pcie_b_phy_rchng_clk",
842
+
.parent_hws = (const struct clk_hw*[]) {
843
+
&gcc_pcie_b_phy_rchng_clk_src.clkr.hw,
844
+
},
845
+
.num_parents = 1,
846
+
.flags = CLK_SET_RATE_PARENT,
847
+
.ops = &clk_branch2_ops,
848
+
},
849
+
},
850
+
};
851
+
852
+
static struct clk_branch gcc_pcie_b_pipe_clk = {
853
+
.halt_reg = 0x4a068,
854
+
.halt_check = BRANCH_HALT_VOTED,
855
+
.clkr = {
856
+
.enable_reg = 0x9d008,
857
+
.enable_mask = BIT(24),
858
+
.hw.init = &(const struct clk_init_data) {
859
+
.name = "gcc_pcie_b_pipe_clk",
860
+
.parent_hws = (const struct clk_hw*[]) {
861
+
&gcc_pcie_b_pipe_clk_src.clkr.hw,
862
+
},
863
+
.num_parents = 1,
864
+
.flags = CLK_SET_RATE_PARENT,
865
+
.ops = &clk_branch2_ops,
866
+
},
867
+
},
868
+
};
869
+
870
+
static struct clk_branch gcc_pcie_b_slv_axi_clk = {
871
+
.halt_reg = 0x4a02c,
872
+
.halt_check = BRANCH_HALT_VOTED,
873
+
.hwcg_reg = 0x4a02c,
874
+
.hwcg_bit = 1,
875
+
.clkr = {
876
+
.enable_reg = 0x9d008,
877
+
.enable_mask = BIT(20),
878
+
.hw.init = &(const struct clk_init_data) {
879
+
.name = "gcc_pcie_b_slv_axi_clk",
880
+
.ops = &clk_branch2_ops,
881
+
},
882
+
},
883
+
};
884
+
885
+
static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = {
886
+
.halt_reg = 0x4a024,
887
+
.halt_check = BRANCH_HALT_VOTED,
888
+
.clkr = {
889
+
.enable_reg = 0x9d008,
890
+
.enable_mask = BIT(19),
891
+
.hw.init = &(const struct clk_init_data) {
892
+
.name = "gcc_pcie_b_slv_q2a_axi_clk",
893
+
.ops = &clk_branch2_ops,
894
+
},
895
+
},
896
+
};
897
+
898
+
static struct clk_branch gcc_pcie_c_aux_clk = {
899
+
.halt_reg = 0x4b058,
900
+
.halt_check = BRANCH_HALT_VOTED,
901
+
.clkr = {
902
+
.enable_reg = 0x9d010,
903
+
.enable_mask = BIT(0),
904
+
.hw.init = &(const struct clk_init_data) {
905
+
.name = "gcc_pcie_c_aux_clk",
906
+
.parent_hws = (const struct clk_hw*[]) {
907
+
&gcc_pcie_c_aux_clk_src.clkr.hw,
908
+
},
909
+
.num_parents = 1,
910
+
.flags = CLK_SET_RATE_PARENT,
911
+
.ops = &clk_branch2_ops,
912
+
},
913
+
},
914
+
};
915
+
916
+
static struct clk_branch gcc_pcie_c_cfg_ahb_clk = {
917
+
.halt_reg = 0x4b054,
918
+
.halt_check = BRANCH_HALT_VOTED,
919
+
.hwcg_reg = 0x4b054,
920
+
.hwcg_bit = 1,
921
+
.clkr = {
922
+
.enable_reg = 0x9d008,
923
+
.enable_mask = BIT(31),
924
+
.hw.init = &(const struct clk_init_data) {
925
+
.name = "gcc_pcie_c_cfg_ahb_clk",
926
+
.ops = &clk_branch2_ops,
927
+
},
928
+
},
929
+
};
930
+
931
+
static struct clk_branch gcc_pcie_c_dti_qtc_clk = {
932
+
.halt_reg = 0x4b018,
933
+
.halt_check = BRANCH_HALT_SKIP,
934
+
.hwcg_reg = 0x4b018,
935
+
.hwcg_bit = 1,
936
+
.clkr = {
937
+
.enable_reg = 0x9d008,
938
+
.enable_mask = BIT(26),
939
+
.hw.init = &(const struct clk_init_data) {
940
+
.name = "gcc_pcie_c_dti_qtc_clk",
941
+
.ops = &clk_branch2_ops,
942
+
},
943
+
},
944
+
};
945
+
946
+
static struct clk_branch gcc_pcie_c_mstr_axi_clk = {
947
+
.halt_reg = 0x4b040,
948
+
.halt_check = BRANCH_HALT_SKIP,
949
+
.hwcg_reg = 0x4b040,
950
+
.hwcg_bit = 1,
951
+
.clkr = {
952
+
.enable_reg = 0x9d008,
953
+
.enable_mask = BIT(30),
954
+
.hw.init = &(const struct clk_init_data) {
955
+
.name = "gcc_pcie_c_mstr_axi_clk",
956
+
.ops = &clk_branch2_ops,
957
+
},
958
+
},
959
+
};
960
+
961
+
static struct clk_branch gcc_pcie_c_phy_aux_clk = {
962
+
.halt_reg = 0x4f01c,
963
+
.halt_check = BRANCH_HALT_VOTED,
964
+
.clkr = {
965
+
.enable_reg = 0x9d010,
966
+
.enable_mask = BIT(14),
967
+
.hw.init = &(const struct clk_init_data) {
968
+
.name = "gcc_pcie_c_phy_aux_clk",
969
+
.parent_hws = (const struct clk_hw*[]) {
970
+
&gcc_pcie_c_phy_aux_clk_src.clkr.hw,
971
+
},
972
+
.num_parents = 1,
973
+
.flags = CLK_SET_RATE_PARENT,
974
+
.ops = &clk_branch2_ops,
975
+
},
976
+
},
977
+
};
978
+
979
+
static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
980
+
.halt_reg = 0x4b078,
981
+
.halt_check = BRANCH_HALT_VOTED,
982
+
.clkr = {
983
+
.enable_reg = 0x9d010,
984
+
.enable_mask = BIT(2),
985
+
.hw.init = &(const struct clk_init_data) {
986
+
.name = "gcc_pcie_c_phy_rchng_clk",
987
+
.parent_hws = (const struct clk_hw*[]) {
988
+
&gcc_pcie_c_phy_rchng_clk_src.clkr.hw,
989
+
},
990
+
.num_parents = 1,
991
+
.flags = CLK_SET_RATE_PARENT,
992
+
.ops = &clk_branch2_ops,
993
+
},
994
+
},
995
+
};
996
+
997
+
static struct clk_branch gcc_pcie_c_pipe_clk = {
998
+
.halt_reg = 0x4b068,
999
+
.halt_check = BRANCH_HALT_VOTED,
1000
+
.clkr = {
1001
+
.enable_reg = 0x9d010,
1002
+
.enable_mask = BIT(1),
1003
+
.hw.init = &(const struct clk_init_data) {
1004
+
.name = "gcc_pcie_c_pipe_clk",
1005
+
.parent_hws = (const struct clk_hw*[]) {
1006
+
&gcc_pcie_c_pipe_clk_src.clkr.hw,
1007
+
},
1008
+
.num_parents = 1,
1009
+
.flags = CLK_SET_RATE_PARENT,
1010
+
.ops = &clk_branch2_ops,
1011
+
},
1012
+
},
1013
+
};
1014
+
1015
+
static struct clk_branch gcc_pcie_c_slv_axi_clk = {
1016
+
.halt_reg = 0x4b02c,
1017
+
.halt_check = BRANCH_HALT_VOTED,
1018
+
.hwcg_reg = 0x4b02c,
1019
+
.hwcg_bit = 1,
1020
+
.clkr = {
1021
+
.enable_reg = 0x9d008,
1022
+
.enable_mask = BIT(29),
1023
+
.hw.init = &(const struct clk_init_data) {
1024
+
.name = "gcc_pcie_c_slv_axi_clk",
1025
+
.ops = &clk_branch2_ops,
1026
+
},
1027
+
},
1028
+
};
1029
+
1030
+
static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = {
1031
+
.halt_reg = 0x4b024,
1032
+
.halt_check = BRANCH_HALT_VOTED,
1033
+
.clkr = {
1034
+
.enable_reg = 0x9d008,
1035
+
.enable_mask = BIT(28),
1036
+
.hw.init = &(const struct clk_init_data) {
1037
+
.name = "gcc_pcie_c_slv_q2a_axi_clk",
1038
+
.ops = &clk_branch2_ops,
1039
+
},
1040
+
},
1041
+
};
1042
+
1043
+
static struct clk_branch gcc_pcie_d_aux_clk = {
1044
+
.halt_reg = 0x4c058,
1045
+
.halt_check = BRANCH_HALT_VOTED,
1046
+
.clkr = {
1047
+
.enable_reg = 0x9d010,
1048
+
.enable_mask = BIT(9),
1049
+
.hw.init = &(const struct clk_init_data) {
1050
+
.name = "gcc_pcie_d_aux_clk",
1051
+
.parent_hws = (const struct clk_hw*[]) {
1052
+
&gcc_pcie_d_aux_clk_src.clkr.hw,
1053
+
},
1054
+
.num_parents = 1,
1055
+
.flags = CLK_SET_RATE_PARENT,
1056
+
.ops = &clk_branch2_ops,
1057
+
},
1058
+
},
1059
+
};
1060
+
1061
+
static struct clk_branch gcc_pcie_d_cfg_ahb_clk = {
1062
+
.halt_reg = 0x4c054,
1063
+
.halt_check = BRANCH_HALT_VOTED,
1064
+
.hwcg_reg = 0x4c054,
1065
+
.hwcg_bit = 1,
1066
+
.clkr = {
1067
+
.enable_reg = 0x9d010,
1068
+
.enable_mask = BIT(8),
1069
+
.hw.init = &(const struct clk_init_data) {
1070
+
.name = "gcc_pcie_d_cfg_ahb_clk",
1071
+
.ops = &clk_branch2_ops,
1072
+
},
1073
+
},
1074
+
};
1075
+
1076
+
static struct clk_branch gcc_pcie_d_dti_qtc_clk = {
1077
+
.halt_reg = 0x4c018,
1078
+
.halt_check = BRANCH_HALT_SKIP,
1079
+
.hwcg_reg = 0x4c018,
1080
+
.hwcg_bit = 1,
1081
+
.clkr = {
1082
+
.enable_reg = 0x9d010,
1083
+
.enable_mask = BIT(3),
1084
+
.hw.init = &(const struct clk_init_data) {
1085
+
.name = "gcc_pcie_d_dti_qtc_clk",
1086
+
.ops = &clk_branch2_ops,
1087
+
},
1088
+
},
1089
+
};
1090
+
1091
+
static struct clk_branch gcc_pcie_d_mstr_axi_clk = {
1092
+
.halt_reg = 0x4c040,
1093
+
.halt_check = BRANCH_HALT_SKIP,
1094
+
.hwcg_reg = 0x4c040,
1095
+
.hwcg_bit = 1,
1096
+
.clkr = {
1097
+
.enable_reg = 0x9d010,
1098
+
.enable_mask = BIT(7),
1099
+
.hw.init = &(const struct clk_init_data) {
1100
+
.name = "gcc_pcie_d_mstr_axi_clk",
1101
+
.ops = &clk_branch2_ops,
1102
+
},
1103
+
},
1104
+
};
1105
+
1106
+
static struct clk_branch gcc_pcie_d_phy_aux_clk = {
1107
+
.halt_reg = 0x5001c,
1108
+
.halt_check = BRANCH_HALT_VOTED,
1109
+
.clkr = {
1110
+
.enable_reg = 0x9d010,
1111
+
.enable_mask = BIT(16),
1112
+
.hw.init = &(const struct clk_init_data) {
1113
+
.name = "gcc_pcie_d_phy_aux_clk",
1114
+
.parent_hws = (const struct clk_hw*[]) {
1115
+
&gcc_pcie_d_phy_aux_clk_src.clkr.hw,
1116
+
},
1117
+
.num_parents = 1,
1118
+
.flags = CLK_SET_RATE_PARENT,
1119
+
.ops = &clk_branch2_ops,
1120
+
},
1121
+
},
1122
+
};
1123
+
1124
+
static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
1125
+
.halt_reg = 0x4c078,
1126
+
.halt_check = BRANCH_HALT_VOTED,
1127
+
.clkr = {
1128
+
.enable_reg = 0x9d010,
1129
+
.enable_mask = BIT(11),
1130
+
.hw.init = &(const struct clk_init_data) {
1131
+
.name = "gcc_pcie_d_phy_rchng_clk",
1132
+
.parent_hws = (const struct clk_hw*[]) {
1133
+
&gcc_pcie_d_phy_rchng_clk_src.clkr.hw,
1134
+
},
1135
+
.num_parents = 1,
1136
+
.flags = CLK_SET_RATE_PARENT,
1137
+
.ops = &clk_branch2_ops,
1138
+
},
1139
+
},
1140
+
};
1141
+
1142
+
static struct clk_branch gcc_pcie_d_pipe_clk = {
1143
+
.halt_reg = 0x4c068,
1144
+
.halt_check = BRANCH_HALT_VOTED,
1145
+
.clkr = {
1146
+
.enable_reg = 0x9d010,
1147
+
.enable_mask = BIT(10),
1148
+
.hw.init = &(const struct clk_init_data) {
1149
+
.name = "gcc_pcie_d_pipe_clk",
1150
+
.parent_hws = (const struct clk_hw*[]) {
1151
+
&gcc_pcie_d_pipe_clk_src.clkr.hw,
1152
+
},
1153
+
.num_parents = 1,
1154
+
.flags = CLK_SET_RATE_PARENT,
1155
+
.ops = &clk_branch2_ops,
1156
+
},
1157
+
},
1158
+
};
1159
+
1160
+
static struct clk_branch gcc_pcie_d_slv_axi_clk = {
1161
+
.halt_reg = 0x4c02c,
1162
+
.halt_check = BRANCH_HALT_VOTED,
1163
+
.hwcg_reg = 0x4c02c,
1164
+
.hwcg_bit = 1,
1165
+
.clkr = {
1166
+
.enable_reg = 0x9d010,
1167
+
.enable_mask = BIT(6),
1168
+
.hw.init = &(const struct clk_init_data) {
1169
+
.name = "gcc_pcie_d_slv_axi_clk",
1170
+
.ops = &clk_branch2_ops,
1171
+
},
1172
+
},
1173
+
};
1174
+
1175
+
static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = {
1176
+
.halt_reg = 0x4c024,
1177
+
.halt_check = BRANCH_HALT_VOTED,
1178
+
.clkr = {
1179
+
.enable_reg = 0x9d010,
1180
+
.enable_mask = BIT(5),
1181
+
.hw.init = &(const struct clk_init_data) {
1182
+
.name = "gcc_pcie_d_slv_q2a_axi_clk",
1183
+
.ops = &clk_branch2_ops,
1184
+
},
1185
+
},
1186
+
};
1187
+
1188
+
static struct clk_branch gcc_pcie_link_ahb_clk = {
1189
+
.halt_reg = 0x52464,
1190
+
.halt_check = BRANCH_HALT,
1191
+
.clkr = {
1192
+
.enable_reg = 0x52464,
1193
+
.enable_mask = BIT(0),
1194
+
.hw.init = &(const struct clk_init_data) {
1195
+
.name = "gcc_pcie_link_ahb_clk",
1196
+
.ops = &clk_branch2_ops,
1197
+
},
1198
+
},
1199
+
};
1200
+
1201
+
static struct clk_branch gcc_pcie_link_xo_clk = {
1202
+
.halt_reg = 0x52468,
1203
+
.halt_check = BRANCH_HALT_VOTED,
1204
+
.hwcg_reg = 0x52468,
1205
+
.hwcg_bit = 1,
1206
+
.clkr = {
1207
+
.enable_reg = 0x52468,
1208
+
.enable_mask = BIT(0),
1209
+
.hw.init = &(const struct clk_init_data) {
1210
+
.name = "gcc_pcie_link_xo_clk",
1211
+
.ops = &clk_branch2_ops,
1212
+
},
1213
+
},
1214
+
};
1215
+
1216
+
static struct clk_branch gcc_pcie_noc_async_bridge_clk = {
1217
+
.halt_reg = 0x52048,
1218
+
.halt_check = BRANCH_HALT_SKIP,
1219
+
.hwcg_reg = 0x52048,
1220
+
.hwcg_bit = 1,
1221
+
.clkr = {
1222
+
.enable_reg = 0x9d018,
1223
+
.enable_mask = BIT(18),
1224
+
.hw.init = &(const struct clk_init_data) {
1225
+
.name = "gcc_pcie_noc_async_bridge_clk",
1226
+
.ops = &clk_branch2_ops,
1227
+
},
1228
+
},
1229
+
};
1230
+
1231
+
static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = {
1232
+
.halt_reg = 0x52040,
1233
+
.halt_check = BRANCH_HALT_VOTED,
1234
+
.hwcg_reg = 0x52040,
1235
+
.hwcg_bit = 1,
1236
+
.clkr = {
1237
+
.enable_reg = 0x9d010,
1238
+
.enable_mask = BIT(24),
1239
+
.hw.init = &(const struct clk_init_data) {
1240
+
.name = "gcc_pcie_noc_cnoc_sf_qx_clk",
1241
+
.ops = &clk_branch2_ops,
1242
+
},
1243
+
},
1244
+
};
1245
+
1246
+
static struct clk_branch gcc_pcie_noc_m_cfg_clk = {
1247
+
.halt_reg = 0x52060,
1248
+
.halt_check = BRANCH_HALT_VOTED,
1249
+
.hwcg_reg = 0x52060,
1250
+
.hwcg_bit = 1,
1251
+
.clkr = {
1252
+
.enable_reg = 0x9d018,
1253
+
.enable_mask = BIT(4),
1254
+
.hw.init = &(const struct clk_init_data) {
1255
+
.name = "gcc_pcie_noc_m_cfg_clk",
1256
+
.ops = &clk_branch2_ops,
1257
+
},
1258
+
},
1259
+
};
1260
+
1261
+
static struct clk_branch gcc_pcie_noc_m_pdb_clk = {
1262
+
.halt_reg = 0x52084,
1263
+
.halt_check = BRANCH_HALT_VOTED,
1264
+
.hwcg_reg = 0x52084,
1265
+
.hwcg_bit = 1,
1266
+
.clkr = {
1267
+
.enable_reg = 0x9d018,
1268
+
.enable_mask = BIT(8),
1269
+
.hw.init = &(const struct clk_init_data) {
1270
+
.name = "gcc_pcie_noc_m_pdb_clk",
1271
+
.ops = &clk_branch2_ops,
1272
+
},
1273
+
},
1274
+
};
1275
+
1276
+
static struct clk_branch gcc_pcie_noc_mstr_axi_clk = {
1277
+
.halt_reg = 0x52050,
1278
+
.halt_check = BRANCH_HALT_SKIP,
1279
+
.hwcg_reg = 0x52050,
1280
+
.hwcg_bit = 1,
1281
+
.clkr = {
1282
+
.enable_reg = 0x9d010,
1283
+
.enable_mask = BIT(25),
1284
+
.hw.init = &(const struct clk_init_data) {
1285
+
.name = "gcc_pcie_noc_mstr_axi_clk",
1286
+
.ops = &clk_branch2_ops,
1287
+
},
1288
+
},
1289
+
};
1290
+
1291
+
static struct clk_branch gcc_pcie_noc_pwrctl_clk = {
1292
+
.halt_reg = 0x52080,
1293
+
.halt_check = BRANCH_HALT_VOTED,
1294
+
.clkr = {
1295
+
.enable_reg = 0x9d018,
1296
+
.enable_mask = BIT(7),
1297
+
.hw.init = &(const struct clk_init_data) {
1298
+
.name = "gcc_pcie_noc_pwrctl_clk",
1299
+
.ops = &clk_branch2_ops,
1300
+
},
1301
+
},
1302
+
};
1303
+
1304
+
static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = {
1305
+
.halt_reg = 0x52074,
1306
+
.halt_check = BRANCH_HALT_VOTED,
1307
+
.clkr = {
1308
+
.enable_reg = 0x9d010,
1309
+
.enable_mask = BIT(19),
1310
+
.hw.init = &(const struct clk_init_data) {
1311
+
.name = "gcc_pcie_noc_qosgen_extref_clk",
1312
+
.ops = &clk_branch2_ops,
1313
+
},
1314
+
},
1315
+
};
1316
+
1317
+
static struct clk_branch gcc_pcie_noc_refgen_clk = {
1318
+
.halt_reg = 0x52078,
1319
+
.halt_check = BRANCH_HALT,
1320
+
.clkr = {
1321
+
.enable_reg = 0x52078,
1322
+
.enable_mask = BIT(0),
1323
+
.hw.init = &(const struct clk_init_data) {
1324
+
.name = "gcc_pcie_noc_refgen_clk",
1325
+
.parent_hws = (const struct clk_hw*[]) {
1326
+
&gcc_pcie_noc_refgen_clk_src.clkr.hw,
1327
+
},
1328
+
.num_parents = 1,
1329
+
.flags = CLK_SET_RATE_PARENT,
1330
+
.ops = &clk_branch2_ops,
1331
+
},
1332
+
},
1333
+
};
1334
+
1335
+
static struct clk_branch gcc_pcie_noc_s_cfg_clk = {
1336
+
.halt_reg = 0x52064,
1337
+
.halt_check = BRANCH_HALT_VOTED,
1338
+
.clkr = {
1339
+
.enable_reg = 0x9d018,
1340
+
.enable_mask = BIT(5),
1341
+
.hw.init = &(const struct clk_init_data) {
1342
+
.name = "gcc_pcie_noc_s_cfg_clk",
1343
+
.ops = &clk_branch2_ops,
1344
+
},
1345
+
},
1346
+
};
1347
+
1348
+
static struct clk_branch gcc_pcie_noc_s_pdb_clk = {
1349
+
.halt_reg = 0x5208c,
1350
+
.halt_check = BRANCH_HALT_VOTED,
1351
+
.hwcg_reg = 0x5208c,
1352
+
.hwcg_bit = 1,
1353
+
.clkr = {
1354
+
.enable_reg = 0x9d018,
1355
+
.enable_mask = BIT(9),
1356
+
.hw.init = &(const struct clk_init_data) {
1357
+
.name = "gcc_pcie_noc_s_pdb_clk",
1358
+
.ops = &clk_branch2_ops,
1359
+
},
1360
+
},
1361
+
};
1362
+
1363
+
static struct clk_branch gcc_pcie_noc_safety_clk = {
1364
+
.halt_reg = 0x5207c,
1365
+
.halt_check = BRANCH_HALT,
1366
+
.clkr = {
1367
+
.enable_reg = 0x5207c,
1368
+
.enable_mask = BIT(0),
1369
+
.hw.init = &(const struct clk_init_data) {
1370
+
.name = "gcc_pcie_noc_safety_clk",
1371
+
.parent_hws = (const struct clk_hw*[]) {
1372
+
&gcc_pcie_noc_safety_clk_src.clkr.hw,
1373
+
},
1374
+
.num_parents = 1,
1375
+
.flags = CLK_SET_RATE_PARENT,
1376
+
.ops = &clk_branch2_ops,
1377
+
},
1378
+
},
1379
+
};
1380
+
1381
+
static struct clk_branch gcc_pcie_noc_slave_axi_clk = {
1382
+
.halt_reg = 0x52058,
1383
+
.halt_check = BRANCH_HALT_VOTED,
1384
+
.hwcg_reg = 0x52058,
1385
+
.hwcg_bit = 1,
1386
+
.clkr = {
1387
+
.enable_reg = 0x9d010,
1388
+
.enable_mask = BIT(26),
1389
+
.hw.init = &(const struct clk_init_data) {
1390
+
.name = "gcc_pcie_noc_slave_axi_clk",
1391
+
.ops = &clk_branch2_ops,
1392
+
},
1393
+
},
1394
+
};
1395
+
1396
+
static struct clk_branch gcc_pcie_noc_tsctr_clk = {
1397
+
.halt_reg = 0x52070,
1398
+
.halt_check = BRANCH_HALT_VOTED,
1399
+
.clkr = {
1400
+
.enable_reg = 0x9d010,
1401
+
.enable_mask = BIT(18),
1402
+
.hw.init = &(const struct clk_init_data) {
1403
+
.name = "gcc_pcie_noc_tsctr_clk",
1404
+
.ops = &clk_branch2_ops,
1405
+
},
1406
+
},
1407
+
};
1408
+
1409
+
static struct clk_branch gcc_pcie_noc_xo_clk = {
1410
+
.halt_reg = 0x52068,
1411
+
.halt_check = BRANCH_HALT_VOTED,
1412
+
.clkr = {
1413
+
.enable_reg = 0x9d018,
1414
+
.enable_mask = BIT(6),
1415
+
.hw.init = &(const struct clk_init_data) {
1416
+
.name = "gcc_pcie_noc_xo_clk",
1417
+
.ops = &clk_branch2_ops,
1418
+
},
1419
+
},
1420
+
};
1421
+
1422
+
static struct clk_branch gcc_pdm2_clk = {
1423
+
.halt_reg = 0x1a00c,
1424
+
.halt_check = BRANCH_HALT,
1425
+
.clkr = {
1426
+
.enable_reg = 0x1a00c,
1427
+
.enable_mask = BIT(0),
1428
+
.hw.init = &(const struct clk_init_data) {
1429
+
.name = "gcc_pdm2_clk",
1430
+
.parent_hws = (const struct clk_hw*[]) {
1431
+
&gcc_pdm2_clk_src.clkr.hw,
1432
+
},
1433
+
.num_parents = 1,
1434
+
.flags = CLK_SET_RATE_PARENT,
1435
+
.ops = &clk_branch2_ops,
1436
+
},
1437
+
},
1438
+
};
1439
+
1440
+
static struct clk_branch gcc_pdm_ahb_clk = {
1441
+
.halt_reg = 0x1a004,
1442
+
.halt_check = BRANCH_HALT_VOTED,
1443
+
.hwcg_reg = 0x1a004,
1444
+
.hwcg_bit = 1,
1445
+
.clkr = {
1446
+
.enable_reg = 0x1a004,
1447
+
.enable_mask = BIT(0),
1448
+
.hw.init = &(const struct clk_init_data) {
1449
+
.name = "gcc_pdm_ahb_clk",
1450
+
.ops = &clk_branch2_ops,
1451
+
},
1452
+
},
1453
+
};
1454
+
1455
+
static struct clk_branch gcc_pdm_xo4_clk = {
1456
+
.halt_reg = 0x1a008,
1457
+
.halt_check = BRANCH_HALT,
1458
+
.clkr = {
1459
+
.enable_reg = 0x1a008,
1460
+
.enable_mask = BIT(0),
1461
+
.hw.init = &(const struct clk_init_data) {
1462
+
.name = "gcc_pdm_xo4_clk",
1463
+
.ops = &clk_branch2_ops,
1464
+
},
1465
+
},
1466
+
};
1467
+
1468
+
static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
1469
+
.halt_reg = 0x23020,
1470
+
.halt_check = BRANCH_HALT_VOTED,
1471
+
.clkr = {
1472
+
.enable_reg = 0x9d000,
1473
+
.enable_mask = BIT(24),
1474
+
.hw.init = &(const struct clk_init_data) {
1475
+
.name = "gcc_qupv3_wrap3_core_2x_clk",
1476
+
.ops = &clk_branch2_ops,
1477
+
},
1478
+
},
1479
+
};
1480
+
1481
+
static struct clk_branch gcc_qupv3_wrap3_core_clk = {
1482
+
.halt_reg = 0x2300c,
1483
+
.halt_check = BRANCH_HALT_VOTED,
1484
+
.clkr = {
1485
+
.enable_reg = 0x9d000,
1486
+
.enable_mask = BIT(23),
1487
+
.hw.init = &(const struct clk_init_data) {
1488
+
.name = "gcc_qupv3_wrap3_core_clk",
1489
+
.ops = &clk_branch2_ops,
1490
+
},
1491
+
},
1492
+
};
1493
+
1494
+
static struct clk_branch gcc_qupv3_wrap3_m_clk = {
1495
+
.halt_reg = 0x23004,
1496
+
.halt_check = BRANCH_HALT_VOTED,
1497
+
.hwcg_reg = 0x23004,
1498
+
.hwcg_bit = 1,
1499
+
.clkr = {
1500
+
.enable_reg = 0x9d000,
1501
+
.enable_mask = BIT(22),
1502
+
.hw.init = &(const struct clk_init_data) {
1503
+
.name = "gcc_qupv3_wrap3_m_clk",
1504
+
.ops = &clk_branch2_ops,
1505
+
},
1506
+
},
1507
+
};
1508
+
1509
+
static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = {
1510
+
.halt_reg = 0x23170,
1511
+
.halt_check = BRANCH_HALT_VOTED,
1512
+
.clkr = {
1513
+
.enable_reg = 0x9d000,
1514
+
.enable_mask = BIT(26),
1515
+
.hw.init = &(const struct clk_init_data) {
1516
+
.name = "gcc_qupv3_wrap3_qspi_ref_clk",
1517
+
.parent_hws = (const struct clk_hw*[]) {
1518
+
&gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
1519
+
},
1520
+
.num_parents = 1,
1521
+
.flags = CLK_SET_RATE_PARENT,
1522
+
.ops = &clk_branch2_ops,
1523
+
},
1524
+
},
1525
+
};
1526
+
1527
+
static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
1528
+
.halt_reg = 0x2315c,
1529
+
.halt_check = BRANCH_HALT_VOTED,
1530
+
.clkr = {
1531
+
.enable_reg = 0x9d000,
1532
+
.enable_mask = BIT(25),
1533
+
.hw.init = &(const struct clk_init_data) {
1534
+
.name = "gcc_qupv3_wrap3_s0_clk",
1535
+
.parent_hws = (const struct clk_hw*[]) {
1536
+
&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
1537
+
},
1538
+
.num_parents = 1,
1539
+
.flags = CLK_SET_RATE_PARENT,
1540
+
.ops = &clk_branch2_ops,
1541
+
},
1542
+
},
1543
+
};
1544
+
1545
+
static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = {
1546
+
.halt_reg = 0x23008,
1547
+
.halt_check = BRANCH_HALT_VOTED,
1548
+
.hwcg_reg = 0x23008,
1549
+
.hwcg_bit = 1,
1550
+
.clkr = {
1551
+
.enable_reg = 0x9d010,
1552
+
.enable_mask = BIT(15),
1553
+
.hw.init = &(const struct clk_init_data) {
1554
+
.name = "gcc_qupv3_wrap3_s_ahb_clk",
1555
+
.ops = &clk_branch2_ops,
1556
+
},
1557
+
},
1558
+
};
1559
+
1560
+
static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = {
1561
+
.halt_reg = 0x7d0b8,
1562
+
.halt_check = BRANCH_HALT_VOTED,
1563
+
.clkr = {
1564
+
.enable_reg = 0x7d0b8,
1565
+
.enable_mask = BIT(0),
1566
+
.hw.init = &(const struct clk_init_data) {
1567
+
.name = "gcc_smmu_pcie_qtc_vote_clk",
1568
+
.ops = &clk_branch2_ops,
1569
+
},
1570
+
},
1571
+
};
1572
+
1573
+
static struct gdsc gcc_pcie_a_gdsc = {
1574
+
.gdscr = 0x49004,
1575
+
.en_rest_wait_val = 0x2,
1576
+
.en_few_wait_val = 0x2,
1577
+
.clk_dis_wait_val = 0xf,
1578
+
.collapse_ctrl = 0x8d02c,
1579
+
.collapse_mask = BIT(1),
1580
+
.pd = {
1581
+
.name = "gcc_pcie_a_gdsc",
1582
+
},
1583
+
.pwrsts = PWRSTS_OFF_ON,
1584
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1585
+
};
1586
+
1587
+
static struct gdsc gcc_pcie_a_phy_gdsc = {
1588
+
.gdscr = 0x4d004,
1589
+
.en_rest_wait_val = 0x2,
1590
+
.en_few_wait_val = 0x2,
1591
+
.clk_dis_wait_val = 0x2,
1592
+
.collapse_ctrl = 0x8d02c,
1593
+
.collapse_mask = BIT(5),
1594
+
.pd = {
1595
+
.name = "gcc_pcie_a_phy_gdsc",
1596
+
},
1597
+
.pwrsts = PWRSTS_OFF_ON,
1598
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1599
+
};
1600
+
1601
+
static struct gdsc gcc_pcie_b_gdsc = {
1602
+
.gdscr = 0x4a004,
1603
+
.en_rest_wait_val = 0x2,
1604
+
.en_few_wait_val = 0x2,
1605
+
.clk_dis_wait_val = 0xf,
1606
+
.collapse_ctrl = 0x8d02c,
1607
+
.collapse_mask = BIT(2),
1608
+
.pd = {
1609
+
.name = "gcc_pcie_b_gdsc",
1610
+
},
1611
+
.pwrsts = PWRSTS_OFF_ON,
1612
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1613
+
};
1614
+
1615
+
static struct gdsc gcc_pcie_b_phy_gdsc = {
1616
+
.gdscr = 0x4e004,
1617
+
.en_rest_wait_val = 0x2,
1618
+
.en_few_wait_val = 0x2,
1619
+
.clk_dis_wait_val = 0x2,
1620
+
.collapse_ctrl = 0x8d02c,
1621
+
.collapse_mask = BIT(6),
1622
+
.pd = {
1623
+
.name = "gcc_pcie_b_phy_gdsc",
1624
+
},
1625
+
.pwrsts = PWRSTS_OFF_ON,
1626
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1627
+
};
1628
+
1629
+
static struct gdsc gcc_pcie_c_gdsc = {
1630
+
.gdscr = 0x4b004,
1631
+
.en_rest_wait_val = 0x2,
1632
+
.en_few_wait_val = 0x2,
1633
+
.clk_dis_wait_val = 0xf,
1634
+
.collapse_ctrl = 0x8d02c,
1635
+
.collapse_mask = BIT(3),
1636
+
.pd = {
1637
+
.name = "gcc_pcie_c_gdsc",
1638
+
},
1639
+
.pwrsts = PWRSTS_OFF_ON,
1640
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1641
+
};
1642
+
1643
+
static struct gdsc gcc_pcie_c_phy_gdsc = {
1644
+
.gdscr = 0x4f004,
1645
+
.en_rest_wait_val = 0x2,
1646
+
.en_few_wait_val = 0x2,
1647
+
.clk_dis_wait_val = 0x2,
1648
+
.collapse_ctrl = 0x8d02c,
1649
+
.collapse_mask = BIT(7),
1650
+
.pd = {
1651
+
.name = "gcc_pcie_c_phy_gdsc",
1652
+
},
1653
+
.pwrsts = PWRSTS_OFF_ON,
1654
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1655
+
};
1656
+
1657
+
static struct gdsc gcc_pcie_d_gdsc = {
1658
+
.gdscr = 0x4c004,
1659
+
.en_rest_wait_val = 0x2,
1660
+
.en_few_wait_val = 0x2,
1661
+
.clk_dis_wait_val = 0xf,
1662
+
.collapse_ctrl = 0x8d02c,
1663
+
.collapse_mask = BIT(4),
1664
+
.pd = {
1665
+
.name = "gcc_pcie_d_gdsc",
1666
+
},
1667
+
.pwrsts = PWRSTS_OFF_ON,
1668
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1669
+
};
1670
+
1671
+
static struct gdsc gcc_pcie_d_phy_gdsc = {
1672
+
.gdscr = 0x50004,
1673
+
.en_rest_wait_val = 0x2,
1674
+
.en_few_wait_val = 0x2,
1675
+
.clk_dis_wait_val = 0x2,
1676
+
.collapse_ctrl = 0x8d02c,
1677
+
.collapse_mask = BIT(8),
1678
+
.pd = {
1679
+
.name = "gcc_pcie_d_phy_gdsc",
1680
+
},
1681
+
.pwrsts = PWRSTS_OFF_ON,
1682
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1683
+
};
1684
+
1685
+
static struct gdsc gcc_pcie_noc_gdsc = {
1686
+
.gdscr = 0x52004,
1687
+
.gds_hw_ctrl = 0x52018,
1688
+
.en_rest_wait_val = 0x2,
1689
+
.en_few_wait_val = 0x2,
1690
+
.clk_dis_wait_val = 0xf,
1691
+
.collapse_ctrl = 0x8d02c,
1692
+
.collapse_mask = BIT(0),
1693
+
.pd = {
1694
+
.name = "gcc_pcie_noc_gdsc",
1695
+
},
1696
+
.pwrsts = PWRSTS_OFF_ON,
1697
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
1698
+
};
1699
+
1700
+
static struct clk_regmap *gcc_nord_clocks[] = {
1701
+
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1702
+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1703
+
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1704
+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1705
+
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1706
+
[GCC_GPLL0] = &gcc_gpll0.clkr,
1707
+
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
1708
+
[GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr,
1709
+
[GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr,
1710
+
[GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr,
1711
+
[GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr,
1712
+
[GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr,
1713
+
[GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr,
1714
+
[GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr,
1715
+
[GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr,
1716
+
[GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr,
1717
+
[GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr,
1718
+
[GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr,
1719
+
[GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr,
1720
+
[GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr,
1721
+
[GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr,
1722
+
[GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr,
1723
+
[GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr,
1724
+
[GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr,
1725
+
[GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr,
1726
+
[GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr,
1727
+
[GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr,
1728
+
[GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr,
1729
+
[GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr,
1730
+
[GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr,
1731
+
[GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr,
1732
+
[GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr,
1733
+
[GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr,
1734
+
[GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr,
1735
+
[GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr,
1736
+
[GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr,
1737
+
[GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr,
1738
+
[GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr,
1739
+
[GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr,
1740
+
[GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr,
1741
+
[GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr,
1742
+
[GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr,
1743
+
[GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr,
1744
+
[GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr,
1745
+
[GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr,
1746
+
[GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr,
1747
+
[GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr,
1748
+
[GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr,
1749
+
[GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr,
1750
+
[GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr,
1751
+
[GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr,
1752
+
[GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr,
1753
+
[GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr,
1754
+
[GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr,
1755
+
[GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr,
1756
+
[GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr,
1757
+
[GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr,
1758
+
[GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr,
1759
+
[GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr,
1760
+
[GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr,
1761
+
[GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr,
1762
+
[GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr,
1763
+
[GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr,
1764
+
[GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr,
1765
+
[GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr,
1766
+
[GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr,
1767
+
[GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr,
1768
+
[GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr,
1769
+
[GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr,
1770
+
[GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr,
1771
+
[GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr,
1772
+
[GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr,
1773
+
[GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr,
1774
+
[GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr,
1775
+
[GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr,
1776
+
[GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr,
1777
+
[GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr,
1778
+
[GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr,
1779
+
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1780
+
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1781
+
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1782
+
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1783
+
[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
1784
+
[GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
1785
+
[GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr,
1786
+
[GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr,
1787
+
[GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr,
1788
+
[GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
1789
+
[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
1790
+
[GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr,
1791
+
[GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr,
1792
+
};
1793
+
1794
+
static struct gdsc *gcc_nord_gdscs[] = {
1795
+
[GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc,
1796
+
[GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc,
1797
+
[GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc,
1798
+
[GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc,
1799
+
[GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc,
1800
+
[GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc,
1801
+
[GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc,
1802
+
[GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc,
1803
+
[GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc,
1804
+
};
1805
+
1806
+
static const struct qcom_reset_map gcc_nord_resets[] = {
1807
+
[GCC_PCIE_A_BCR] = { 0x49000 },
1808
+
[GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 },
1809
+
[GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c },
1810
+
[GCC_PCIE_A_PHY_BCR] = { 0x4d000 },
1811
+
[GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 },
1812
+
[GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 },
1813
+
[GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 },
1814
+
[GCC_PCIE_B_BCR] = { 0x4a000 },
1815
+
[GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 },
1816
+
[GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 },
1817
+
[GCC_PCIE_B_PHY_BCR] = { 0x4e000 },
1818
+
[GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 },
1819
+
[GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 },
1820
+
[GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c },
1821
+
[GCC_PCIE_C_BCR] = { 0x4b000 },
1822
+
[GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c },
1823
+
[GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 },
1824
+
[GCC_PCIE_C_PHY_BCR] = { 0x4f000 },
1825
+
[GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c },
1826
+
[GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 },
1827
+
[GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 },
1828
+
[GCC_PCIE_D_BCR] = { 0x4c000 },
1829
+
[GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 },
1830
+
[GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 },
1831
+
[GCC_PCIE_D_PHY_BCR] = { 0x50000 },
1832
+
[GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 },
1833
+
[GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 },
1834
+
[GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c },
1835
+
[GCC_PCIE_NOC_BCR] = { 0x52000 },
1836
+
[GCC_PDM_BCR] = { 0x1a000 },
1837
+
[GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 },
1838
+
[GCC_TCSR_PCIE_BCR] = { 0xb901c },
1839
+
};
1840
+
1841
+
static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = {
1842
+
DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),
1843
+
};
1844
+
1845
+
static const struct regmap_config gcc_nord_regmap_config = {
1846
+
.reg_bits = 32,
1847
+
.reg_stride = 4,
1848
+
.val_bits = 32,
1849
+
.max_register = 0x1f41f0,
1850
+
.fast_io = true,
1851
+
};
1852
+
1853
+
static struct qcom_cc_driver_data gcc_nord_driver_data = {
1854
+
.dfs_rcgs = gcc_nord_dfs_clocks,
1855
+
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
1856
+
};
1857
+
1858
+
static const struct qcom_cc_desc gcc_nord_desc = {
1859
+
.config = &gcc_nord_regmap_config,
1860
+
.clks = gcc_nord_clocks,
1861
+
.num_clks = ARRAY_SIZE(gcc_nord_clocks),
1862
+
.resets = gcc_nord_resets,
1863
+
.num_resets = ARRAY_SIZE(gcc_nord_resets),
1864
+
.gdscs = gcc_nord_gdscs,
1865
+
.num_gdscs = ARRAY_SIZE(gcc_nord_gdscs),
1866
+
.use_rpm = true,
1867
+
.driver_data = &gcc_nord_driver_data,
1868
+
};
1869
+
1870
+
static const struct of_device_id gcc_nord_match_table[] = {
1871
+
{ .compatible = "qcom,nord-gcc" },
1872
+
{ }
1873
+
};
1874
+
MODULE_DEVICE_TABLE(of, gcc_nord_match_table);
1875
+
1876
+
static int gcc_nord_probe(struct platform_device *pdev)
1877
+
{
1878
+
return qcom_cc_probe(pdev, &gcc_nord_desc);
1879
+
}
1880
+
1881
+
static struct platform_driver gcc_nord_driver = {
1882
+
.probe = gcc_nord_probe,
1883
+
.driver = {
1884
+
.name = "gcc-nord",
1885
+
.of_match_table = gcc_nord_match_table,
1886
+
},
1887
+
};
1888
+
1889
+
static int __init gcc_nord_init(void)
1890
+
{
1891
+
return platform_driver_register(&gcc_nord_driver);
1892
+
}
1893
+
subsys_initcall(gcc_nord_init);
1894
+
1895
+
static void __exit gcc_nord_exit(void)
1896
+
{
1897
+
platform_driver_unregister(&gcc_nord_driver);
1898
+
}
1899
+
module_exit(gcc_nord_exit);
1900
+
1901
+
MODULE_DESCRIPTION("QTI GCC NORD Driver");
1902
+
MODULE_LICENSE("GPL");
+1987
drivers/clk/qcom/negcc-nord.c
+1987
drivers/clk/qcom/negcc-nord.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,nord-negcc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-pll.h"
17
+
#include "clk-rcg.h"
18
+
#include "clk-regmap.h"
19
+
#include "clk-regmap-divider.h"
20
+
#include "clk-regmap-mux.h"
21
+
#include "clk-regmap-phy-mux.h"
22
+
#include "common.h"
23
+
#include "gdsc.h"
24
+
#include "reset.h"
25
+
26
+
enum {
27
+
DT_BI_TCXO,
28
+
DT_SLEEP_CLK,
29
+
DT_UFS_PHY_RX_SYMBOL_0_CLK,
30
+
DT_UFS_PHY_RX_SYMBOL_1_CLK,
31
+
DT_UFS_PHY_TX_SYMBOL_0_CLK,
32
+
DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
33
+
DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
34
+
};
35
+
36
+
enum {
37
+
P_BI_TCXO,
38
+
P_NE_GCC_GPLL0_OUT_EVEN,
39
+
P_NE_GCC_GPLL0_OUT_MAIN,
40
+
P_NE_GCC_GPLL2_OUT_MAIN,
41
+
P_SLEEP_CLK,
42
+
P_UFS_PHY_RX_SYMBOL_0_CLK,
43
+
P_UFS_PHY_RX_SYMBOL_1_CLK,
44
+
P_UFS_PHY_TX_SYMBOL_0_CLK,
45
+
P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK,
46
+
P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK,
47
+
};
48
+
49
+
static struct clk_alpha_pll ne_gcc_gpll0 = {
50
+
.offset = 0x0,
51
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
52
+
.clkr = {
53
+
.enable_reg = 0x0,
54
+
.enable_mask = BIT(0),
55
+
.hw.init = &(const struct clk_init_data) {
56
+
.name = "ne_gcc_gpll0",
57
+
.parent_data = &(const struct clk_parent_data) {
58
+
.index = DT_BI_TCXO,
59
+
},
60
+
.num_parents = 1,
61
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
62
+
},
63
+
},
64
+
};
65
+
66
+
static const struct clk_div_table post_div_table_ne_gcc_gpll0_out_even[] = {
67
+
{ 0x1, 2 },
68
+
{ }
69
+
};
70
+
71
+
static struct clk_alpha_pll_postdiv ne_gcc_gpll0_out_even = {
72
+
.offset = 0x0,
73
+
.post_div_shift = 10,
74
+
.post_div_table = post_div_table_ne_gcc_gpll0_out_even,
75
+
.num_post_div = ARRAY_SIZE(post_div_table_ne_gcc_gpll0_out_even),
76
+
.width = 4,
77
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
78
+
.clkr.hw.init = &(const struct clk_init_data) {
79
+
.name = "ne_gcc_gpll0_out_even",
80
+
.parent_hws = (const struct clk_hw*[]) {
81
+
&ne_gcc_gpll0.clkr.hw,
82
+
},
83
+
.num_parents = 1,
84
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
85
+
},
86
+
};
87
+
88
+
static struct clk_alpha_pll ne_gcc_gpll2 = {
89
+
.offset = 0x2000,
90
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
91
+
.clkr = {
92
+
.enable_reg = 0x0,
93
+
.enable_mask = BIT(2),
94
+
.hw.init = &(const struct clk_init_data) {
95
+
.name = "ne_gcc_gpll2",
96
+
.parent_data = &(const struct clk_parent_data) {
97
+
.index = DT_BI_TCXO,
98
+
},
99
+
.num_parents = 1,
100
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
101
+
},
102
+
},
103
+
};
104
+
105
+
static const struct parent_map ne_gcc_parent_map_0[] = {
106
+
{ P_BI_TCXO, 0 },
107
+
{ P_NE_GCC_GPLL0_OUT_MAIN, 1 },
108
+
};
109
+
110
+
static const struct clk_parent_data ne_gcc_parent_data_0[] = {
111
+
{ .index = DT_BI_TCXO },
112
+
{ .hw = &ne_gcc_gpll0.clkr.hw },
113
+
};
114
+
115
+
static const struct parent_map ne_gcc_parent_map_1[] = {
116
+
{ P_BI_TCXO, 0 },
117
+
{ P_NE_GCC_GPLL0_OUT_MAIN, 1 },
118
+
{ P_NE_GCC_GPLL0_OUT_EVEN, 5 },
119
+
};
120
+
121
+
static const struct clk_parent_data ne_gcc_parent_data_1[] = {
122
+
{ .index = DT_BI_TCXO },
123
+
{ .hw = &ne_gcc_gpll0.clkr.hw },
124
+
{ .hw = &ne_gcc_gpll0_out_even.clkr.hw },
125
+
};
126
+
127
+
static const struct parent_map ne_gcc_parent_map_2[] = {
128
+
{ P_BI_TCXO, 0 },
129
+
{ P_NE_GCC_GPLL0_OUT_MAIN, 1 },
130
+
{ P_NE_GCC_GPLL2_OUT_MAIN, 3 },
131
+
};
132
+
133
+
static const struct clk_parent_data ne_gcc_parent_data_2[] = {
134
+
{ .index = DT_BI_TCXO },
135
+
{ .hw = &ne_gcc_gpll0.clkr.hw },
136
+
{ .hw = &ne_gcc_gpll2.clkr.hw },
137
+
};
138
+
139
+
static const struct parent_map ne_gcc_parent_map_3[] = {
140
+
{ P_BI_TCXO, 0 },
141
+
{ P_SLEEP_CLK, 5 },
142
+
};
143
+
144
+
static const struct clk_parent_data ne_gcc_parent_data_3[] = {
145
+
{ .index = DT_BI_TCXO },
146
+
{ .index = DT_SLEEP_CLK },
147
+
};
148
+
149
+
static const struct parent_map ne_gcc_parent_map_4[] = {
150
+
{ P_BI_TCXO, 0 },
151
+
{ P_NE_GCC_GPLL0_OUT_MAIN, 1 },
152
+
{ P_SLEEP_CLK, 5 },
153
+
};
154
+
155
+
static const struct clk_parent_data ne_gcc_parent_data_4[] = {
156
+
{ .index = DT_BI_TCXO },
157
+
{ .hw = &ne_gcc_gpll0.clkr.hw },
158
+
{ .index = DT_SLEEP_CLK },
159
+
};
160
+
161
+
static const struct parent_map ne_gcc_parent_map_5[] = {
162
+
{ P_BI_TCXO, 0 },
163
+
};
164
+
165
+
static const struct clk_parent_data ne_gcc_parent_data_5[] = {
166
+
{ .index = DT_BI_TCXO },
167
+
};
168
+
169
+
static const struct parent_map ne_gcc_parent_map_6[] = {
170
+
{ P_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
171
+
{ P_BI_TCXO, 2 },
172
+
};
173
+
174
+
static const struct clk_parent_data ne_gcc_parent_data_6[] = {
175
+
{ .index = DT_USB3_PHY_WRAPPER_NE_GCC_USB31_PIPE_CLK },
176
+
{ .index = DT_BI_TCXO },
177
+
};
178
+
179
+
static const struct parent_map ne_gcc_parent_map_7[] = {
180
+
{ P_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK, 0 },
181
+
{ P_BI_TCXO, 2 },
182
+
};
183
+
184
+
static const struct clk_parent_data ne_gcc_parent_data_7[] = {
185
+
{ .index = DT_USB3_PHY_SEC_WRAPPER_NE_GCC_USB31_PIPE_CLK },
186
+
{ .index = DT_BI_TCXO },
187
+
};
188
+
189
+
static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_0_clk_src = {
190
+
.reg = 0x33068,
191
+
.clkr = {
192
+
.hw.init = &(const struct clk_init_data) {
193
+
.name = "ne_gcc_ufs_phy_rx_symbol_0_clk_src",
194
+
.parent_data = &(const struct clk_parent_data){
195
+
.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
196
+
},
197
+
.num_parents = 1,
198
+
.ops = &clk_regmap_phy_mux_ops,
199
+
},
200
+
},
201
+
};
202
+
203
+
static struct clk_regmap_phy_mux ne_gcc_ufs_phy_rx_symbol_1_clk_src = {
204
+
.reg = 0x330f0,
205
+
.clkr = {
206
+
.hw.init = &(const struct clk_init_data) {
207
+
.name = "ne_gcc_ufs_phy_rx_symbol_1_clk_src",
208
+
.parent_data = &(const struct clk_parent_data){
209
+
.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
210
+
},
211
+
.num_parents = 1,
212
+
.ops = &clk_regmap_phy_mux_ops,
213
+
},
214
+
},
215
+
};
216
+
217
+
static struct clk_regmap_phy_mux ne_gcc_ufs_phy_tx_symbol_0_clk_src = {
218
+
.reg = 0x33058,
219
+
.clkr = {
220
+
.hw.init = &(const struct clk_init_data) {
221
+
.name = "ne_gcc_ufs_phy_tx_symbol_0_clk_src",
222
+
.parent_data = &(const struct clk_parent_data){
223
+
.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
224
+
},
225
+
.num_parents = 1,
226
+
.ops = &clk_regmap_phy_mux_ops,
227
+
},
228
+
},
229
+
};
230
+
231
+
static struct clk_regmap_mux ne_gcc_usb3_prim_phy_pipe_clk_src = {
232
+
.reg = 0x2a078,
233
+
.shift = 0,
234
+
.width = 2,
235
+
.parent_map = ne_gcc_parent_map_6,
236
+
.clkr = {
237
+
.hw.init = &(const struct clk_init_data) {
238
+
.name = "ne_gcc_usb3_prim_phy_pipe_clk_src",
239
+
.parent_data = ne_gcc_parent_data_6,
240
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_6),
241
+
.ops = &clk_regmap_mux_closest_ops,
242
+
},
243
+
},
244
+
};
245
+
246
+
static struct clk_regmap_mux ne_gcc_usb3_sec_phy_pipe_clk_src = {
247
+
.reg = 0x2c078,
248
+
.shift = 0,
249
+
.width = 2,
250
+
.parent_map = ne_gcc_parent_map_7,
251
+
.clkr = {
252
+
.hw.init = &(const struct clk_init_data) {
253
+
.name = "ne_gcc_usb3_sec_phy_pipe_clk_src",
254
+
.parent_data = ne_gcc_parent_data_7,
255
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_7),
256
+
.ops = &clk_regmap_mux_closest_ops,
257
+
},
258
+
},
259
+
};
260
+
261
+
static const struct freq_tbl ftbl_ne_gcc_gp1_clk_src[] = {
262
+
F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
263
+
F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
264
+
F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
265
+
{ }
266
+
};
267
+
268
+
static struct clk_rcg2 ne_gcc_gp1_clk_src = {
269
+
.cmd_rcgr = 0x21004,
270
+
.mnd_width = 16,
271
+
.hid_width = 5,
272
+
.parent_map = ne_gcc_parent_map_4,
273
+
.freq_tbl = ftbl_ne_gcc_gp1_clk_src,
274
+
.hw_clk_ctrl = true,
275
+
.clkr.hw.init = &(const struct clk_init_data) {
276
+
.name = "ne_gcc_gp1_clk_src",
277
+
.parent_data = ne_gcc_parent_data_4,
278
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
279
+
.flags = CLK_SET_RATE_PARENT,
280
+
.ops = &clk_rcg2_shared_ops,
281
+
},
282
+
};
283
+
284
+
static struct clk_rcg2 ne_gcc_gp2_clk_src = {
285
+
.cmd_rcgr = 0x22004,
286
+
.mnd_width = 16,
287
+
.hid_width = 5,
288
+
.parent_map = ne_gcc_parent_map_4,
289
+
.freq_tbl = ftbl_ne_gcc_gp1_clk_src,
290
+
.hw_clk_ctrl = true,
291
+
.clkr.hw.init = &(const struct clk_init_data) {
292
+
.name = "ne_gcc_gp2_clk_src",
293
+
.parent_data = ne_gcc_parent_data_4,
294
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_4),
295
+
.flags = CLK_SET_RATE_PARENT,
296
+
.ops = &clk_rcg2_shared_ops,
297
+
},
298
+
};
299
+
300
+
static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s0_clk_src[] = {
301
+
F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
302
+
F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
303
+
F(19200000, P_BI_TCXO, 1, 0, 0),
304
+
F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
305
+
F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
306
+
F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
307
+
F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
308
+
F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
309
+
F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
310
+
F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
311
+
F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
312
+
F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
313
+
F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
314
+
F(102400000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 64, 375),
315
+
F(112000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 14, 75),
316
+
F(117964800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625),
317
+
F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
318
+
{ }
319
+
};
320
+
321
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s0_clk_src_init = {
322
+
.name = "ne_gcc_qupv3_wrap2_s0_clk_src",
323
+
.parent_data = ne_gcc_parent_data_0,
324
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
325
+
.flags = CLK_SET_RATE_PARENT,
326
+
.ops = &clk_rcg2_shared_no_init_park_ops,
327
+
};
328
+
329
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s0_clk_src = {
330
+
.cmd_rcgr = 0x3816c,
331
+
.mnd_width = 16,
332
+
.hid_width = 5,
333
+
.parent_map = ne_gcc_parent_map_0,
334
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
335
+
.hw_clk_ctrl = true,
336
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s0_clk_src_init,
337
+
};
338
+
339
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s1_clk_src_init = {
340
+
.name = "ne_gcc_qupv3_wrap2_s1_clk_src",
341
+
.parent_data = ne_gcc_parent_data_0,
342
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
343
+
.flags = CLK_SET_RATE_PARENT,
344
+
.ops = &clk_rcg2_shared_no_init_park_ops,
345
+
};
346
+
347
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s1_clk_src = {
348
+
.cmd_rcgr = 0x382a8,
349
+
.mnd_width = 16,
350
+
.hid_width = 5,
351
+
.parent_map = ne_gcc_parent_map_0,
352
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s0_clk_src,
353
+
.hw_clk_ctrl = true,
354
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s1_clk_src_init,
355
+
};
356
+
357
+
static const struct freq_tbl ftbl_ne_gcc_qupv3_wrap2_s2_clk_src[] = {
358
+
F(7372800, P_NE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
359
+
F(14745600, P_NE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
360
+
F(19200000, P_BI_TCXO, 1, 0, 0),
361
+
F(29491200, P_NE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
362
+
F(32000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
363
+
F(48000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
364
+
F(51200000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
365
+
F(64000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
366
+
F(66666667, P_NE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
367
+
F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
368
+
F(80000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
369
+
F(96000000, P_NE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
370
+
F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
371
+
{ }
372
+
};
373
+
374
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s2_clk_src_init = {
375
+
.name = "ne_gcc_qupv3_wrap2_s2_clk_src",
376
+
.parent_data = ne_gcc_parent_data_0,
377
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
378
+
.flags = CLK_SET_RATE_PARENT,
379
+
.ops = &clk_rcg2_shared_no_init_park_ops,
380
+
};
381
+
382
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s2_clk_src = {
383
+
.cmd_rcgr = 0x383e4,
384
+
.mnd_width = 16,
385
+
.hid_width = 5,
386
+
.parent_map = ne_gcc_parent_map_0,
387
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
388
+
.hw_clk_ctrl = true,
389
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s2_clk_src_init,
390
+
};
391
+
392
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s3_clk_src_init = {
393
+
.name = "ne_gcc_qupv3_wrap2_s3_clk_src",
394
+
.parent_data = ne_gcc_parent_data_0,
395
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
396
+
.flags = CLK_SET_RATE_PARENT,
397
+
.ops = &clk_rcg2_shared_no_init_park_ops,
398
+
};
399
+
400
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s3_clk_src = {
401
+
.cmd_rcgr = 0x38520,
402
+
.mnd_width = 16,
403
+
.hid_width = 5,
404
+
.parent_map = ne_gcc_parent_map_0,
405
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
406
+
.hw_clk_ctrl = true,
407
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s3_clk_src_init,
408
+
};
409
+
410
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s4_clk_src_init = {
411
+
.name = "ne_gcc_qupv3_wrap2_s4_clk_src",
412
+
.parent_data = ne_gcc_parent_data_0,
413
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
414
+
.flags = CLK_SET_RATE_PARENT,
415
+
.ops = &clk_rcg2_shared_no_init_park_ops,
416
+
};
417
+
418
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s4_clk_src = {
419
+
.cmd_rcgr = 0x3865c,
420
+
.mnd_width = 16,
421
+
.hid_width = 5,
422
+
.parent_map = ne_gcc_parent_map_0,
423
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
424
+
.hw_clk_ctrl = true,
425
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s4_clk_src_init,
426
+
};
427
+
428
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s5_clk_src_init = {
429
+
.name = "ne_gcc_qupv3_wrap2_s5_clk_src",
430
+
.parent_data = ne_gcc_parent_data_0,
431
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
432
+
.flags = CLK_SET_RATE_PARENT,
433
+
.ops = &clk_rcg2_shared_no_init_park_ops,
434
+
};
435
+
436
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s5_clk_src = {
437
+
.cmd_rcgr = 0x38798,
438
+
.mnd_width = 16,
439
+
.hid_width = 5,
440
+
.parent_map = ne_gcc_parent_map_0,
441
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
442
+
.hw_clk_ctrl = true,
443
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s5_clk_src_init,
444
+
};
445
+
446
+
static struct clk_init_data ne_gcc_qupv3_wrap2_s6_clk_src_init = {
447
+
.name = "ne_gcc_qupv3_wrap2_s6_clk_src",
448
+
.parent_data = ne_gcc_parent_data_0,
449
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
450
+
.flags = CLK_SET_RATE_PARENT,
451
+
.ops = &clk_rcg2_shared_no_init_park_ops,
452
+
};
453
+
454
+
static struct clk_rcg2 ne_gcc_qupv3_wrap2_s6_clk_src = {
455
+
.cmd_rcgr = 0x388d4,
456
+
.mnd_width = 16,
457
+
.hid_width = 5,
458
+
.parent_map = ne_gcc_parent_map_0,
459
+
.freq_tbl = ftbl_ne_gcc_qupv3_wrap2_s2_clk_src,
460
+
.hw_clk_ctrl = true,
461
+
.clkr.hw.init = &ne_gcc_qupv3_wrap2_s6_clk_src_init,
462
+
};
463
+
464
+
static const struct freq_tbl ftbl_ne_gcc_sdcc4_apps_clk_src[] = {
465
+
F(37500000, P_NE_GCC_GPLL0_OUT_MAIN, 16, 0, 0),
466
+
F(50000000, P_NE_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
467
+
F(100000000, P_NE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
468
+
{ }
469
+
};
470
+
471
+
static struct clk_rcg2 ne_gcc_sdcc4_apps_clk_src = {
472
+
.cmd_rcgr = 0x1801c,
473
+
.mnd_width = 8,
474
+
.hid_width = 5,
475
+
.parent_map = ne_gcc_parent_map_0,
476
+
.freq_tbl = ftbl_ne_gcc_sdcc4_apps_clk_src,
477
+
.hw_clk_ctrl = true,
478
+
.clkr.hw.init = &(const struct clk_init_data) {
479
+
.name = "ne_gcc_sdcc4_apps_clk_src",
480
+
.parent_data = ne_gcc_parent_data_0,
481
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
482
+
.flags = CLK_SET_RATE_PARENT,
483
+
.ops = &clk_rcg2_shared_floor_ops,
484
+
},
485
+
};
486
+
487
+
static const struct freq_tbl ftbl_ne_gcc_ufs_phy_axi_clk_src[] = {
488
+
F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
489
+
F(201500000, P_NE_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
490
+
F(300000000, P_NE_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
491
+
F(403000000, P_NE_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
492
+
{ }
493
+
};
494
+
495
+
static struct clk_rcg2 ne_gcc_ufs_phy_axi_clk_src = {
496
+
.cmd_rcgr = 0x33034,
497
+
.mnd_width = 8,
498
+
.hid_width = 5,
499
+
.parent_map = ne_gcc_parent_map_2,
500
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
501
+
.hw_clk_ctrl = true,
502
+
.clkr.hw.init = &(const struct clk_init_data) {
503
+
.name = "ne_gcc_ufs_phy_axi_clk_src",
504
+
.parent_data = ne_gcc_parent_data_2,
505
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
506
+
.flags = CLK_SET_RATE_PARENT,
507
+
.ops = &clk_rcg2_shared_ops,
508
+
},
509
+
};
510
+
511
+
static struct clk_rcg2 ne_gcc_ufs_phy_ice_core_clk_src = {
512
+
.cmd_rcgr = 0x3308c,
513
+
.mnd_width = 0,
514
+
.hid_width = 5,
515
+
.parent_map = ne_gcc_parent_map_2,
516
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
517
+
.hw_clk_ctrl = true,
518
+
.clkr.hw.init = &(const struct clk_init_data) {
519
+
.name = "ne_gcc_ufs_phy_ice_core_clk_src",
520
+
.parent_data = ne_gcc_parent_data_2,
521
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
522
+
.flags = CLK_SET_RATE_PARENT,
523
+
.ops = &clk_rcg2_shared_ops,
524
+
},
525
+
};
526
+
527
+
static const struct freq_tbl ftbl_ne_gcc_ufs_phy_phy_aux_clk_src[] = {
528
+
F(19200000, P_BI_TCXO, 1, 0, 0),
529
+
{ }
530
+
};
531
+
532
+
static struct clk_rcg2 ne_gcc_ufs_phy_phy_aux_clk_src = {
533
+
.cmd_rcgr = 0x330c0,
534
+
.mnd_width = 0,
535
+
.hid_width = 5,
536
+
.parent_map = ne_gcc_parent_map_5,
537
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
538
+
.hw_clk_ctrl = true,
539
+
.clkr.hw.init = &(const struct clk_init_data) {
540
+
.name = "ne_gcc_ufs_phy_phy_aux_clk_src",
541
+
.parent_data = ne_gcc_parent_data_5,
542
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_5),
543
+
.flags = CLK_SET_RATE_PARENT,
544
+
.ops = &clk_rcg2_shared_ops,
545
+
},
546
+
};
547
+
548
+
static struct clk_rcg2 ne_gcc_ufs_phy_unipro_core_clk_src = {
549
+
.cmd_rcgr = 0x330a4,
550
+
.mnd_width = 0,
551
+
.hid_width = 5,
552
+
.parent_map = ne_gcc_parent_map_2,
553
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_axi_clk_src,
554
+
.hw_clk_ctrl = true,
555
+
.clkr.hw.init = &(const struct clk_init_data) {
556
+
.name = "ne_gcc_ufs_phy_unipro_core_clk_src",
557
+
.parent_data = ne_gcc_parent_data_2,
558
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_2),
559
+
.flags = CLK_SET_RATE_PARENT,
560
+
.ops = &clk_rcg2_shared_ops,
561
+
},
562
+
};
563
+
564
+
static const struct freq_tbl ftbl_ne_gcc_usb20_master_clk_src[] = {
565
+
F(75000000, P_NE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
566
+
F(120000000, P_NE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
567
+
{ }
568
+
};
569
+
570
+
static struct clk_rcg2 ne_gcc_usb20_master_clk_src = {
571
+
.cmd_rcgr = 0x31030,
572
+
.mnd_width = 8,
573
+
.hid_width = 5,
574
+
.parent_map = ne_gcc_parent_map_0,
575
+
.freq_tbl = ftbl_ne_gcc_usb20_master_clk_src,
576
+
.hw_clk_ctrl = true,
577
+
.clkr.hw.init = &(const struct clk_init_data) {
578
+
.name = "ne_gcc_usb20_master_clk_src",
579
+
.parent_data = ne_gcc_parent_data_0,
580
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
581
+
.flags = CLK_SET_RATE_PARENT,
582
+
.ops = &clk_rcg2_shared_ops,
583
+
},
584
+
};
585
+
586
+
static struct clk_rcg2 ne_gcc_usb20_mock_utmi_clk_src = {
587
+
.cmd_rcgr = 0x31048,
588
+
.mnd_width = 0,
589
+
.hid_width = 5,
590
+
.parent_map = ne_gcc_parent_map_0,
591
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
592
+
.hw_clk_ctrl = true,
593
+
.clkr.hw.init = &(const struct clk_init_data) {
594
+
.name = "ne_gcc_usb20_mock_utmi_clk_src",
595
+
.parent_data = ne_gcc_parent_data_0,
596
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
597
+
.flags = CLK_SET_RATE_PARENT,
598
+
.ops = &clk_rcg2_shared_ops,
599
+
},
600
+
};
601
+
602
+
static const struct freq_tbl ftbl_ne_gcc_usb31_prim_master_clk_src[] = {
603
+
F(85714286, P_NE_GCC_GPLL0_OUT_MAIN, 7, 0, 0),
604
+
F(133333333, P_NE_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
605
+
F(200000000, P_NE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
606
+
F(240000000, P_NE_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
607
+
{ }
608
+
};
609
+
610
+
static struct clk_rcg2 ne_gcc_usb31_prim_master_clk_src = {
611
+
.cmd_rcgr = 0x2a038,
612
+
.mnd_width = 8,
613
+
.hid_width = 5,
614
+
.parent_map = ne_gcc_parent_map_1,
615
+
.freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src,
616
+
.hw_clk_ctrl = true,
617
+
.clkr.hw.init = &(const struct clk_init_data) {
618
+
.name = "ne_gcc_usb31_prim_master_clk_src",
619
+
.parent_data = ne_gcc_parent_data_1,
620
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_1),
621
+
.flags = CLK_SET_RATE_PARENT,
622
+
.ops = &clk_rcg2_shared_ops,
623
+
},
624
+
};
625
+
626
+
static struct clk_rcg2 ne_gcc_usb31_prim_mock_utmi_clk_src = {
627
+
.cmd_rcgr = 0x2a050,
628
+
.mnd_width = 0,
629
+
.hid_width = 5,
630
+
.parent_map = ne_gcc_parent_map_0,
631
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
632
+
.hw_clk_ctrl = true,
633
+
.clkr.hw.init = &(const struct clk_init_data) {
634
+
.name = "ne_gcc_usb31_prim_mock_utmi_clk_src",
635
+
.parent_data = ne_gcc_parent_data_0,
636
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
637
+
.flags = CLK_SET_RATE_PARENT,
638
+
.ops = &clk_rcg2_shared_ops,
639
+
},
640
+
};
641
+
642
+
static struct clk_rcg2 ne_gcc_usb31_sec_master_clk_src = {
643
+
.cmd_rcgr = 0x2c038,
644
+
.mnd_width = 8,
645
+
.hid_width = 5,
646
+
.parent_map = ne_gcc_parent_map_0,
647
+
.freq_tbl = ftbl_ne_gcc_usb31_prim_master_clk_src,
648
+
.hw_clk_ctrl = true,
649
+
.clkr.hw.init = &(const struct clk_init_data) {
650
+
.name = "ne_gcc_usb31_sec_master_clk_src",
651
+
.parent_data = ne_gcc_parent_data_0,
652
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
653
+
.flags = CLK_SET_RATE_PARENT,
654
+
.ops = &clk_rcg2_shared_ops,
655
+
},
656
+
};
657
+
658
+
static struct clk_rcg2 ne_gcc_usb31_sec_mock_utmi_clk_src = {
659
+
.cmd_rcgr = 0x2c050,
660
+
.mnd_width = 0,
661
+
.hid_width = 5,
662
+
.parent_map = ne_gcc_parent_map_0,
663
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
664
+
.hw_clk_ctrl = true,
665
+
.clkr.hw.init = &(const struct clk_init_data) {
666
+
.name = "ne_gcc_usb31_sec_mock_utmi_clk_src",
667
+
.parent_data = ne_gcc_parent_data_0,
668
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_0),
669
+
.flags = CLK_SET_RATE_PARENT,
670
+
.ops = &clk_rcg2_shared_ops,
671
+
},
672
+
};
673
+
674
+
static struct clk_rcg2 ne_gcc_usb3_prim_phy_aux_clk_src = {
675
+
.cmd_rcgr = 0x2a07c,
676
+
.mnd_width = 0,
677
+
.hid_width = 5,
678
+
.parent_map = ne_gcc_parent_map_3,
679
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
680
+
.hw_clk_ctrl = true,
681
+
.clkr.hw.init = &(const struct clk_init_data) {
682
+
.name = "ne_gcc_usb3_prim_phy_aux_clk_src",
683
+
.parent_data = ne_gcc_parent_data_3,
684
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_3),
685
+
.flags = CLK_SET_RATE_PARENT,
686
+
.ops = &clk_rcg2_shared_ops,
687
+
},
688
+
};
689
+
690
+
static struct clk_rcg2 ne_gcc_usb3_sec_phy_aux_clk_src = {
691
+
.cmd_rcgr = 0x2c07c,
692
+
.mnd_width = 0,
693
+
.hid_width = 5,
694
+
.parent_map = ne_gcc_parent_map_3,
695
+
.freq_tbl = ftbl_ne_gcc_ufs_phy_phy_aux_clk_src,
696
+
.hw_clk_ctrl = true,
697
+
.clkr.hw.init = &(const struct clk_init_data) {
698
+
.name = "ne_gcc_usb3_sec_phy_aux_clk_src",
699
+
.parent_data = ne_gcc_parent_data_3,
700
+
.num_parents = ARRAY_SIZE(ne_gcc_parent_data_3),
701
+
.flags = CLK_SET_RATE_PARENT,
702
+
.ops = &clk_rcg2_shared_ops,
703
+
},
704
+
};
705
+
706
+
static struct clk_regmap_div ne_gcc_usb20_mock_utmi_postdiv_clk_src = {
707
+
.reg = 0x31060,
708
+
.shift = 0,
709
+
.width = 4,
710
+
.clkr.hw.init = &(const struct clk_init_data) {
711
+
.name = "ne_gcc_usb20_mock_utmi_postdiv_clk_src",
712
+
.parent_hws = (const struct clk_hw*[]) {
713
+
&ne_gcc_usb20_mock_utmi_clk_src.clkr.hw,
714
+
},
715
+
.num_parents = 1,
716
+
.flags = CLK_SET_RATE_PARENT,
717
+
.ops = &clk_regmap_div_ro_ops,
718
+
},
719
+
};
720
+
721
+
static struct clk_regmap_div ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src = {
722
+
.reg = 0x2a068,
723
+
.shift = 0,
724
+
.width = 4,
725
+
.clkr.hw.init = &(const struct clk_init_data) {
726
+
.name = "ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src",
727
+
.parent_hws = (const struct clk_hw*[]) {
728
+
&ne_gcc_usb31_prim_mock_utmi_clk_src.clkr.hw,
729
+
},
730
+
.num_parents = 1,
731
+
.flags = CLK_SET_RATE_PARENT,
732
+
.ops = &clk_regmap_div_ro_ops,
733
+
},
734
+
};
735
+
736
+
static struct clk_regmap_div ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src = {
737
+
.reg = 0x2c068,
738
+
.shift = 0,
739
+
.width = 4,
740
+
.clkr.hw.init = &(const struct clk_init_data) {
741
+
.name = "ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src",
742
+
.parent_hws = (const struct clk_hw*[]) {
743
+
&ne_gcc_usb31_sec_mock_utmi_clk_src.clkr.hw,
744
+
},
745
+
.num_parents = 1,
746
+
.flags = CLK_SET_RATE_PARENT,
747
+
.ops = &clk_regmap_div_ro_ops,
748
+
},
749
+
};
750
+
751
+
static struct clk_branch ne_gcc_aggre_noc_ufs_phy_axi_clk = {
752
+
.halt_reg = 0x330f4,
753
+
.halt_check = BRANCH_HALT_VOTED,
754
+
.hwcg_reg = 0x330f4,
755
+
.hwcg_bit = 1,
756
+
.clkr = {
757
+
.enable_reg = 0x330f4,
758
+
.enable_mask = BIT(0),
759
+
.hw.init = &(const struct clk_init_data) {
760
+
.name = "ne_gcc_aggre_noc_ufs_phy_axi_clk",
761
+
.parent_hws = (const struct clk_hw*[]) {
762
+
&ne_gcc_ufs_phy_axi_clk_src.clkr.hw,
763
+
},
764
+
.num_parents = 1,
765
+
.flags = CLK_SET_RATE_PARENT,
766
+
.ops = &clk_branch2_ops,
767
+
},
768
+
},
769
+
};
770
+
771
+
static struct clk_branch ne_gcc_aggre_noc_usb2_axi_clk = {
772
+
.halt_reg = 0x31068,
773
+
.halt_check = BRANCH_HALT_VOTED,
774
+
.hwcg_reg = 0x31068,
775
+
.hwcg_bit = 1,
776
+
.clkr = {
777
+
.enable_reg = 0x31068,
778
+
.enable_mask = BIT(0),
779
+
.hw.init = &(const struct clk_init_data) {
780
+
.name = "ne_gcc_aggre_noc_usb2_axi_clk",
781
+
.parent_hws = (const struct clk_hw*[]) {
782
+
&ne_gcc_usb20_master_clk_src.clkr.hw,
783
+
},
784
+
.num_parents = 1,
785
+
.flags = CLK_SET_RATE_PARENT,
786
+
.ops = &clk_branch2_ops,
787
+
},
788
+
},
789
+
};
790
+
791
+
static struct clk_branch ne_gcc_aggre_noc_usb3_prim_axi_clk = {
792
+
.halt_reg = 0x2a098,
793
+
.halt_check = BRANCH_HALT_VOTED,
794
+
.hwcg_reg = 0x2a098,
795
+
.hwcg_bit = 1,
796
+
.clkr = {
797
+
.enable_reg = 0x2a098,
798
+
.enable_mask = BIT(0),
799
+
.hw.init = &(const struct clk_init_data) {
800
+
.name = "ne_gcc_aggre_noc_usb3_prim_axi_clk",
801
+
.parent_hws = (const struct clk_hw*[]) {
802
+
&ne_gcc_usb31_prim_master_clk_src.clkr.hw,
803
+
},
804
+
.num_parents = 1,
805
+
.flags = CLK_SET_RATE_PARENT,
806
+
.ops = &clk_branch2_ops,
807
+
},
808
+
},
809
+
};
810
+
811
+
static struct clk_branch ne_gcc_aggre_noc_usb3_sec_axi_clk = {
812
+
.halt_reg = 0x2c098,
813
+
.halt_check = BRANCH_HALT_VOTED,
814
+
.hwcg_reg = 0x2c098,
815
+
.hwcg_bit = 1,
816
+
.clkr = {
817
+
.enable_reg = 0x2c098,
818
+
.enable_mask = BIT(0),
819
+
.hw.init = &(const struct clk_init_data) {
820
+
.name = "ne_gcc_aggre_noc_usb3_sec_axi_clk",
821
+
.parent_hws = (const struct clk_hw*[]) {
822
+
&ne_gcc_usb31_sec_master_clk_src.clkr.hw,
823
+
},
824
+
.num_parents = 1,
825
+
.flags = CLK_SET_RATE_PARENT,
826
+
.ops = &clk_branch2_ops,
827
+
},
828
+
},
829
+
};
830
+
831
+
static struct clk_branch ne_gcc_ahb2phy_clk = {
832
+
.halt_reg = 0x30004,
833
+
.halt_check = BRANCH_HALT_VOTED,
834
+
.hwcg_reg = 0x30004,
835
+
.hwcg_bit = 1,
836
+
.clkr = {
837
+
.enable_reg = 0x30004,
838
+
.enable_mask = BIT(0),
839
+
.hw.init = &(const struct clk_init_data) {
840
+
.name = "ne_gcc_ahb2phy_clk",
841
+
.ops = &clk_branch2_ops,
842
+
},
843
+
},
844
+
};
845
+
846
+
static struct clk_branch ne_gcc_cnoc_usb2_axi_clk = {
847
+
.halt_reg = 0x31064,
848
+
.halt_check = BRANCH_HALT_VOTED,
849
+
.hwcg_reg = 0x31064,
850
+
.hwcg_bit = 1,
851
+
.clkr = {
852
+
.enable_reg = 0x31064,
853
+
.enable_mask = BIT(0),
854
+
.hw.init = &(const struct clk_init_data) {
855
+
.name = "ne_gcc_cnoc_usb2_axi_clk",
856
+
.parent_hws = (const struct clk_hw*[]) {
857
+
&ne_gcc_usb20_master_clk_src.clkr.hw,
858
+
},
859
+
.num_parents = 1,
860
+
.flags = CLK_SET_RATE_PARENT,
861
+
.ops = &clk_branch2_ops,
862
+
},
863
+
},
864
+
};
865
+
866
+
static struct clk_branch ne_gcc_cnoc_usb3_prim_axi_clk = {
867
+
.halt_reg = 0x2a094,
868
+
.halt_check = BRANCH_HALT_VOTED,
869
+
.hwcg_reg = 0x2a094,
870
+
.hwcg_bit = 1,
871
+
.clkr = {
872
+
.enable_reg = 0x2a094,
873
+
.enable_mask = BIT(0),
874
+
.hw.init = &(const struct clk_init_data) {
875
+
.name = "ne_gcc_cnoc_usb3_prim_axi_clk",
876
+
.parent_hws = (const struct clk_hw*[]) {
877
+
&ne_gcc_usb31_prim_master_clk_src.clkr.hw,
878
+
},
879
+
.num_parents = 1,
880
+
.flags = CLK_SET_RATE_PARENT,
881
+
.ops = &clk_branch2_ops,
882
+
},
883
+
},
884
+
};
885
+
886
+
static struct clk_branch ne_gcc_cnoc_usb3_sec_axi_clk = {
887
+
.halt_reg = 0x2c094,
888
+
.halt_check = BRANCH_HALT_VOTED,
889
+
.hwcg_reg = 0x2c094,
890
+
.hwcg_bit = 1,
891
+
.clkr = {
892
+
.enable_reg = 0x2c094,
893
+
.enable_mask = BIT(0),
894
+
.hw.init = &(const struct clk_init_data) {
895
+
.name = "ne_gcc_cnoc_usb3_sec_axi_clk",
896
+
.parent_hws = (const struct clk_hw*[]) {
897
+
&ne_gcc_usb31_sec_master_clk_src.clkr.hw,
898
+
},
899
+
.num_parents = 1,
900
+
.flags = CLK_SET_RATE_PARENT,
901
+
.ops = &clk_branch2_ops,
902
+
},
903
+
},
904
+
};
905
+
906
+
static struct clk_branch ne_gcc_frq_measure_ref_clk = {
907
+
.halt_reg = 0x20008,
908
+
.halt_check = BRANCH_HALT,
909
+
.clkr = {
910
+
.enable_reg = 0x20008,
911
+
.enable_mask = BIT(0),
912
+
.hw.init = &(const struct clk_init_data) {
913
+
.name = "ne_gcc_frq_measure_ref_clk",
914
+
.ops = &clk_branch2_ops,
915
+
},
916
+
},
917
+
};
918
+
919
+
static struct clk_branch ne_gcc_gp1_clk = {
920
+
.halt_reg = 0x21000,
921
+
.halt_check = BRANCH_HALT,
922
+
.clkr = {
923
+
.enable_reg = 0x21000,
924
+
.enable_mask = BIT(0),
925
+
.hw.init = &(const struct clk_init_data) {
926
+
.name = "ne_gcc_gp1_clk",
927
+
.parent_hws = (const struct clk_hw*[]) {
928
+
&ne_gcc_gp1_clk_src.clkr.hw,
929
+
},
930
+
.num_parents = 1,
931
+
.flags = CLK_SET_RATE_PARENT,
932
+
.ops = &clk_branch2_ops,
933
+
},
934
+
},
935
+
};
936
+
937
+
static struct clk_branch ne_gcc_gp2_clk = {
938
+
.halt_reg = 0x22000,
939
+
.halt_check = BRANCH_HALT,
940
+
.clkr = {
941
+
.enable_reg = 0x22000,
942
+
.enable_mask = BIT(0),
943
+
.hw.init = &(const struct clk_init_data) {
944
+
.name = "ne_gcc_gp2_clk",
945
+
.parent_hws = (const struct clk_hw*[]) {
946
+
&ne_gcc_gp2_clk_src.clkr.hw,
947
+
},
948
+
.num_parents = 1,
949
+
.flags = CLK_SET_RATE_PARENT,
950
+
.ops = &clk_branch2_ops,
951
+
},
952
+
},
953
+
};
954
+
955
+
static struct clk_branch ne_gcc_gpu_2_cfg_clk = {
956
+
.halt_reg = 0x34004,
957
+
.halt_check = BRANCH_HALT_VOTED,
958
+
.hwcg_reg = 0x34004,
959
+
.hwcg_bit = 1,
960
+
.clkr = {
961
+
.enable_reg = 0x34004,
962
+
.enable_mask = BIT(0),
963
+
.hw.init = &(const struct clk_init_data) {
964
+
.name = "ne_gcc_gpu_2_cfg_clk",
965
+
.ops = &clk_branch2_ops,
966
+
},
967
+
},
968
+
};
969
+
970
+
static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = {
971
+
.halt_check = BRANCH_HALT_DELAY,
972
+
.clkr = {
973
+
.enable_reg = 0x57000,
974
+
.enable_mask = BIT(19),
975
+
.hw.init = &(const struct clk_init_data) {
976
+
.name = "ne_gcc_gpu_2_gpll0_clk_src",
977
+
.parent_hws = (const struct clk_hw*[]) {
978
+
&ne_gcc_gpll0.clkr.hw,
979
+
},
980
+
.num_parents = 1,
981
+
.flags = CLK_SET_RATE_PARENT,
982
+
.ops = &clk_branch2_ops,
983
+
},
984
+
},
985
+
};
986
+
987
+
static struct clk_branch ne_gcc_gpu_2_gpll0_div_clk_src = {
988
+
.halt_check = BRANCH_HALT_DELAY,
989
+
.clkr = {
990
+
.enable_reg = 0x57000,
991
+
.enable_mask = BIT(20),
992
+
.hw.init = &(const struct clk_init_data) {
993
+
.name = "ne_gcc_gpu_2_gpll0_div_clk_src",
994
+
.parent_hws = (const struct clk_hw*[]) {
995
+
&ne_gcc_gpll0_out_even.clkr.hw,
996
+
},
997
+
.num_parents = 1,
998
+
.flags = CLK_SET_RATE_PARENT,
999
+
.ops = &clk_branch2_ops,
1000
+
},
1001
+
},
1002
+
};
1003
+
1004
+
static struct clk_branch ne_gcc_gpu_2_hscnoc_gfx_clk = {
1005
+
.halt_reg = 0x34014,
1006
+
.halt_check = BRANCH_HALT_VOTED,
1007
+
.hwcg_reg = 0x34014,
1008
+
.hwcg_bit = 1,
1009
+
.clkr = {
1010
+
.enable_reg = 0x34014,
1011
+
.enable_mask = BIT(0),
1012
+
.hw.init = &(const struct clk_init_data) {
1013
+
.name = "ne_gcc_gpu_2_hscnoc_gfx_clk",
1014
+
.ops = &clk_branch2_ops,
1015
+
},
1016
+
},
1017
+
};
1018
+
1019
+
static struct clk_branch ne_gcc_gpu_2_smmu_vote_clk = {
1020
+
.halt_reg = 0x57028,
1021
+
.halt_check = BRANCH_HALT_VOTED,
1022
+
.clkr = {
1023
+
.enable_reg = 0x57028,
1024
+
.enable_mask = BIT(0),
1025
+
.hw.init = &(const struct clk_init_data) {
1026
+
.name = "ne_gcc_gpu_2_smmu_vote_clk",
1027
+
.ops = &clk_branch2_ops,
1028
+
},
1029
+
},
1030
+
};
1031
+
1032
+
static struct clk_branch ne_gcc_qupv3_wrap2_core_2x_clk = {
1033
+
.halt_reg = 0x38020,
1034
+
.halt_check = BRANCH_HALT_VOTED,
1035
+
.clkr = {
1036
+
.enable_reg = 0x57008,
1037
+
.enable_mask = BIT(1),
1038
+
.hw.init = &(const struct clk_init_data) {
1039
+
.name = "ne_gcc_qupv3_wrap2_core_2x_clk",
1040
+
.ops = &clk_branch2_ops,
1041
+
},
1042
+
},
1043
+
};
1044
+
1045
+
static struct clk_branch ne_gcc_qupv3_wrap2_core_clk = {
1046
+
.halt_reg = 0x3800c,
1047
+
.halt_check = BRANCH_HALT_VOTED,
1048
+
.clkr = {
1049
+
.enable_reg = 0x57008,
1050
+
.enable_mask = BIT(0),
1051
+
.hw.init = &(const struct clk_init_data) {
1052
+
.name = "ne_gcc_qupv3_wrap2_core_clk",
1053
+
.ops = &clk_branch2_ops,
1054
+
},
1055
+
},
1056
+
};
1057
+
1058
+
static struct clk_branch ne_gcc_qupv3_wrap2_m_ahb_clk = {
1059
+
.halt_reg = 0x38004,
1060
+
.halt_check = BRANCH_HALT_VOTED,
1061
+
.hwcg_reg = 0x38004,
1062
+
.hwcg_bit = 1,
1063
+
.clkr = {
1064
+
.enable_reg = 0x57000,
1065
+
.enable_mask = BIT(30),
1066
+
.hw.init = &(const struct clk_init_data) {
1067
+
.name = "ne_gcc_qupv3_wrap2_m_ahb_clk",
1068
+
.ops = &clk_branch2_ops,
1069
+
},
1070
+
},
1071
+
};
1072
+
1073
+
static struct clk_branch ne_gcc_qupv3_wrap2_s0_clk = {
1074
+
.halt_reg = 0x3815c,
1075
+
.halt_check = BRANCH_HALT_VOTED,
1076
+
.clkr = {
1077
+
.enable_reg = 0x57008,
1078
+
.enable_mask = BIT(2),
1079
+
.hw.init = &(const struct clk_init_data) {
1080
+
.name = "ne_gcc_qupv3_wrap2_s0_clk",
1081
+
.parent_hws = (const struct clk_hw*[]) {
1082
+
&ne_gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
1083
+
},
1084
+
.num_parents = 1,
1085
+
.flags = CLK_SET_RATE_PARENT,
1086
+
.ops = &clk_branch2_ops,
1087
+
},
1088
+
},
1089
+
};
1090
+
1091
+
static struct clk_branch ne_gcc_qupv3_wrap2_s1_clk = {
1092
+
.halt_reg = 0x38298,
1093
+
.halt_check = BRANCH_HALT_VOTED,
1094
+
.clkr = {
1095
+
.enable_reg = 0x57008,
1096
+
.enable_mask = BIT(3),
1097
+
.hw.init = &(const struct clk_init_data) {
1098
+
.name = "ne_gcc_qupv3_wrap2_s1_clk",
1099
+
.parent_hws = (const struct clk_hw*[]) {
1100
+
&ne_gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
1101
+
},
1102
+
.num_parents = 1,
1103
+
.flags = CLK_SET_RATE_PARENT,
1104
+
.ops = &clk_branch2_ops,
1105
+
},
1106
+
},
1107
+
};
1108
+
1109
+
static struct clk_branch ne_gcc_qupv3_wrap2_s2_clk = {
1110
+
.halt_reg = 0x383d4,
1111
+
.halt_check = BRANCH_HALT_VOTED,
1112
+
.clkr = {
1113
+
.enable_reg = 0x57008,
1114
+
.enable_mask = BIT(4),
1115
+
.hw.init = &(const struct clk_init_data) {
1116
+
.name = "ne_gcc_qupv3_wrap2_s2_clk",
1117
+
.parent_hws = (const struct clk_hw*[]) {
1118
+
&ne_gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
1119
+
},
1120
+
.num_parents = 1,
1121
+
.flags = CLK_SET_RATE_PARENT,
1122
+
.ops = &clk_branch2_ops,
1123
+
},
1124
+
},
1125
+
};
1126
+
1127
+
static struct clk_branch ne_gcc_qupv3_wrap2_s3_clk = {
1128
+
.halt_reg = 0x38510,
1129
+
.halt_check = BRANCH_HALT_VOTED,
1130
+
.clkr = {
1131
+
.enable_reg = 0x57008,
1132
+
.enable_mask = BIT(5),
1133
+
.hw.init = &(const struct clk_init_data) {
1134
+
.name = "ne_gcc_qupv3_wrap2_s3_clk",
1135
+
.parent_hws = (const struct clk_hw*[]) {
1136
+
&ne_gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
1137
+
},
1138
+
.num_parents = 1,
1139
+
.flags = CLK_SET_RATE_PARENT,
1140
+
.ops = &clk_branch2_ops,
1141
+
},
1142
+
},
1143
+
};
1144
+
1145
+
static struct clk_branch ne_gcc_qupv3_wrap2_s4_clk = {
1146
+
.halt_reg = 0x3864c,
1147
+
.halt_check = BRANCH_HALT_VOTED,
1148
+
.clkr = {
1149
+
.enable_reg = 0x57008,
1150
+
.enable_mask = BIT(6),
1151
+
.hw.init = &(const struct clk_init_data) {
1152
+
.name = "ne_gcc_qupv3_wrap2_s4_clk",
1153
+
.parent_hws = (const struct clk_hw*[]) {
1154
+
&ne_gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
1155
+
},
1156
+
.num_parents = 1,
1157
+
.flags = CLK_SET_RATE_PARENT,
1158
+
.ops = &clk_branch2_ops,
1159
+
},
1160
+
},
1161
+
};
1162
+
1163
+
static struct clk_branch ne_gcc_qupv3_wrap2_s5_clk = {
1164
+
.halt_reg = 0x38788,
1165
+
.halt_check = BRANCH_HALT_VOTED,
1166
+
.clkr = {
1167
+
.enable_reg = 0x57008,
1168
+
.enable_mask = BIT(7),
1169
+
.hw.init = &(const struct clk_init_data) {
1170
+
.name = "ne_gcc_qupv3_wrap2_s5_clk",
1171
+
.parent_hws = (const struct clk_hw*[]) {
1172
+
&ne_gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
1173
+
},
1174
+
.num_parents = 1,
1175
+
.flags = CLK_SET_RATE_PARENT,
1176
+
.ops = &clk_branch2_ops,
1177
+
},
1178
+
},
1179
+
};
1180
+
1181
+
static struct clk_branch ne_gcc_qupv3_wrap2_s6_clk = {
1182
+
.halt_reg = 0x388c4,
1183
+
.halt_check = BRANCH_HALT_VOTED,
1184
+
.clkr = {
1185
+
.enable_reg = 0x57008,
1186
+
.enable_mask = BIT(8),
1187
+
.hw.init = &(const struct clk_init_data) {
1188
+
.name = "ne_gcc_qupv3_wrap2_s6_clk",
1189
+
.parent_hws = (const struct clk_hw*[]) {
1190
+
&ne_gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
1191
+
},
1192
+
.num_parents = 1,
1193
+
.flags = CLK_SET_RATE_PARENT,
1194
+
.ops = &clk_branch2_ops,
1195
+
},
1196
+
},
1197
+
};
1198
+
1199
+
static struct clk_branch ne_gcc_qupv3_wrap2_s_ahb_clk = {
1200
+
.halt_reg = 0x38008,
1201
+
.halt_check = BRANCH_HALT_VOTED,
1202
+
.hwcg_reg = 0x38008,
1203
+
.hwcg_bit = 1,
1204
+
.clkr = {
1205
+
.enable_reg = 0x57000,
1206
+
.enable_mask = BIT(31),
1207
+
.hw.init = &(const struct clk_init_data) {
1208
+
.name = "ne_gcc_qupv3_wrap2_s_ahb_clk",
1209
+
.ops = &clk_branch2_ops,
1210
+
},
1211
+
},
1212
+
};
1213
+
1214
+
static struct clk_branch ne_gcc_sdcc4_apps_clk = {
1215
+
.halt_reg = 0x18004,
1216
+
.halt_check = BRANCH_HALT,
1217
+
.clkr = {
1218
+
.enable_reg = 0x18004,
1219
+
.enable_mask = BIT(0),
1220
+
.hw.init = &(const struct clk_init_data) {
1221
+
.name = "ne_gcc_sdcc4_apps_clk",
1222
+
.parent_hws = (const struct clk_hw*[]) {
1223
+
&ne_gcc_sdcc4_apps_clk_src.clkr.hw,
1224
+
},
1225
+
.num_parents = 1,
1226
+
.flags = CLK_SET_RATE_PARENT,
1227
+
.ops = &clk_branch2_ops,
1228
+
},
1229
+
},
1230
+
};
1231
+
1232
+
static struct clk_branch ne_gcc_sdcc4_axi_clk = {
1233
+
.halt_reg = 0x18014,
1234
+
.halt_check = BRANCH_HALT,
1235
+
.clkr = {
1236
+
.enable_reg = 0x18014,
1237
+
.enable_mask = BIT(0),
1238
+
.hw.init = &(const struct clk_init_data) {
1239
+
.name = "ne_gcc_sdcc4_axi_clk",
1240
+
.ops = &clk_branch2_ops,
1241
+
},
1242
+
},
1243
+
};
1244
+
1245
+
static struct clk_branch ne_gcc_ufs_phy_ahb_clk = {
1246
+
.halt_reg = 0x33028,
1247
+
.halt_check = BRANCH_HALT_VOTED,
1248
+
.hwcg_reg = 0x33028,
1249
+
.hwcg_bit = 1,
1250
+
.clkr = {
1251
+
.enable_reg = 0x33028,
1252
+
.enable_mask = BIT(0),
1253
+
.hw.init = &(const struct clk_init_data) {
1254
+
.name = "ne_gcc_ufs_phy_ahb_clk",
1255
+
.ops = &clk_branch2_ops,
1256
+
},
1257
+
},
1258
+
};
1259
+
1260
+
static struct clk_branch ne_gcc_ufs_phy_axi_clk = {
1261
+
.halt_reg = 0x33018,
1262
+
.halt_check = BRANCH_HALT_VOTED,
1263
+
.hwcg_reg = 0x33018,
1264
+
.hwcg_bit = 1,
1265
+
.clkr = {
1266
+
.enable_reg = 0x33018,
1267
+
.enable_mask = BIT(0),
1268
+
.hw.init = &(const struct clk_init_data) {
1269
+
.name = "ne_gcc_ufs_phy_axi_clk",
1270
+
.parent_hws = (const struct clk_hw*[]) {
1271
+
&ne_gcc_ufs_phy_axi_clk_src.clkr.hw,
1272
+
},
1273
+
.num_parents = 1,
1274
+
.flags = CLK_SET_RATE_PARENT,
1275
+
.ops = &clk_branch2_ops,
1276
+
},
1277
+
},
1278
+
};
1279
+
1280
+
static struct clk_branch ne_gcc_ufs_phy_ice_core_clk = {
1281
+
.halt_reg = 0x3307c,
1282
+
.halt_check = BRANCH_HALT_VOTED,
1283
+
.hwcg_reg = 0x3307c,
1284
+
.hwcg_bit = 1,
1285
+
.clkr = {
1286
+
.enable_reg = 0x3307c,
1287
+
.enable_mask = BIT(0),
1288
+
.hw.init = &(const struct clk_init_data) {
1289
+
.name = "ne_gcc_ufs_phy_ice_core_clk",
1290
+
.parent_hws = (const struct clk_hw*[]) {
1291
+
&ne_gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1292
+
},
1293
+
.num_parents = 1,
1294
+
.flags = CLK_SET_RATE_PARENT,
1295
+
.ops = &clk_branch2_ops,
1296
+
},
1297
+
},
1298
+
};
1299
+
1300
+
static struct clk_branch ne_gcc_ufs_phy_phy_aux_clk = {
1301
+
.halt_reg = 0x330bc,
1302
+
.halt_check = BRANCH_HALT_VOTED,
1303
+
.hwcg_reg = 0x330bc,
1304
+
.hwcg_bit = 1,
1305
+
.clkr = {
1306
+
.enable_reg = 0x330bc,
1307
+
.enable_mask = BIT(0),
1308
+
.hw.init = &(const struct clk_init_data) {
1309
+
.name = "ne_gcc_ufs_phy_phy_aux_clk",
1310
+
.parent_hws = (const struct clk_hw*[]) {
1311
+
&ne_gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1312
+
},
1313
+
.num_parents = 1,
1314
+
.flags = CLK_SET_RATE_PARENT,
1315
+
.ops = &clk_branch2_ops,
1316
+
},
1317
+
},
1318
+
};
1319
+
1320
+
static struct clk_branch ne_gcc_ufs_phy_rx_symbol_0_clk = {
1321
+
.halt_reg = 0x33030,
1322
+
.halt_check = BRANCH_HALT_DELAY,
1323
+
.clkr = {
1324
+
.enable_reg = 0x33030,
1325
+
.enable_mask = BIT(0),
1326
+
.hw.init = &(const struct clk_init_data) {
1327
+
.name = "ne_gcc_ufs_phy_rx_symbol_0_clk",
1328
+
.parent_hws = (const struct clk_hw*[]) {
1329
+
&ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
1330
+
},
1331
+
.num_parents = 1,
1332
+
.flags = CLK_SET_RATE_PARENT,
1333
+
.ops = &clk_branch2_ops,
1334
+
},
1335
+
},
1336
+
};
1337
+
1338
+
static struct clk_branch ne_gcc_ufs_phy_rx_symbol_1_clk = {
1339
+
.halt_reg = 0x330d8,
1340
+
.halt_check = BRANCH_HALT_DELAY,
1341
+
.clkr = {
1342
+
.enable_reg = 0x330d8,
1343
+
.enable_mask = BIT(0),
1344
+
.hw.init = &(const struct clk_init_data) {
1345
+
.name = "ne_gcc_ufs_phy_rx_symbol_1_clk",
1346
+
.parent_hws = (const struct clk_hw*[]) {
1347
+
&ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
1348
+
},
1349
+
.num_parents = 1,
1350
+
.flags = CLK_SET_RATE_PARENT,
1351
+
.ops = &clk_branch2_ops,
1352
+
},
1353
+
},
1354
+
};
1355
+
1356
+
static struct clk_branch ne_gcc_ufs_phy_tx_symbol_0_clk = {
1357
+
.halt_reg = 0x3302c,
1358
+
.halt_check = BRANCH_HALT_DELAY,
1359
+
.clkr = {
1360
+
.enable_reg = 0x3302c,
1361
+
.enable_mask = BIT(0),
1362
+
.hw.init = &(const struct clk_init_data) {
1363
+
.name = "ne_gcc_ufs_phy_tx_symbol_0_clk",
1364
+
.parent_hws = (const struct clk_hw*[]) {
1365
+
&ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
1366
+
},
1367
+
.num_parents = 1,
1368
+
.flags = CLK_SET_RATE_PARENT,
1369
+
.ops = &clk_branch2_ops,
1370
+
},
1371
+
},
1372
+
};
1373
+
1374
+
static struct clk_branch ne_gcc_ufs_phy_unipro_core_clk = {
1375
+
.halt_reg = 0x3306c,
1376
+
.halt_check = BRANCH_HALT_VOTED,
1377
+
.hwcg_reg = 0x3306c,
1378
+
.hwcg_bit = 1,
1379
+
.clkr = {
1380
+
.enable_reg = 0x3306c,
1381
+
.enable_mask = BIT(0),
1382
+
.hw.init = &(const struct clk_init_data) {
1383
+
.name = "ne_gcc_ufs_phy_unipro_core_clk",
1384
+
.parent_hws = (const struct clk_hw*[]) {
1385
+
&ne_gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1386
+
},
1387
+
.num_parents = 1,
1388
+
.flags = CLK_SET_RATE_PARENT,
1389
+
.ops = &clk_branch2_ops,
1390
+
},
1391
+
},
1392
+
};
1393
+
1394
+
static struct clk_branch ne_gcc_usb20_master_clk = {
1395
+
.halt_reg = 0x31018,
1396
+
.halt_check = BRANCH_HALT,
1397
+
.clkr = {
1398
+
.enable_reg = 0x31018,
1399
+
.enable_mask = BIT(0),
1400
+
.hw.init = &(const struct clk_init_data) {
1401
+
.name = "ne_gcc_usb20_master_clk",
1402
+
.parent_hws = (const struct clk_hw*[]) {
1403
+
&ne_gcc_usb20_master_clk_src.clkr.hw,
1404
+
},
1405
+
.num_parents = 1,
1406
+
.flags = CLK_SET_RATE_PARENT,
1407
+
.ops = &clk_branch2_ops,
1408
+
},
1409
+
},
1410
+
};
1411
+
1412
+
static struct clk_branch ne_gcc_usb20_mock_utmi_clk = {
1413
+
.halt_reg = 0x3102c,
1414
+
.halt_check = BRANCH_HALT,
1415
+
.clkr = {
1416
+
.enable_reg = 0x3102c,
1417
+
.enable_mask = BIT(0),
1418
+
.hw.init = &(const struct clk_init_data) {
1419
+
.name = "ne_gcc_usb20_mock_utmi_clk",
1420
+
.parent_hws = (const struct clk_hw*[]) {
1421
+
&ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
1422
+
},
1423
+
.num_parents = 1,
1424
+
.flags = CLK_SET_RATE_PARENT,
1425
+
.ops = &clk_branch2_ops,
1426
+
},
1427
+
},
1428
+
};
1429
+
1430
+
static struct clk_branch ne_gcc_usb20_sleep_clk = {
1431
+
.halt_reg = 0x31028,
1432
+
.halt_check = BRANCH_HALT,
1433
+
.clkr = {
1434
+
.enable_reg = 0x31028,
1435
+
.enable_mask = BIT(0),
1436
+
.hw.init = &(const struct clk_init_data) {
1437
+
.name = "ne_gcc_usb20_sleep_clk",
1438
+
.ops = &clk_branch2_ops,
1439
+
},
1440
+
},
1441
+
};
1442
+
1443
+
static struct clk_branch ne_gcc_usb31_prim_atb_clk = {
1444
+
.halt_reg = 0x2a018,
1445
+
.halt_check = BRANCH_HALT_VOTED,
1446
+
.clkr = {
1447
+
.enable_reg = 0x2a018,
1448
+
.enable_mask = BIT(0),
1449
+
.hw.init = &(const struct clk_init_data) {
1450
+
.name = "ne_gcc_usb31_prim_atb_clk",
1451
+
.parent_hws = (const struct clk_hw*[]) {
1452
+
&ne_gcc_usb31_prim_master_clk_src.clkr.hw,
1453
+
},
1454
+
.num_parents = 1,
1455
+
.flags = CLK_SET_RATE_PARENT,
1456
+
.ops = &clk_branch2_ops,
1457
+
},
1458
+
},
1459
+
};
1460
+
1461
+
static struct clk_branch ne_gcc_usb31_prim_eud_ahb_clk = {
1462
+
.halt_reg = 0x2a02c,
1463
+
.halt_check = BRANCH_HALT_VOTED,
1464
+
.hwcg_reg = 0x2a02c,
1465
+
.hwcg_bit = 1,
1466
+
.clkr = {
1467
+
.enable_reg = 0x2a02c,
1468
+
.enable_mask = BIT(0),
1469
+
.hw.init = &(const struct clk_init_data) {
1470
+
.name = "ne_gcc_usb31_prim_eud_ahb_clk",
1471
+
.ops = &clk_branch2_ops,
1472
+
},
1473
+
},
1474
+
};
1475
+
1476
+
static struct clk_branch ne_gcc_usb31_prim_master_clk = {
1477
+
.halt_reg = 0x2a01c,
1478
+
.halt_check = BRANCH_HALT,
1479
+
.clkr = {
1480
+
.enable_reg = 0x2a01c,
1481
+
.enable_mask = BIT(0),
1482
+
.hw.init = &(const struct clk_init_data) {
1483
+
.name = "ne_gcc_usb31_prim_master_clk",
1484
+
.parent_hws = (const struct clk_hw*[]) {
1485
+
&ne_gcc_usb31_prim_master_clk_src.clkr.hw,
1486
+
},
1487
+
.num_parents = 1,
1488
+
.flags = CLK_SET_RATE_PARENT,
1489
+
.ops = &clk_branch2_ops,
1490
+
},
1491
+
},
1492
+
};
1493
+
1494
+
static struct clk_branch ne_gcc_usb31_prim_mock_utmi_clk = {
1495
+
.halt_reg = 0x2a034,
1496
+
.halt_check = BRANCH_HALT,
1497
+
.clkr = {
1498
+
.enable_reg = 0x2a034,
1499
+
.enable_mask = BIT(0),
1500
+
.hw.init = &(const struct clk_init_data) {
1501
+
.name = "ne_gcc_usb31_prim_mock_utmi_clk",
1502
+
.parent_hws = (const struct clk_hw*[]) {
1503
+
&ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr.hw,
1504
+
},
1505
+
.num_parents = 1,
1506
+
.flags = CLK_SET_RATE_PARENT,
1507
+
.ops = &clk_branch2_ops,
1508
+
},
1509
+
},
1510
+
};
1511
+
1512
+
static struct clk_branch ne_gcc_usb31_prim_sleep_clk = {
1513
+
.halt_reg = 0x2a030,
1514
+
.halt_check = BRANCH_HALT,
1515
+
.clkr = {
1516
+
.enable_reg = 0x2a030,
1517
+
.enable_mask = BIT(0),
1518
+
.hw.init = &(const struct clk_init_data) {
1519
+
.name = "ne_gcc_usb31_prim_sleep_clk",
1520
+
.ops = &clk_branch2_ops,
1521
+
},
1522
+
},
1523
+
};
1524
+
1525
+
static struct clk_branch ne_gcc_usb31_sec_atb_clk = {
1526
+
.halt_reg = 0x2c018,
1527
+
.halt_check = BRANCH_HALT_VOTED,
1528
+
.clkr = {
1529
+
.enable_reg = 0x2c018,
1530
+
.enable_mask = BIT(0),
1531
+
.hw.init = &(const struct clk_init_data) {
1532
+
.name = "ne_gcc_usb31_sec_atb_clk",
1533
+
.parent_hws = (const struct clk_hw*[]) {
1534
+
&ne_gcc_usb31_prim_master_clk_src.clkr.hw,
1535
+
},
1536
+
.num_parents = 1,
1537
+
.flags = CLK_SET_RATE_PARENT,
1538
+
.ops = &clk_branch2_ops,
1539
+
},
1540
+
},
1541
+
};
1542
+
1543
+
static struct clk_branch ne_gcc_usb31_sec_eud_ahb_clk = {
1544
+
.halt_reg = 0x2c02c,
1545
+
.halt_check = BRANCH_HALT_VOTED,
1546
+
.hwcg_reg = 0x2c02c,
1547
+
.hwcg_bit = 1,
1548
+
.clkr = {
1549
+
.enable_reg = 0x2c02c,
1550
+
.enable_mask = BIT(0),
1551
+
.hw.init = &(const struct clk_init_data) {
1552
+
.name = "ne_gcc_usb31_sec_eud_ahb_clk",
1553
+
.ops = &clk_branch2_ops,
1554
+
},
1555
+
},
1556
+
};
1557
+
1558
+
static struct clk_branch ne_gcc_usb31_sec_master_clk = {
1559
+
.halt_reg = 0x2c01c,
1560
+
.halt_check = BRANCH_HALT,
1561
+
.clkr = {
1562
+
.enable_reg = 0x2c01c,
1563
+
.enable_mask = BIT(0),
1564
+
.hw.init = &(const struct clk_init_data) {
1565
+
.name = "ne_gcc_usb31_sec_master_clk",
1566
+
.parent_hws = (const struct clk_hw*[]) {
1567
+
&ne_gcc_usb31_sec_master_clk_src.clkr.hw,
1568
+
},
1569
+
.num_parents = 1,
1570
+
.flags = CLK_SET_RATE_PARENT,
1571
+
.ops = &clk_branch2_ops,
1572
+
},
1573
+
},
1574
+
};
1575
+
1576
+
static struct clk_branch ne_gcc_usb31_sec_mock_utmi_clk = {
1577
+
.halt_reg = 0x2c034,
1578
+
.halt_check = BRANCH_HALT,
1579
+
.clkr = {
1580
+
.enable_reg = 0x2c034,
1581
+
.enable_mask = BIT(0),
1582
+
.hw.init = &(const struct clk_init_data) {
1583
+
.name = "ne_gcc_usb31_sec_mock_utmi_clk",
1584
+
.parent_hws = (const struct clk_hw*[]) {
1585
+
&ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr.hw,
1586
+
},
1587
+
.num_parents = 1,
1588
+
.flags = CLK_SET_RATE_PARENT,
1589
+
.ops = &clk_branch2_ops,
1590
+
},
1591
+
},
1592
+
};
1593
+
1594
+
static struct clk_branch ne_gcc_usb31_sec_sleep_clk = {
1595
+
.halt_reg = 0x2c030,
1596
+
.halt_check = BRANCH_HALT,
1597
+
.clkr = {
1598
+
.enable_reg = 0x2c030,
1599
+
.enable_mask = BIT(0),
1600
+
.hw.init = &(const struct clk_init_data) {
1601
+
.name = "ne_gcc_usb31_sec_sleep_clk",
1602
+
.ops = &clk_branch2_ops,
1603
+
},
1604
+
},
1605
+
};
1606
+
1607
+
static struct clk_branch ne_gcc_usb3_prim_phy_aux_clk = {
1608
+
.halt_reg = 0x2a06c,
1609
+
.halt_check = BRANCH_HALT,
1610
+
.clkr = {
1611
+
.enable_reg = 0x2a06c,
1612
+
.enable_mask = BIT(0),
1613
+
.hw.init = &(const struct clk_init_data) {
1614
+
.name = "ne_gcc_usb3_prim_phy_aux_clk",
1615
+
.parent_hws = (const struct clk_hw*[]) {
1616
+
&ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
1617
+
},
1618
+
.num_parents = 1,
1619
+
.flags = CLK_SET_RATE_PARENT,
1620
+
.ops = &clk_branch2_ops,
1621
+
},
1622
+
},
1623
+
};
1624
+
1625
+
static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = {
1626
+
.halt_reg = 0x2a070,
1627
+
.halt_check = BRANCH_HALT,
1628
+
.clkr = {
1629
+
.enable_reg = 0x2a070,
1630
+
.enable_mask = BIT(0),
1631
+
.hw.init = &(const struct clk_init_data) {
1632
+
.name = "ne_gcc_usb3_prim_phy_com_aux_clk",
1633
+
.parent_hws = (const struct clk_hw*[]) {
1634
+
&ne_gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
1635
+
},
1636
+
.num_parents = 1,
1637
+
.flags = CLK_SET_RATE_PARENT,
1638
+
.ops = &clk_branch2_ops,
1639
+
},
1640
+
},
1641
+
};
1642
+
1643
+
static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = {
1644
+
.halt_reg = 0x2a074,
1645
+
.halt_check = BRANCH_HALT_VOTED,
1646
+
.hwcg_reg = 0x2a074,
1647
+
.hwcg_bit = 1,
1648
+
.clkr = {
1649
+
.enable_reg = 0x2a074,
1650
+
.enable_mask = BIT(0),
1651
+
.hw.init = &(const struct clk_init_data) {
1652
+
.name = "ne_gcc_usb3_prim_phy_pipe_clk",
1653
+
.parent_hws = (const struct clk_hw*[]) {
1654
+
&ne_gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
1655
+
},
1656
+
.num_parents = 1,
1657
+
.flags = CLK_SET_RATE_PARENT,
1658
+
.ops = &clk_branch2_ops,
1659
+
},
1660
+
},
1661
+
};
1662
+
1663
+
static struct clk_branch ne_gcc_usb3_sec_phy_aux_clk = {
1664
+
.halt_reg = 0x2c06c,
1665
+
.halt_check = BRANCH_HALT,
1666
+
.clkr = {
1667
+
.enable_reg = 0x2c06c,
1668
+
.enable_mask = BIT(0),
1669
+
.hw.init = &(const struct clk_init_data) {
1670
+
.name = "ne_gcc_usb3_sec_phy_aux_clk",
1671
+
.parent_hws = (const struct clk_hw*[]) {
1672
+
&ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
1673
+
},
1674
+
.num_parents = 1,
1675
+
.flags = CLK_SET_RATE_PARENT,
1676
+
.ops = &clk_branch2_ops,
1677
+
},
1678
+
},
1679
+
};
1680
+
1681
+
static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = {
1682
+
.halt_reg = 0x2c070,
1683
+
.halt_check = BRANCH_HALT,
1684
+
.clkr = {
1685
+
.enable_reg = 0x2c070,
1686
+
.enable_mask = BIT(0),
1687
+
.hw.init = &(const struct clk_init_data) {
1688
+
.name = "ne_gcc_usb3_sec_phy_com_aux_clk",
1689
+
.parent_hws = (const struct clk_hw*[]) {
1690
+
&ne_gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
1691
+
},
1692
+
.num_parents = 1,
1693
+
.flags = CLK_SET_RATE_PARENT,
1694
+
.ops = &clk_branch2_ops,
1695
+
},
1696
+
},
1697
+
};
1698
+
1699
+
static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = {
1700
+
.halt_reg = 0x2c074,
1701
+
.halt_check = BRANCH_HALT_VOTED,
1702
+
.hwcg_reg = 0x2c074,
1703
+
.hwcg_bit = 1,
1704
+
.clkr = {
1705
+
.enable_reg = 0x2c074,
1706
+
.enable_mask = BIT(0),
1707
+
.hw.init = &(const struct clk_init_data) {
1708
+
.name = "ne_gcc_usb3_sec_phy_pipe_clk",
1709
+
.parent_hws = (const struct clk_hw*[]) {
1710
+
&ne_gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
1711
+
},
1712
+
.num_parents = 1,
1713
+
.flags = CLK_SET_RATE_PARENT,
1714
+
.ops = &clk_branch2_ops,
1715
+
},
1716
+
},
1717
+
};
1718
+
1719
+
static struct gdsc ne_gcc_ufs_mem_phy_gdsc = {
1720
+
.gdscr = 0x32000,
1721
+
.en_rest_wait_val = 0x2,
1722
+
.en_few_wait_val = 0x2,
1723
+
.clk_dis_wait_val = 0x2,
1724
+
.pd = {
1725
+
.name = "ne_gcc_ufs_mem_phy_gdsc",
1726
+
},
1727
+
.pwrsts = PWRSTS_OFF_ON,
1728
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1729
+
};
1730
+
1731
+
static struct gdsc ne_gcc_ufs_phy_gdsc = {
1732
+
.gdscr = 0x33004,
1733
+
.en_rest_wait_val = 0x2,
1734
+
.en_few_wait_val = 0x2,
1735
+
.clk_dis_wait_val = 0xf,
1736
+
.pd = {
1737
+
.name = "ne_gcc_ufs_phy_gdsc",
1738
+
},
1739
+
.pwrsts = PWRSTS_OFF_ON,
1740
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1741
+
};
1742
+
1743
+
static struct gdsc ne_gcc_usb20_prim_gdsc = {
1744
+
.gdscr = 0x31004,
1745
+
.en_rest_wait_val = 0x2,
1746
+
.en_few_wait_val = 0x2,
1747
+
.clk_dis_wait_val = 0xf,
1748
+
.pd = {
1749
+
.name = "ne_gcc_usb20_prim_gdsc",
1750
+
},
1751
+
.pwrsts = PWRSTS_OFF_ON,
1752
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1753
+
};
1754
+
1755
+
static struct gdsc ne_gcc_usb31_prim_gdsc = {
1756
+
.gdscr = 0x2a004,
1757
+
.en_rest_wait_val = 0x2,
1758
+
.en_few_wait_val = 0x2,
1759
+
.clk_dis_wait_val = 0xf,
1760
+
.pd = {
1761
+
.name = "ne_gcc_usb31_prim_gdsc",
1762
+
},
1763
+
.pwrsts = PWRSTS_OFF_ON,
1764
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1765
+
};
1766
+
1767
+
static struct gdsc ne_gcc_usb31_sec_gdsc = {
1768
+
.gdscr = 0x2c004,
1769
+
.en_rest_wait_val = 0x2,
1770
+
.en_few_wait_val = 0x2,
1771
+
.clk_dis_wait_val = 0xf,
1772
+
.pd = {
1773
+
.name = "ne_gcc_usb31_sec_gdsc",
1774
+
},
1775
+
.pwrsts = PWRSTS_OFF_ON,
1776
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1777
+
};
1778
+
1779
+
static struct gdsc ne_gcc_usb3_phy_gdsc = {
1780
+
.gdscr = 0x2b00c,
1781
+
.en_rest_wait_val = 0x2,
1782
+
.en_few_wait_val = 0x2,
1783
+
.clk_dis_wait_val = 0x2,
1784
+
.pd = {
1785
+
.name = "ne_gcc_usb3_phy_gdsc",
1786
+
},
1787
+
.pwrsts = PWRSTS_OFF_ON,
1788
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1789
+
};
1790
+
1791
+
static struct gdsc ne_gcc_usb3_sec_phy_gdsc = {
1792
+
.gdscr = 0x2d00c,
1793
+
.en_rest_wait_val = 0x2,
1794
+
.en_few_wait_val = 0x2,
1795
+
.clk_dis_wait_val = 0x2,
1796
+
.pd = {
1797
+
.name = "ne_gcc_usb3_sec_phy_gdsc",
1798
+
},
1799
+
.pwrsts = PWRSTS_OFF_ON,
1800
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1801
+
};
1802
+
1803
+
static struct clk_regmap *ne_gcc_nord_clocks[] = {
1804
+
[NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK] = &ne_gcc_aggre_noc_ufs_phy_axi_clk.clkr,
1805
+
[NE_GCC_AGGRE_NOC_USB2_AXI_CLK] = &ne_gcc_aggre_noc_usb2_axi_clk.clkr,
1806
+
[NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK] = &ne_gcc_aggre_noc_usb3_prim_axi_clk.clkr,
1807
+
[NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK] = &ne_gcc_aggre_noc_usb3_sec_axi_clk.clkr,
1808
+
[NE_GCC_AHB2PHY_CLK] = &ne_gcc_ahb2phy_clk.clkr,
1809
+
[NE_GCC_CNOC_USB2_AXI_CLK] = &ne_gcc_cnoc_usb2_axi_clk.clkr,
1810
+
[NE_GCC_CNOC_USB3_PRIM_AXI_CLK] = &ne_gcc_cnoc_usb3_prim_axi_clk.clkr,
1811
+
[NE_GCC_CNOC_USB3_SEC_AXI_CLK] = &ne_gcc_cnoc_usb3_sec_axi_clk.clkr,
1812
+
[NE_GCC_FRQ_MEASURE_REF_CLK] = &ne_gcc_frq_measure_ref_clk.clkr,
1813
+
[NE_GCC_GP1_CLK] = &ne_gcc_gp1_clk.clkr,
1814
+
[NE_GCC_GP1_CLK_SRC] = &ne_gcc_gp1_clk_src.clkr,
1815
+
[NE_GCC_GP2_CLK] = &ne_gcc_gp2_clk.clkr,
1816
+
[NE_GCC_GP2_CLK_SRC] = &ne_gcc_gp2_clk_src.clkr,
1817
+
[NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr,
1818
+
[NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr,
1819
+
[NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr,
1820
+
[NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr,
1821
+
[NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr,
1822
+
[NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr,
1823
+
[NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr,
1824
+
[NE_GCC_GPU_2_SMMU_VOTE_CLK] = &ne_gcc_gpu_2_smmu_vote_clk.clkr,
1825
+
[NE_GCC_QUPV3_WRAP2_CORE_2X_CLK] = &ne_gcc_qupv3_wrap2_core_2x_clk.clkr,
1826
+
[NE_GCC_QUPV3_WRAP2_CORE_CLK] = &ne_gcc_qupv3_wrap2_core_clk.clkr,
1827
+
[NE_GCC_QUPV3_WRAP2_M_AHB_CLK] = &ne_gcc_qupv3_wrap2_m_ahb_clk.clkr,
1828
+
[NE_GCC_QUPV3_WRAP2_S0_CLK] = &ne_gcc_qupv3_wrap2_s0_clk.clkr,
1829
+
[NE_GCC_QUPV3_WRAP2_S0_CLK_SRC] = &ne_gcc_qupv3_wrap2_s0_clk_src.clkr,
1830
+
[NE_GCC_QUPV3_WRAP2_S1_CLK] = &ne_gcc_qupv3_wrap2_s1_clk.clkr,
1831
+
[NE_GCC_QUPV3_WRAP2_S1_CLK_SRC] = &ne_gcc_qupv3_wrap2_s1_clk_src.clkr,
1832
+
[NE_GCC_QUPV3_WRAP2_S2_CLK] = &ne_gcc_qupv3_wrap2_s2_clk.clkr,
1833
+
[NE_GCC_QUPV3_WRAP2_S2_CLK_SRC] = &ne_gcc_qupv3_wrap2_s2_clk_src.clkr,
1834
+
[NE_GCC_QUPV3_WRAP2_S3_CLK] = &ne_gcc_qupv3_wrap2_s3_clk.clkr,
1835
+
[NE_GCC_QUPV3_WRAP2_S3_CLK_SRC] = &ne_gcc_qupv3_wrap2_s3_clk_src.clkr,
1836
+
[NE_GCC_QUPV3_WRAP2_S4_CLK] = &ne_gcc_qupv3_wrap2_s4_clk.clkr,
1837
+
[NE_GCC_QUPV3_WRAP2_S4_CLK_SRC] = &ne_gcc_qupv3_wrap2_s4_clk_src.clkr,
1838
+
[NE_GCC_QUPV3_WRAP2_S5_CLK] = &ne_gcc_qupv3_wrap2_s5_clk.clkr,
1839
+
[NE_GCC_QUPV3_WRAP2_S5_CLK_SRC] = &ne_gcc_qupv3_wrap2_s5_clk_src.clkr,
1840
+
[NE_GCC_QUPV3_WRAP2_S6_CLK] = &ne_gcc_qupv3_wrap2_s6_clk.clkr,
1841
+
[NE_GCC_QUPV3_WRAP2_S6_CLK_SRC] = &ne_gcc_qupv3_wrap2_s6_clk_src.clkr,
1842
+
[NE_GCC_QUPV3_WRAP2_S_AHB_CLK] = &ne_gcc_qupv3_wrap2_s_ahb_clk.clkr,
1843
+
[NE_GCC_SDCC4_APPS_CLK] = &ne_gcc_sdcc4_apps_clk.clkr,
1844
+
[NE_GCC_SDCC4_APPS_CLK_SRC] = &ne_gcc_sdcc4_apps_clk_src.clkr,
1845
+
[NE_GCC_SDCC4_AXI_CLK] = &ne_gcc_sdcc4_axi_clk.clkr,
1846
+
[NE_GCC_UFS_PHY_AHB_CLK] = &ne_gcc_ufs_phy_ahb_clk.clkr,
1847
+
[NE_GCC_UFS_PHY_AXI_CLK] = &ne_gcc_ufs_phy_axi_clk.clkr,
1848
+
[NE_GCC_UFS_PHY_AXI_CLK_SRC] = &ne_gcc_ufs_phy_axi_clk_src.clkr,
1849
+
[NE_GCC_UFS_PHY_ICE_CORE_CLK] = &ne_gcc_ufs_phy_ice_core_clk.clkr,
1850
+
[NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &ne_gcc_ufs_phy_ice_core_clk_src.clkr,
1851
+
[NE_GCC_UFS_PHY_PHY_AUX_CLK] = &ne_gcc_ufs_phy_phy_aux_clk.clkr,
1852
+
[NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &ne_gcc_ufs_phy_phy_aux_clk_src.clkr,
1853
+
[NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_rx_symbol_0_clk.clkr,
1854
+
[NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
1855
+
[NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &ne_gcc_ufs_phy_rx_symbol_1_clk.clkr,
1856
+
[NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &ne_gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
1857
+
[NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &ne_gcc_ufs_phy_tx_symbol_0_clk.clkr,
1858
+
[NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &ne_gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
1859
+
[NE_GCC_UFS_PHY_UNIPRO_CORE_CLK] = &ne_gcc_ufs_phy_unipro_core_clk.clkr,
1860
+
[NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &ne_gcc_ufs_phy_unipro_core_clk_src.clkr,
1861
+
[NE_GCC_USB20_MASTER_CLK] = &ne_gcc_usb20_master_clk.clkr,
1862
+
[NE_GCC_USB20_MASTER_CLK_SRC] = &ne_gcc_usb20_master_clk_src.clkr,
1863
+
[NE_GCC_USB20_MOCK_UTMI_CLK] = &ne_gcc_usb20_mock_utmi_clk.clkr,
1864
+
[NE_GCC_USB20_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb20_mock_utmi_clk_src.clkr,
1865
+
[NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &ne_gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
1866
+
[NE_GCC_USB20_SLEEP_CLK] = &ne_gcc_usb20_sleep_clk.clkr,
1867
+
[NE_GCC_USB31_PRIM_ATB_CLK] = &ne_gcc_usb31_prim_atb_clk.clkr,
1868
+
[NE_GCC_USB31_PRIM_EUD_AHB_CLK] = &ne_gcc_usb31_prim_eud_ahb_clk.clkr,
1869
+
[NE_GCC_USB31_PRIM_MASTER_CLK] = &ne_gcc_usb31_prim_master_clk.clkr,
1870
+
[NE_GCC_USB31_PRIM_MASTER_CLK_SRC] = &ne_gcc_usb31_prim_master_clk_src.clkr,
1871
+
[NE_GCC_USB31_PRIM_MOCK_UTMI_CLK] = &ne_gcc_usb31_prim_mock_utmi_clk.clkr,
1872
+
[NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_prim_mock_utmi_clk_src.clkr,
1873
+
[NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
1874
+
&ne_gcc_usb31_prim_mock_utmi_postdiv_clk_src.clkr,
1875
+
[NE_GCC_USB31_PRIM_SLEEP_CLK] = &ne_gcc_usb31_prim_sleep_clk.clkr,
1876
+
[NE_GCC_USB31_SEC_ATB_CLK] = &ne_gcc_usb31_sec_atb_clk.clkr,
1877
+
[NE_GCC_USB31_SEC_EUD_AHB_CLK] = &ne_gcc_usb31_sec_eud_ahb_clk.clkr,
1878
+
[NE_GCC_USB31_SEC_MASTER_CLK] = &ne_gcc_usb31_sec_master_clk.clkr,
1879
+
[NE_GCC_USB31_SEC_MASTER_CLK_SRC] = &ne_gcc_usb31_sec_master_clk_src.clkr,
1880
+
[NE_GCC_USB31_SEC_MOCK_UTMI_CLK] = &ne_gcc_usb31_sec_mock_utmi_clk.clkr,
1881
+
[NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC] = &ne_gcc_usb31_sec_mock_utmi_clk_src.clkr,
1882
+
[NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
1883
+
&ne_gcc_usb31_sec_mock_utmi_postdiv_clk_src.clkr,
1884
+
[NE_GCC_USB31_SEC_SLEEP_CLK] = &ne_gcc_usb31_sec_sleep_clk.clkr,
1885
+
[NE_GCC_USB3_PRIM_PHY_AUX_CLK] = &ne_gcc_usb3_prim_phy_aux_clk.clkr,
1886
+
[NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_prim_phy_aux_clk_src.clkr,
1887
+
[NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &ne_gcc_usb3_prim_phy_com_aux_clk.clkr,
1888
+
[NE_GCC_USB3_PRIM_PHY_PIPE_CLK] = &ne_gcc_usb3_prim_phy_pipe_clk.clkr,
1889
+
[NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_prim_phy_pipe_clk_src.clkr,
1890
+
[NE_GCC_USB3_SEC_PHY_AUX_CLK] = &ne_gcc_usb3_sec_phy_aux_clk.clkr,
1891
+
[NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &ne_gcc_usb3_sec_phy_aux_clk_src.clkr,
1892
+
[NE_GCC_USB3_SEC_PHY_COM_AUX_CLK] = &ne_gcc_usb3_sec_phy_com_aux_clk.clkr,
1893
+
[NE_GCC_USB3_SEC_PHY_PIPE_CLK] = &ne_gcc_usb3_sec_phy_pipe_clk.clkr,
1894
+
[NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &ne_gcc_usb3_sec_phy_pipe_clk_src.clkr,
1895
+
};
1896
+
1897
+
static struct gdsc *ne_gcc_nord_gdscs[] = {
1898
+
[NE_GCC_UFS_MEM_PHY_GDSC] = &ne_gcc_ufs_mem_phy_gdsc,
1899
+
[NE_GCC_UFS_PHY_GDSC] = &ne_gcc_ufs_phy_gdsc,
1900
+
[NE_GCC_USB20_PRIM_GDSC] = &ne_gcc_usb20_prim_gdsc,
1901
+
[NE_GCC_USB31_PRIM_GDSC] = &ne_gcc_usb31_prim_gdsc,
1902
+
[NE_GCC_USB31_SEC_GDSC] = &ne_gcc_usb31_sec_gdsc,
1903
+
[NE_GCC_USB3_PHY_GDSC] = &ne_gcc_usb3_phy_gdsc,
1904
+
[NE_GCC_USB3_SEC_PHY_GDSC] = &ne_gcc_usb3_sec_phy_gdsc,
1905
+
};
1906
+
1907
+
static const struct qcom_reset_map ne_gcc_nord_resets[] = {
1908
+
[NE_GCC_GPU_2_BCR] = { 0x34000 },
1909
+
[NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 },
1910
+
[NE_GCC_SDCC4_BCR] = { 0x18000 },
1911
+
[NE_GCC_UFS_PHY_BCR] = { 0x33000 },
1912
+
[NE_GCC_USB20_PRIM_BCR] = { 0x31000 },
1913
+
[NE_GCC_USB31_PRIM_BCR] = { 0x2a000 },
1914
+
[NE_GCC_USB31_SEC_BCR] = { 0x2c000 },
1915
+
[NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 },
1916
+
[NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 },
1917
+
[NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 },
1918
+
[NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 },
1919
+
[NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 },
1920
+
[NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 },
1921
+
};
1922
+
1923
+
static const struct clk_rcg_dfs_data ne_gcc_nord_dfs_clocks[] = {
1924
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s0_clk_src),
1925
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s1_clk_src),
1926
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s2_clk_src),
1927
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s3_clk_src),
1928
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s4_clk_src),
1929
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s5_clk_src),
1930
+
DEFINE_RCG_DFS(ne_gcc_qupv3_wrap2_s6_clk_src),
1931
+
};
1932
+
1933
+
static const struct regmap_config ne_gcc_nord_regmap_config = {
1934
+
.reg_bits = 32,
1935
+
.reg_stride = 4,
1936
+
.val_bits = 32,
1937
+
.max_register = 0xf41f0,
1938
+
.fast_io = true,
1939
+
};
1940
+
1941
+
static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
1942
+
{
1943
+
/* FORCE_MEM_CORE_ON for ne_gcc_ufs_phy_ice_core_clk and ne_gcc_ufs_phy_axi_clk */
1944
+
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_ice_core_clk, true);
1945
+
qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true);
1946
+
}
1947
+
1948
+
static struct qcom_cc_driver_data ne_gcc_nord_driver_data = {
1949
+
.dfs_rcgs = ne_gcc_nord_dfs_clocks,
1950
+
.num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks),
1951
+
.clk_regs_configure = clk_nord_regs_configure,
1952
+
};
1953
+
1954
+
static const struct qcom_cc_desc ne_gcc_nord_desc = {
1955
+
.config = &ne_gcc_nord_regmap_config,
1956
+
.clks = ne_gcc_nord_clocks,
1957
+
.num_clks = ARRAY_SIZE(ne_gcc_nord_clocks),
1958
+
.resets = ne_gcc_nord_resets,
1959
+
.num_resets = ARRAY_SIZE(ne_gcc_nord_resets),
1960
+
.gdscs = ne_gcc_nord_gdscs,
1961
+
.num_gdscs = ARRAY_SIZE(ne_gcc_nord_gdscs),
1962
+
.driver_data = &ne_gcc_nord_driver_data,
1963
+
};
1964
+
1965
+
static const struct of_device_id ne_gcc_nord_match_table[] = {
1966
+
{ .compatible = "qcom,nord-negcc" },
1967
+
{ }
1968
+
};
1969
+
MODULE_DEVICE_TABLE(of, ne_gcc_nord_match_table);
1970
+
1971
+
static int ne_gcc_nord_probe(struct platform_device *pdev)
1972
+
{
1973
+
return qcom_cc_probe(pdev, &ne_gcc_nord_desc);
1974
+
}
1975
+
1976
+
static struct platform_driver ne_gcc_nord_driver = {
1977
+
.probe = ne_gcc_nord_probe,
1978
+
.driver = {
1979
+
.name = "negcc-nord",
1980
+
.of_match_table = ne_gcc_nord_match_table,
1981
+
},
1982
+
};
1983
+
1984
+
module_platform_driver(ne_gcc_nord_driver);
1985
+
1986
+
MODULE_DESCRIPTION("QTI NEGCC NORD Driver");
1987
+
MODULE_LICENSE("GPL");
+688
drivers/clk/qcom/nwgcc-nord.c
+688
drivers/clk/qcom/nwgcc-nord.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,nord-nwgcc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-pll.h"
17
+
#include "clk-rcg.h"
18
+
#include "clk-regmap.h"
19
+
#include "clk-regmap-divider.h"
20
+
#include "clk-regmap-mux.h"
21
+
#include "common.h"
22
+
#include "reset.h"
23
+
24
+
enum {
25
+
DT_BI_TCXO,
26
+
DT_SLEEP_CLK,
27
+
};
28
+
29
+
enum {
30
+
P_BI_TCXO,
31
+
P_NW_GCC_GPLL0_OUT_EVEN,
32
+
P_NW_GCC_GPLL0_OUT_MAIN,
33
+
P_SLEEP_CLK,
34
+
};
35
+
36
+
static struct clk_alpha_pll nw_gcc_gpll0 = {
37
+
.offset = 0x0,
38
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
39
+
.clkr = {
40
+
.enable_reg = 0x0,
41
+
.enable_mask = BIT(0),
42
+
.hw.init = &(const struct clk_init_data) {
43
+
.name = "nw_gcc_gpll0",
44
+
.parent_data = &(const struct clk_parent_data) {
45
+
.index = DT_BI_TCXO,
46
+
},
47
+
.num_parents = 1,
48
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
49
+
},
50
+
},
51
+
};
52
+
53
+
static const struct clk_div_table post_div_table_nw_gcc_gpll0_out_even[] = {
54
+
{ 0x1, 2 },
55
+
{ }
56
+
};
57
+
58
+
static struct clk_alpha_pll_postdiv nw_gcc_gpll0_out_even = {
59
+
.offset = 0x0,
60
+
.post_div_shift = 10,
61
+
.post_div_table = post_div_table_nw_gcc_gpll0_out_even,
62
+
.num_post_div = ARRAY_SIZE(post_div_table_nw_gcc_gpll0_out_even),
63
+
.width = 4,
64
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
65
+
.clkr.hw.init = &(const struct clk_init_data) {
66
+
.name = "nw_gcc_gpll0_out_even",
67
+
.parent_hws = (const struct clk_hw*[]) {
68
+
&nw_gcc_gpll0.clkr.hw,
69
+
},
70
+
.num_parents = 1,
71
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
72
+
},
73
+
};
74
+
75
+
static const struct parent_map nw_gcc_parent_map_0[] = {
76
+
{ P_BI_TCXO, 0 },
77
+
{ P_NW_GCC_GPLL0_OUT_MAIN, 1 },
78
+
{ P_SLEEP_CLK, 5 },
79
+
{ P_NW_GCC_GPLL0_OUT_EVEN, 6 },
80
+
};
81
+
82
+
static const struct clk_parent_data nw_gcc_parent_data_0[] = {
83
+
{ .index = DT_BI_TCXO },
84
+
{ .hw = &nw_gcc_gpll0.clkr.hw },
85
+
{ .index = DT_SLEEP_CLK },
86
+
{ .hw = &nw_gcc_gpll0_out_even.clkr.hw },
87
+
};
88
+
89
+
static const struct freq_tbl ftbl_nw_gcc_gp1_clk_src[] = {
90
+
F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
91
+
F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
92
+
F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
93
+
{ }
94
+
};
95
+
96
+
static struct clk_rcg2 nw_gcc_gp1_clk_src = {
97
+
.cmd_rcgr = 0x20004,
98
+
.mnd_width = 16,
99
+
.hid_width = 5,
100
+
.parent_map = nw_gcc_parent_map_0,
101
+
.freq_tbl = ftbl_nw_gcc_gp1_clk_src,
102
+
.hw_clk_ctrl = true,
103
+
.clkr.hw.init = &(const struct clk_init_data) {
104
+
.name = "nw_gcc_gp1_clk_src",
105
+
.parent_data = nw_gcc_parent_data_0,
106
+
.num_parents = ARRAY_SIZE(nw_gcc_parent_data_0),
107
+
.flags = CLK_SET_RATE_PARENT,
108
+
.ops = &clk_rcg2_shared_ops,
109
+
},
110
+
};
111
+
112
+
static struct clk_rcg2 nw_gcc_gp2_clk_src = {
113
+
.cmd_rcgr = 0x21004,
114
+
.mnd_width = 16,
115
+
.hid_width = 5,
116
+
.parent_map = nw_gcc_parent_map_0,
117
+
.freq_tbl = ftbl_nw_gcc_gp1_clk_src,
118
+
.hw_clk_ctrl = true,
119
+
.clkr.hw.init = &(const struct clk_init_data) {
120
+
.name = "nw_gcc_gp2_clk_src",
121
+
.parent_data = nw_gcc_parent_data_0,
122
+
.num_parents = ARRAY_SIZE(nw_gcc_parent_data_0),
123
+
.flags = CLK_SET_RATE_PARENT,
124
+
.ops = &clk_rcg2_shared_ops,
125
+
},
126
+
};
127
+
128
+
static struct clk_branch nw_gcc_acmu_mux_clk = {
129
+
.halt_reg = 0x1f01c,
130
+
.halt_check = BRANCH_HALT,
131
+
.clkr = {
132
+
.enable_reg = 0x1f01c,
133
+
.enable_mask = BIT(0),
134
+
.hw.init = &(const struct clk_init_data) {
135
+
.name = "nw_gcc_acmu_mux_clk",
136
+
.ops = &clk_branch2_ops,
137
+
},
138
+
},
139
+
};
140
+
141
+
static struct clk_branch nw_gcc_camera_hf_axi_clk = {
142
+
.halt_reg = 0x16008,
143
+
.halt_check = BRANCH_HALT_SKIP,
144
+
.hwcg_reg = 0x16008,
145
+
.hwcg_bit = 1,
146
+
.clkr = {
147
+
.enable_reg = 0x16008,
148
+
.enable_mask = BIT(0),
149
+
.hw.init = &(const struct clk_init_data) {
150
+
.name = "nw_gcc_camera_hf_axi_clk",
151
+
.ops = &clk_branch2_ops,
152
+
},
153
+
},
154
+
};
155
+
156
+
static struct clk_branch nw_gcc_camera_sf_axi_clk = {
157
+
.halt_reg = 0x1601c,
158
+
.halt_check = BRANCH_HALT_SKIP,
159
+
.hwcg_reg = 0x1601c,
160
+
.hwcg_bit = 1,
161
+
.clkr = {
162
+
.enable_reg = 0x1601c,
163
+
.enable_mask = BIT(0),
164
+
.hw.init = &(const struct clk_init_data) {
165
+
.name = "nw_gcc_camera_sf_axi_clk",
166
+
.ops = &clk_branch2_ops,
167
+
},
168
+
},
169
+
};
170
+
171
+
static struct clk_branch nw_gcc_camera_trig_clk = {
172
+
.halt_reg = 0x16034,
173
+
.halt_check = BRANCH_HALT_VOTED,
174
+
.hwcg_reg = 0x16034,
175
+
.hwcg_bit = 1,
176
+
.clkr = {
177
+
.enable_reg = 0x16034,
178
+
.enable_mask = BIT(0),
179
+
.hw.init = &(const struct clk_init_data) {
180
+
.name = "nw_gcc_camera_trig_clk",
181
+
.ops = &clk_branch2_ops,
182
+
},
183
+
},
184
+
};
185
+
186
+
static struct clk_branch nw_gcc_disp_0_hf_axi_clk = {
187
+
.halt_reg = 0x18008,
188
+
.halt_check = BRANCH_HALT_SKIP,
189
+
.hwcg_reg = 0x18008,
190
+
.hwcg_bit = 1,
191
+
.clkr = {
192
+
.enable_reg = 0x18008,
193
+
.enable_mask = BIT(0),
194
+
.hw.init = &(const struct clk_init_data) {
195
+
.name = "nw_gcc_disp_0_hf_axi_clk",
196
+
.ops = &clk_branch2_ops,
197
+
},
198
+
},
199
+
};
200
+
201
+
static struct clk_branch nw_gcc_disp_0_trig_clk = {
202
+
.halt_reg = 0x1801c,
203
+
.halt_check = BRANCH_HALT_VOTED,
204
+
.hwcg_reg = 0x1801c,
205
+
.hwcg_bit = 1,
206
+
.clkr = {
207
+
.enable_reg = 0x1801c,
208
+
.enable_mask = BIT(0),
209
+
.hw.init = &(const struct clk_init_data) {
210
+
.name = "nw_gcc_disp_0_trig_clk",
211
+
.ops = &clk_branch2_ops,
212
+
},
213
+
},
214
+
};
215
+
216
+
static struct clk_branch nw_gcc_disp_1_hf_axi_clk = {
217
+
.halt_reg = 0x19008,
218
+
.halt_check = BRANCH_HALT_SKIP,
219
+
.hwcg_reg = 0x19008,
220
+
.hwcg_bit = 1,
221
+
.clkr = {
222
+
.enable_reg = 0x19008,
223
+
.enable_mask = BIT(0),
224
+
.hw.init = &(const struct clk_init_data) {
225
+
.name = "nw_gcc_disp_1_hf_axi_clk",
226
+
.ops = &clk_branch2_ops,
227
+
},
228
+
},
229
+
};
230
+
231
+
static struct clk_branch nw_gcc_disp_1_trig_clk = {
232
+
.halt_reg = 0x1901c,
233
+
.halt_check = BRANCH_HALT_VOTED,
234
+
.hwcg_reg = 0x1901c,
235
+
.hwcg_bit = 1,
236
+
.clkr = {
237
+
.enable_reg = 0x1901c,
238
+
.enable_mask = BIT(0),
239
+
.hw.init = &(const struct clk_init_data) {
240
+
.name = "nw_gcc_disp_1_trig_clk",
241
+
.ops = &clk_branch2_ops,
242
+
},
243
+
},
244
+
};
245
+
246
+
static struct clk_branch nw_gcc_dprx0_axi_hf_clk = {
247
+
.halt_reg = 0x29004,
248
+
.halt_check = BRANCH_HALT_SKIP,
249
+
.hwcg_reg = 0x29004,
250
+
.hwcg_bit = 1,
251
+
.clkr = {
252
+
.enable_reg = 0x29004,
253
+
.enable_mask = BIT(0),
254
+
.hw.init = &(const struct clk_init_data) {
255
+
.name = "nw_gcc_dprx0_axi_hf_clk",
256
+
.ops = &clk_branch2_ops,
257
+
},
258
+
},
259
+
};
260
+
261
+
static struct clk_branch nw_gcc_dprx1_axi_hf_clk = {
262
+
.halt_reg = 0x2a004,
263
+
.halt_check = BRANCH_HALT_SKIP,
264
+
.hwcg_reg = 0x2a004,
265
+
.hwcg_bit = 1,
266
+
.clkr = {
267
+
.enable_reg = 0x2a004,
268
+
.enable_mask = BIT(0),
269
+
.hw.init = &(const struct clk_init_data) {
270
+
.name = "nw_gcc_dprx1_axi_hf_clk",
271
+
.ops = &clk_branch2_ops,
272
+
},
273
+
},
274
+
};
275
+
276
+
static struct clk_branch nw_gcc_eva_axi0_clk = {
277
+
.halt_reg = 0x1b008,
278
+
.halt_check = BRANCH_HALT_SKIP,
279
+
.hwcg_reg = 0x1b008,
280
+
.hwcg_bit = 1,
281
+
.clkr = {
282
+
.enable_reg = 0x1b008,
283
+
.enable_mask = BIT(0),
284
+
.hw.init = &(const struct clk_init_data) {
285
+
.name = "nw_gcc_eva_axi0_clk",
286
+
.ops = &clk_branch2_ops,
287
+
},
288
+
},
289
+
};
290
+
291
+
static struct clk_branch nw_gcc_eva_axi0c_clk = {
292
+
.halt_reg = 0x1b01c,
293
+
.halt_check = BRANCH_HALT_SKIP,
294
+
.hwcg_reg = 0x1b01c,
295
+
.hwcg_bit = 1,
296
+
.clkr = {
297
+
.enable_reg = 0x1b01c,
298
+
.enable_mask = BIT(0),
299
+
.hw.init = &(const struct clk_init_data) {
300
+
.name = "nw_gcc_eva_axi0c_clk",
301
+
.ops = &clk_branch2_ops,
302
+
},
303
+
},
304
+
};
305
+
306
+
static struct clk_branch nw_gcc_eva_trig_clk = {
307
+
.halt_reg = 0x1b028,
308
+
.halt_check = BRANCH_HALT_VOTED,
309
+
.hwcg_reg = 0x1b028,
310
+
.hwcg_bit = 1,
311
+
.clkr = {
312
+
.enable_reg = 0x1b028,
313
+
.enable_mask = BIT(0),
314
+
.hw.init = &(const struct clk_init_data) {
315
+
.name = "nw_gcc_eva_trig_clk",
316
+
.ops = &clk_branch2_ops,
317
+
},
318
+
},
319
+
};
320
+
321
+
static struct clk_branch nw_gcc_frq_measure_ref_clk = {
322
+
.halt_reg = 0x1f008,
323
+
.halt_check = BRANCH_HALT,
324
+
.clkr = {
325
+
.enable_reg = 0x1f008,
326
+
.enable_mask = BIT(0),
327
+
.hw.init = &(const struct clk_init_data) {
328
+
.name = "nw_gcc_frq_measure_ref_clk",
329
+
.ops = &clk_branch2_ops,
330
+
},
331
+
},
332
+
};
333
+
334
+
static struct clk_branch nw_gcc_gp1_clk = {
335
+
.halt_reg = 0x20000,
336
+
.halt_check = BRANCH_HALT,
337
+
.clkr = {
338
+
.enable_reg = 0x20000,
339
+
.enable_mask = BIT(0),
340
+
.hw.init = &(const struct clk_init_data) {
341
+
.name = "nw_gcc_gp1_clk",
342
+
.parent_hws = (const struct clk_hw*[]) {
343
+
&nw_gcc_gp1_clk_src.clkr.hw,
344
+
},
345
+
.num_parents = 1,
346
+
.flags = CLK_SET_RATE_PARENT,
347
+
.ops = &clk_branch2_ops,
348
+
},
349
+
},
350
+
};
351
+
352
+
static struct clk_branch nw_gcc_gp2_clk = {
353
+
.halt_reg = 0x21000,
354
+
.halt_check = BRANCH_HALT,
355
+
.clkr = {
356
+
.enable_reg = 0x21000,
357
+
.enable_mask = BIT(0),
358
+
.hw.init = &(const struct clk_init_data) {
359
+
.name = "nw_gcc_gp2_clk",
360
+
.parent_hws = (const struct clk_hw*[]) {
361
+
&nw_gcc_gp2_clk_src.clkr.hw,
362
+
},
363
+
.num_parents = 1,
364
+
.flags = CLK_SET_RATE_PARENT,
365
+
.ops = &clk_branch2_ops,
366
+
},
367
+
},
368
+
};
369
+
370
+
static struct clk_branch nw_gcc_gpu_2_gpll0_clk_src = {
371
+
.halt_reg = 0x24150,
372
+
.halt_check = BRANCH_HALT_VOTED,
373
+
.hwcg_reg = 0x24150,
374
+
.hwcg_bit = 1,
375
+
.clkr = {
376
+
.enable_reg = 0x76000,
377
+
.enable_mask = BIT(6),
378
+
.hw.init = &(const struct clk_init_data) {
379
+
.name = "nw_gcc_gpu_2_gpll0_clk_src",
380
+
.parent_hws = (const struct clk_hw*[]) {
381
+
&nw_gcc_gpll0.clkr.hw,
382
+
},
383
+
.num_parents = 1,
384
+
.flags = CLK_SET_RATE_PARENT,
385
+
.ops = &clk_branch2_ops,
386
+
},
387
+
},
388
+
};
389
+
390
+
static struct clk_branch nw_gcc_gpu_2_gpll0_div_clk_src = {
391
+
.halt_reg = 0x24158,
392
+
.halt_check = BRANCH_HALT_VOTED,
393
+
.hwcg_reg = 0x24158,
394
+
.hwcg_bit = 1,
395
+
.clkr = {
396
+
.enable_reg = 0x76000,
397
+
.enable_mask = BIT(7),
398
+
.hw.init = &(const struct clk_init_data) {
399
+
.name = "nw_gcc_gpu_2_gpll0_div_clk_src",
400
+
.parent_hws = (const struct clk_hw*[]) {
401
+
&nw_gcc_gpll0_out_even.clkr.hw,
402
+
},
403
+
.num_parents = 1,
404
+
.flags = CLK_SET_RATE_PARENT,
405
+
.ops = &clk_branch2_ops,
406
+
},
407
+
},
408
+
};
409
+
410
+
static struct clk_branch nw_gcc_gpu_2_hscnoc_gfx_clk = {
411
+
.halt_reg = 0x2400c,
412
+
.halt_check = BRANCH_HALT_VOTED,
413
+
.hwcg_reg = 0x2400c,
414
+
.hwcg_bit = 1,
415
+
.clkr = {
416
+
.enable_reg = 0x2400c,
417
+
.enable_mask = BIT(0),
418
+
.hw.init = &(const struct clk_init_data) {
419
+
.name = "nw_gcc_gpu_2_hscnoc_gfx_clk",
420
+
.ops = &clk_branch2_ops,
421
+
},
422
+
},
423
+
};
424
+
425
+
static struct clk_branch nw_gcc_gpu_gpll0_clk_src = {
426
+
.halt_reg = 0x23150,
427
+
.halt_check = BRANCH_HALT_VOTED,
428
+
.hwcg_reg = 0x23150,
429
+
.hwcg_bit = 1,
430
+
.clkr = {
431
+
.enable_reg = 0x76000,
432
+
.enable_mask = BIT(4),
433
+
.hw.init = &(const struct clk_init_data) {
434
+
.name = "nw_gcc_gpu_gpll0_clk_src",
435
+
.parent_hws = (const struct clk_hw*[]) {
436
+
&nw_gcc_gpll0.clkr.hw,
437
+
},
438
+
.num_parents = 1,
439
+
.flags = CLK_SET_RATE_PARENT,
440
+
.ops = &clk_branch2_ops,
441
+
},
442
+
},
443
+
};
444
+
445
+
static struct clk_branch nw_gcc_gpu_gpll0_div_clk_src = {
446
+
.halt_reg = 0x23158,
447
+
.halt_check = BRANCH_HALT_VOTED,
448
+
.hwcg_reg = 0x23158,
449
+
.hwcg_bit = 1,
450
+
.clkr = {
451
+
.enable_reg = 0x76000,
452
+
.enable_mask = BIT(5),
453
+
.hw.init = &(const struct clk_init_data) {
454
+
.name = "nw_gcc_gpu_gpll0_div_clk_src",
455
+
.parent_hws = (const struct clk_hw*[]) {
456
+
&nw_gcc_gpll0_out_even.clkr.hw,
457
+
},
458
+
.num_parents = 1,
459
+
.flags = CLK_SET_RATE_PARENT,
460
+
.ops = &clk_branch2_ops,
461
+
},
462
+
},
463
+
};
464
+
465
+
static struct clk_branch nw_gcc_gpu_hscnoc_gfx_clk = {
466
+
.halt_reg = 0x2300c,
467
+
.halt_check = BRANCH_HALT_SKIP,
468
+
.hwcg_reg = 0x2300c,
469
+
.hwcg_bit = 1,
470
+
.clkr = {
471
+
.enable_reg = 0x2300c,
472
+
.enable_mask = BIT(0),
473
+
.hw.init = &(const struct clk_init_data) {
474
+
.name = "nw_gcc_gpu_hscnoc_gfx_clk",
475
+
.ops = &clk_branch2_ops,
476
+
},
477
+
},
478
+
};
479
+
480
+
static struct clk_branch nw_gcc_gpu_smmu_vote_clk = {
481
+
.halt_reg = 0x86038,
482
+
.halt_check = BRANCH_HALT_VOTED,
483
+
.clkr = {
484
+
.enable_reg = 0x86038,
485
+
.enable_mask = BIT(0),
486
+
.hw.init = &(const struct clk_init_data) {
487
+
.name = "nw_gcc_gpu_smmu_vote_clk",
488
+
.ops = &clk_branch2_ops,
489
+
},
490
+
},
491
+
};
492
+
493
+
static struct clk_branch nw_gcc_hscnoc_gpu_2_axi_clk = {
494
+
.halt_reg = 0x24160,
495
+
.halt_check = BRANCH_HALT_SKIP,
496
+
.hwcg_reg = 0x24160,
497
+
.hwcg_bit = 1,
498
+
.clkr = {
499
+
.enable_reg = 0x24160,
500
+
.enable_mask = BIT(0),
501
+
.hw.init = &(const struct clk_init_data) {
502
+
.name = "nw_gcc_hscnoc_gpu_2_axi_clk",
503
+
.ops = &clk_branch2_ops,
504
+
},
505
+
},
506
+
};
507
+
508
+
static struct clk_branch nw_gcc_hscnoc_gpu_axi_clk = {
509
+
.halt_reg = 0x23160,
510
+
.halt_check = BRANCH_HALT_SKIP,
511
+
.hwcg_reg = 0x23160,
512
+
.hwcg_bit = 1,
513
+
.clkr = {
514
+
.enable_reg = 0x23160,
515
+
.enable_mask = BIT(0),
516
+
.hw.init = &(const struct clk_init_data) {
517
+
.name = "nw_gcc_hscnoc_gpu_axi_clk",
518
+
.ops = &clk_branch2_ops,
519
+
},
520
+
},
521
+
};
522
+
523
+
static struct clk_branch nw_gcc_mmu_1_tcu_vote_clk = {
524
+
.halt_reg = 0x86040,
525
+
.halt_check = BRANCH_HALT_VOTED,
526
+
.clkr = {
527
+
.enable_reg = 0x86040,
528
+
.enable_mask = BIT(0),
529
+
.hw.init = &(const struct clk_init_data) {
530
+
.name = "nw_gcc_mmu_1_tcu_vote_clk",
531
+
.ops = &clk_branch2_ops,
532
+
},
533
+
},
534
+
};
535
+
536
+
static struct clk_branch nw_gcc_video_axi0_clk = {
537
+
.halt_reg = 0x1a008,
538
+
.halt_check = BRANCH_HALT_SKIP,
539
+
.hwcg_reg = 0x1a008,
540
+
.hwcg_bit = 1,
541
+
.clkr = {
542
+
.enable_reg = 0x1a008,
543
+
.enable_mask = BIT(0),
544
+
.hw.init = &(const struct clk_init_data) {
545
+
.name = "nw_gcc_video_axi0_clk",
546
+
.ops = &clk_branch2_ops,
547
+
},
548
+
},
549
+
};
550
+
551
+
static struct clk_branch nw_gcc_video_axi0c_clk = {
552
+
.halt_reg = 0x1a01c,
553
+
.halt_check = BRANCH_HALT_SKIP,
554
+
.hwcg_reg = 0x1a01c,
555
+
.hwcg_bit = 1,
556
+
.clkr = {
557
+
.enable_reg = 0x1a01c,
558
+
.enable_mask = BIT(0),
559
+
.hw.init = &(const struct clk_init_data) {
560
+
.name = "nw_gcc_video_axi0c_clk",
561
+
.ops = &clk_branch2_ops,
562
+
},
563
+
},
564
+
};
565
+
566
+
static struct clk_branch nw_gcc_video_axi1_clk = {
567
+
.halt_reg = 0x1a030,
568
+
.halt_check = BRANCH_HALT_SKIP,
569
+
.hwcg_reg = 0x1a030,
570
+
.hwcg_bit = 1,
571
+
.clkr = {
572
+
.enable_reg = 0x1a030,
573
+
.enable_mask = BIT(0),
574
+
.hw.init = &(const struct clk_init_data) {
575
+
.name = "nw_gcc_video_axi1_clk",
576
+
.ops = &clk_branch2_ops,
577
+
},
578
+
},
579
+
};
580
+
581
+
static struct clk_regmap *nw_gcc_nord_clocks[] = {
582
+
[NW_GCC_ACMU_MUX_CLK] = &nw_gcc_acmu_mux_clk.clkr,
583
+
[NW_GCC_CAMERA_HF_AXI_CLK] = &nw_gcc_camera_hf_axi_clk.clkr,
584
+
[NW_GCC_CAMERA_SF_AXI_CLK] = &nw_gcc_camera_sf_axi_clk.clkr,
585
+
[NW_GCC_CAMERA_TRIG_CLK] = &nw_gcc_camera_trig_clk.clkr,
586
+
[NW_GCC_DISP_0_HF_AXI_CLK] = &nw_gcc_disp_0_hf_axi_clk.clkr,
587
+
[NW_GCC_DISP_0_TRIG_CLK] = &nw_gcc_disp_0_trig_clk.clkr,
588
+
[NW_GCC_DISP_1_HF_AXI_CLK] = &nw_gcc_disp_1_hf_axi_clk.clkr,
589
+
[NW_GCC_DISP_1_TRIG_CLK] = &nw_gcc_disp_1_trig_clk.clkr,
590
+
[NW_GCC_DPRX0_AXI_HF_CLK] = &nw_gcc_dprx0_axi_hf_clk.clkr,
591
+
[NW_GCC_DPRX1_AXI_HF_CLK] = &nw_gcc_dprx1_axi_hf_clk.clkr,
592
+
[NW_GCC_EVA_AXI0_CLK] = &nw_gcc_eva_axi0_clk.clkr,
593
+
[NW_GCC_EVA_AXI0C_CLK] = &nw_gcc_eva_axi0c_clk.clkr,
594
+
[NW_GCC_EVA_TRIG_CLK] = &nw_gcc_eva_trig_clk.clkr,
595
+
[NW_GCC_FRQ_MEASURE_REF_CLK] = &nw_gcc_frq_measure_ref_clk.clkr,
596
+
[NW_GCC_GP1_CLK] = &nw_gcc_gp1_clk.clkr,
597
+
[NW_GCC_GP1_CLK_SRC] = &nw_gcc_gp1_clk_src.clkr,
598
+
[NW_GCC_GP2_CLK] = &nw_gcc_gp2_clk.clkr,
599
+
[NW_GCC_GP2_CLK_SRC] = &nw_gcc_gp2_clk_src.clkr,
600
+
[NW_GCC_GPLL0] = &nw_gcc_gpll0.clkr,
601
+
[NW_GCC_GPLL0_OUT_EVEN] = &nw_gcc_gpll0_out_even.clkr,
602
+
[NW_GCC_GPU_2_GPLL0_CLK_SRC] = &nw_gcc_gpu_2_gpll0_clk_src.clkr,
603
+
[NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_2_gpll0_div_clk_src.clkr,
604
+
[NW_GCC_GPU_2_HSCNOC_GFX_CLK] = &nw_gcc_gpu_2_hscnoc_gfx_clk.clkr,
605
+
[NW_GCC_GPU_GPLL0_CLK_SRC] = &nw_gcc_gpu_gpll0_clk_src.clkr,
606
+
[NW_GCC_GPU_GPLL0_DIV_CLK_SRC] = &nw_gcc_gpu_gpll0_div_clk_src.clkr,
607
+
[NW_GCC_GPU_HSCNOC_GFX_CLK] = &nw_gcc_gpu_hscnoc_gfx_clk.clkr,
608
+
[NW_GCC_GPU_SMMU_VOTE_CLK] = &nw_gcc_gpu_smmu_vote_clk.clkr,
609
+
[NW_GCC_HSCNOC_GPU_2_AXI_CLK] = &nw_gcc_hscnoc_gpu_2_axi_clk.clkr,
610
+
[NW_GCC_HSCNOC_GPU_AXI_CLK] = &nw_gcc_hscnoc_gpu_axi_clk.clkr,
611
+
[NW_GCC_MMU_1_TCU_VOTE_CLK] = &nw_gcc_mmu_1_tcu_vote_clk.clkr,
612
+
[NW_GCC_VIDEO_AXI0_CLK] = &nw_gcc_video_axi0_clk.clkr,
613
+
[NW_GCC_VIDEO_AXI0C_CLK] = &nw_gcc_video_axi0c_clk.clkr,
614
+
[NW_GCC_VIDEO_AXI1_CLK] = &nw_gcc_video_axi1_clk.clkr,
615
+
};
616
+
617
+
static const struct qcom_reset_map nw_gcc_nord_resets[] = {
618
+
[NW_GCC_CAMERA_BCR] = { 0x16000 },
619
+
[NW_GCC_DISPLAY_0_BCR] = { 0x18000 },
620
+
[NW_GCC_DISPLAY_1_BCR] = { 0x19000 },
621
+
[NW_GCC_DPRX0_BCR] = { 0x29000 },
622
+
[NW_GCC_DPRX1_BCR] = { 0x2a000 },
623
+
[NW_GCC_EVA_BCR] = { 0x1b000 },
624
+
[NW_GCC_GPU_2_BCR] = { 0x24000 },
625
+
[NW_GCC_GPU_BCR] = { 0x23000 },
626
+
[NW_GCC_VIDEO_BCR] = { 0x1a000 },
627
+
};
628
+
629
+
static u32 nw_gcc_nord_critical_cbcrs[] = {
630
+
0x16004, /* NW_GCC_CAMERA_AHB_CLK */
631
+
0x16030, /* NW_GCC_CAMERA_XO_CLK */
632
+
0x18004, /* NW_GCC_DISP_0_AHB_CLK */
633
+
0x19004, /* NW_GCC_DISP_1_AHB_CLK */
634
+
0x29018, /* NW_GCC_DPRX0_CFG_AHB_CLK */
635
+
0x2a018, /* NW_GCC_DPRX1_CFG_AHB_CLK */
636
+
0x1b004, /* NW_GCC_EVA_AHB_CLK */
637
+
0x1b024, /* NW_GCC_EVA_XO_CLK */
638
+
0x23004, /* NW_GCC_GPU_CFG_AHB_CLK */
639
+
0x24004, /* NW_GCC_GPU_2_CFG_AHB_CLK */
640
+
0x1a004, /* NW_GCC_VIDEO_AHB_CLK */
641
+
0x1a044, /* NW_GCC_VIDEO_XO_CLK */
642
+
};
643
+
644
+
static struct qcom_cc_driver_data nw_gcc_nord_driver_data = {
645
+
.clk_cbcrs = nw_gcc_nord_critical_cbcrs,
646
+
.num_clk_cbcrs = ARRAY_SIZE(nw_gcc_nord_critical_cbcrs),
647
+
};
648
+
649
+
static const struct regmap_config nw_gcc_nord_regmap_config = {
650
+
.reg_bits = 32,
651
+
.reg_stride = 4,
652
+
.val_bits = 32,
653
+
.max_register = 0xf41f0,
654
+
.fast_io = true,
655
+
};
656
+
657
+
static const struct qcom_cc_desc nw_gcc_nord_desc = {
658
+
.config = &nw_gcc_nord_regmap_config,
659
+
.clks = nw_gcc_nord_clocks,
660
+
.num_clks = ARRAY_SIZE(nw_gcc_nord_clocks),
661
+
.resets = nw_gcc_nord_resets,
662
+
.num_resets = ARRAY_SIZE(nw_gcc_nord_resets),
663
+
.driver_data = &nw_gcc_nord_driver_data,
664
+
};
665
+
666
+
static const struct of_device_id nw_gcc_nord_match_table[] = {
667
+
{ .compatible = "qcom,nord-nwgcc" },
668
+
{ }
669
+
};
670
+
MODULE_DEVICE_TABLE(of, nw_gcc_nord_match_table);
671
+
672
+
static int nw_gcc_nord_probe(struct platform_device *pdev)
673
+
{
674
+
return qcom_cc_probe(pdev, &nw_gcc_nord_desc);
675
+
}
676
+
677
+
static struct platform_driver nw_gcc_nord_driver = {
678
+
.probe = nw_gcc_nord_probe,
679
+
.driver = {
680
+
.name = "nwgcc-nord",
681
+
.of_match_table = nw_gcc_nord_match_table,
682
+
},
683
+
};
684
+
685
+
module_platform_driver(nw_gcc_nord_driver);
686
+
687
+
MODULE_DESCRIPTION("QTI NWGCC NORD Driver");
688
+
MODULE_LICENSE("GPL");
+1609
drivers/clk/qcom/segcc-nord.c
+1609
drivers/clk/qcom/segcc-nord.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,nord-segcc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-pll.h"
17
+
#include "clk-rcg.h"
18
+
#include "clk-regmap.h"
19
+
#include "clk-regmap-divider.h"
20
+
#include "common.h"
21
+
#include "gdsc.h"
22
+
#include "reset.h"
23
+
24
+
enum {
25
+
DT_BI_TCXO,
26
+
DT_SLEEP_CLK,
27
+
};
28
+
29
+
enum {
30
+
P_BI_TCXO,
31
+
P_SE_GCC_GPLL0_OUT_EVEN,
32
+
P_SE_GCC_GPLL0_OUT_MAIN,
33
+
P_SE_GCC_GPLL2_OUT_MAIN,
34
+
P_SE_GCC_GPLL4_OUT_MAIN,
35
+
P_SE_GCC_GPLL5_OUT_MAIN,
36
+
P_SLEEP_CLK,
37
+
};
38
+
39
+
static struct clk_alpha_pll se_gcc_gpll0 = {
40
+
.offset = 0x0,
41
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
42
+
.clkr = {
43
+
.enable_reg = 0x0,
44
+
.enable_mask = BIT(0),
45
+
.hw.init = &(const struct clk_init_data) {
46
+
.name = "se_gcc_gpll0",
47
+
.parent_data = &(const struct clk_parent_data) {
48
+
.index = DT_BI_TCXO,
49
+
},
50
+
.num_parents = 1,
51
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
52
+
},
53
+
},
54
+
};
55
+
56
+
static const struct clk_div_table post_div_table_se_gcc_gpll0_out_even[] = {
57
+
{ 0x1, 2 },
58
+
{ }
59
+
};
60
+
61
+
static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even = {
62
+
.offset = 0x0,
63
+
.post_div_shift = 10,
64
+
.post_div_table = post_div_table_se_gcc_gpll0_out_even,
65
+
.num_post_div = ARRAY_SIZE(post_div_table_se_gcc_gpll0_out_even),
66
+
.width = 4,
67
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
68
+
.clkr.hw.init = &(const struct clk_init_data) {
69
+
.name = "se_gcc_gpll0_out_even",
70
+
.parent_hws = (const struct clk_hw*[]) {
71
+
&se_gcc_gpll0.clkr.hw,
72
+
},
73
+
.num_parents = 1,
74
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
75
+
},
76
+
};
77
+
78
+
static struct clk_alpha_pll se_gcc_gpll2 = {
79
+
.offset = 0x2000,
80
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
81
+
.clkr = {
82
+
.enable_reg = 0x0,
83
+
.enable_mask = BIT(2),
84
+
.hw.init = &(const struct clk_init_data) {
85
+
.name = "se_gcc_gpll2",
86
+
.parent_data = &(const struct clk_parent_data) {
87
+
.index = DT_BI_TCXO,
88
+
},
89
+
.num_parents = 1,
90
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
91
+
},
92
+
},
93
+
};
94
+
95
+
static struct clk_alpha_pll se_gcc_gpll4 = {
96
+
.offset = 0x4000,
97
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
98
+
.clkr = {
99
+
.enable_reg = 0x0,
100
+
.enable_mask = BIT(4),
101
+
.hw.init = &(const struct clk_init_data) {
102
+
.name = "se_gcc_gpll4",
103
+
.parent_data = &(const struct clk_parent_data) {
104
+
.index = DT_BI_TCXO,
105
+
},
106
+
.num_parents = 1,
107
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
108
+
},
109
+
},
110
+
};
111
+
112
+
static struct clk_alpha_pll se_gcc_gpll5 = {
113
+
.offset = 0x5000,
114
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
115
+
.clkr = {
116
+
.enable_reg = 0x0,
117
+
.enable_mask = BIT(5),
118
+
.hw.init = &(const struct clk_init_data) {
119
+
.name = "se_gcc_gpll5",
120
+
.parent_data = &(const struct clk_parent_data) {
121
+
.index = DT_BI_TCXO,
122
+
},
123
+
.num_parents = 1,
124
+
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
125
+
},
126
+
},
127
+
};
128
+
129
+
static const struct parent_map se_gcc_parent_map_0[] = {
130
+
{ P_BI_TCXO, 0 },
131
+
{ P_SE_GCC_GPLL0_OUT_MAIN, 1 },
132
+
{ P_SE_GCC_GPLL0_OUT_EVEN, 2 },
133
+
};
134
+
135
+
static const struct clk_parent_data se_gcc_parent_data_0[] = {
136
+
{ .index = DT_BI_TCXO },
137
+
{ .hw = &se_gcc_gpll0.clkr.hw },
138
+
{ .hw = &se_gcc_gpll0_out_even.clkr.hw },
139
+
};
140
+
141
+
static const struct parent_map se_gcc_parent_map_1[] = {
142
+
{ P_BI_TCXO, 0 },
143
+
{ P_SE_GCC_GPLL0_OUT_MAIN, 1 },
144
+
};
145
+
146
+
static const struct clk_parent_data se_gcc_parent_data_1[] = {
147
+
{ .index = DT_BI_TCXO },
148
+
{ .hw = &se_gcc_gpll0.clkr.hw },
149
+
};
150
+
151
+
static const struct parent_map se_gcc_parent_map_2[] = {
152
+
{ P_BI_TCXO, 0 },
153
+
{ P_SE_GCC_GPLL0_OUT_MAIN, 1 },
154
+
{ P_SLEEP_CLK, 5 },
155
+
};
156
+
157
+
static const struct clk_parent_data se_gcc_parent_data_2[] = {
158
+
{ .index = DT_BI_TCXO },
159
+
{ .hw = &se_gcc_gpll0.clkr.hw },
160
+
{ .index = DT_SLEEP_CLK },
161
+
};
162
+
163
+
static const struct parent_map se_gcc_parent_map_3[] = {
164
+
{ P_BI_TCXO, 0 },
165
+
{ P_SE_GCC_GPLL0_OUT_MAIN, 1 },
166
+
{ P_SE_GCC_GPLL5_OUT_MAIN, 3 },
167
+
{ P_SE_GCC_GPLL4_OUT_MAIN, 5 },
168
+
{ P_SE_GCC_GPLL2_OUT_MAIN, 6 },
169
+
};
170
+
171
+
static const struct clk_parent_data se_gcc_parent_data_3[] = {
172
+
{ .index = DT_BI_TCXO },
173
+
{ .hw = &se_gcc_gpll0.clkr.hw },
174
+
{ .hw = &se_gcc_gpll5.clkr.hw },
175
+
{ .hw = &se_gcc_gpll4.clkr.hw },
176
+
{ .hw = &se_gcc_gpll2.clkr.hw },
177
+
};
178
+
179
+
static const struct parent_map se_gcc_parent_map_4[] = {
180
+
{ P_BI_TCXO, 0 },
181
+
{ P_SE_GCC_GPLL0_OUT_MAIN, 1 },
182
+
{ P_SE_GCC_GPLL0_OUT_EVEN, 2 },
183
+
{ P_SLEEP_CLK, 5 },
184
+
};
185
+
186
+
static const struct clk_parent_data se_gcc_parent_data_4[] = {
187
+
{ .index = DT_BI_TCXO },
188
+
{ .hw = &se_gcc_gpll0.clkr.hw },
189
+
{ .hw = &se_gcc_gpll0_out_even.clkr.hw },
190
+
{ .index = DT_SLEEP_CLK },
191
+
};
192
+
193
+
static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] = {
194
+
F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
195
+
F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
196
+
{ }
197
+
};
198
+
199
+
static struct clk_rcg2 se_gcc_eee_emac0_clk_src = {
200
+
.cmd_rcgr = 0x240b8,
201
+
.mnd_width = 16,
202
+
.hid_width = 5,
203
+
.parent_map = se_gcc_parent_map_2,
204
+
.freq_tbl = ftbl_se_gcc_eee_emac0_clk_src,
205
+
.hw_clk_ctrl = true,
206
+
.clkr.hw.init = &(const struct clk_init_data) {
207
+
.name = "se_gcc_eee_emac0_clk_src",
208
+
.parent_data = se_gcc_parent_data_2,
209
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
210
+
.flags = CLK_SET_RATE_PARENT,
211
+
.ops = &clk_rcg2_shared_ops,
212
+
},
213
+
};
214
+
215
+
static struct clk_rcg2 se_gcc_eee_emac1_clk_src = {
216
+
.cmd_rcgr = 0x250b8,
217
+
.mnd_width = 16,
218
+
.hid_width = 5,
219
+
.parent_map = se_gcc_parent_map_2,
220
+
.freq_tbl = ftbl_se_gcc_eee_emac0_clk_src,
221
+
.hw_clk_ctrl = true,
222
+
.clkr.hw.init = &(const struct clk_init_data) {
223
+
.name = "se_gcc_eee_emac1_clk_src",
224
+
.parent_data = se_gcc_parent_data_2,
225
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
226
+
.flags = CLK_SET_RATE_PARENT,
227
+
.ops = &clk_rcg2_shared_ops,
228
+
},
229
+
};
230
+
231
+
static const struct freq_tbl ftbl_se_gcc_emac0_phy_aux_clk_src[] = {
232
+
F(19200000, P_BI_TCXO, 1, 0, 0),
233
+
{ }
234
+
};
235
+
236
+
static struct clk_rcg2 se_gcc_emac0_phy_aux_clk_src = {
237
+
.cmd_rcgr = 0x24030,
238
+
.mnd_width = 0,
239
+
.hid_width = 5,
240
+
.parent_map = se_gcc_parent_map_2,
241
+
.freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src,
242
+
.hw_clk_ctrl = true,
243
+
.clkr.hw.init = &(const struct clk_init_data) {
244
+
.name = "se_gcc_emac0_phy_aux_clk_src",
245
+
.parent_data = se_gcc_parent_data_2,
246
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
247
+
.flags = CLK_SET_RATE_PARENT,
248
+
.ops = &clk_rcg2_shared_ops,
249
+
},
250
+
};
251
+
252
+
static const struct freq_tbl ftbl_se_gcc_emac0_ptp_clk_src[] = {
253
+
F(150000000, P_SE_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
254
+
F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0),
255
+
{ }
256
+
};
257
+
258
+
static struct clk_rcg2 se_gcc_emac0_ptp_clk_src = {
259
+
.cmd_rcgr = 0x24084,
260
+
.mnd_width = 16,
261
+
.hid_width = 5,
262
+
.parent_map = se_gcc_parent_map_3,
263
+
.freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src,
264
+
.hw_clk_ctrl = true,
265
+
.clkr.hw.init = &(const struct clk_init_data) {
266
+
.name = "se_gcc_emac0_ptp_clk_src",
267
+
.parent_data = se_gcc_parent_data_3,
268
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
269
+
.flags = CLK_SET_RATE_PARENT,
270
+
.ops = &clk_rcg2_shared_ops,
271
+
},
272
+
};
273
+
274
+
static const struct freq_tbl ftbl_se_gcc_emac0_rgmii_clk_src[] = {
275
+
F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
276
+
F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
277
+
F(250000000, P_SE_GCC_GPLL5_OUT_MAIN, 4, 0, 0),
278
+
{ }
279
+
};
280
+
281
+
static struct clk_rcg2 se_gcc_emac0_rgmii_clk_src = {
282
+
.cmd_rcgr = 0x2406c,
283
+
.mnd_width = 16,
284
+
.hid_width = 5,
285
+
.parent_map = se_gcc_parent_map_3,
286
+
.freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src,
287
+
.hw_clk_ctrl = true,
288
+
.clkr.hw.init = &(const struct clk_init_data) {
289
+
.name = "se_gcc_emac0_rgmii_clk_src",
290
+
.parent_data = se_gcc_parent_data_3,
291
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
292
+
.flags = CLK_SET_RATE_PARENT,
293
+
.ops = &clk_rcg2_shared_ops,
294
+
},
295
+
};
296
+
297
+
static struct clk_rcg2 se_gcc_emac1_phy_aux_clk_src = {
298
+
.cmd_rcgr = 0x25030,
299
+
.mnd_width = 0,
300
+
.hid_width = 5,
301
+
.parent_map = se_gcc_parent_map_2,
302
+
.freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src,
303
+
.hw_clk_ctrl = true,
304
+
.clkr.hw.init = &(const struct clk_init_data) {
305
+
.name = "se_gcc_emac1_phy_aux_clk_src",
306
+
.parent_data = se_gcc_parent_data_2,
307
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_2),
308
+
.flags = CLK_SET_RATE_PARENT,
309
+
.ops = &clk_rcg2_shared_ops,
310
+
},
311
+
};
312
+
313
+
static struct clk_rcg2 se_gcc_emac1_ptp_clk_src = {
314
+
.cmd_rcgr = 0x25084,
315
+
.mnd_width = 16,
316
+
.hid_width = 5,
317
+
.parent_map = se_gcc_parent_map_3,
318
+
.freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src,
319
+
.hw_clk_ctrl = true,
320
+
.clkr.hw.init = &(const struct clk_init_data) {
321
+
.name = "se_gcc_emac1_ptp_clk_src",
322
+
.parent_data = se_gcc_parent_data_3,
323
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
324
+
.flags = CLK_SET_RATE_PARENT,
325
+
.ops = &clk_rcg2_shared_ops,
326
+
},
327
+
};
328
+
329
+
static struct clk_rcg2 se_gcc_emac1_rgmii_clk_src = {
330
+
.cmd_rcgr = 0x2506c,
331
+
.mnd_width = 16,
332
+
.hid_width = 5,
333
+
.parent_map = se_gcc_parent_map_3,
334
+
.freq_tbl = ftbl_se_gcc_emac0_rgmii_clk_src,
335
+
.hw_clk_ctrl = true,
336
+
.clkr.hw.init = &(const struct clk_init_data) {
337
+
.name = "se_gcc_emac1_rgmii_clk_src",
338
+
.parent_data = se_gcc_parent_data_3,
339
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_3),
340
+
.flags = CLK_SET_RATE_PARENT,
341
+
.ops = &clk_rcg2_shared_ops,
342
+
},
343
+
};
344
+
345
+
static const struct freq_tbl ftbl_se_gcc_gp1_clk_src[] = {
346
+
F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
347
+
F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
348
+
F(200000000, P_SE_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
349
+
{ }
350
+
};
351
+
352
+
static struct clk_rcg2 se_gcc_gp1_clk_src = {
353
+
.cmd_rcgr = 0x19004,
354
+
.mnd_width = 16,
355
+
.hid_width = 5,
356
+
.parent_map = se_gcc_parent_map_4,
357
+
.freq_tbl = ftbl_se_gcc_gp1_clk_src,
358
+
.hw_clk_ctrl = true,
359
+
.clkr.hw.init = &(const struct clk_init_data) {
360
+
.name = "se_gcc_gp1_clk_src",
361
+
.parent_data = se_gcc_parent_data_4,
362
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_4),
363
+
.flags = CLK_SET_RATE_PARENT,
364
+
.ops = &clk_rcg2_shared_ops,
365
+
},
366
+
};
367
+
368
+
static struct clk_rcg2 se_gcc_gp2_clk_src = {
369
+
.cmd_rcgr = 0x1a004,
370
+
.mnd_width = 16,
371
+
.hid_width = 5,
372
+
.parent_map = se_gcc_parent_map_4,
373
+
.freq_tbl = ftbl_se_gcc_gp1_clk_src,
374
+
.hw_clk_ctrl = true,
375
+
.clkr.hw.init = &(const struct clk_init_data) {
376
+
.name = "se_gcc_gp2_clk_src",
377
+
.parent_data = se_gcc_parent_data_4,
378
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_4),
379
+
.flags = CLK_SET_RATE_PARENT,
380
+
.ops = &clk_rcg2_shared_ops,
381
+
},
382
+
};
383
+
384
+
static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] = {
385
+
F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
386
+
F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
387
+
F(19200000, P_BI_TCXO, 1, 0, 0),
388
+
F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
389
+
F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
390
+
F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
391
+
F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
392
+
F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
393
+
F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
394
+
F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
395
+
F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
396
+
F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
397
+
F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
398
+
F(102400000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 64, 375),
399
+
F(112000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 14, 75),
400
+
F(117964800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 3072, 15625),
401
+
F(120000000, P_SE_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
402
+
{ }
403
+
};
404
+
405
+
static struct clk_init_data se_gcc_qupv3_wrap0_s0_clk_src_init = {
406
+
.name = "se_gcc_qupv3_wrap0_s0_clk_src",
407
+
.parent_data = se_gcc_parent_data_1,
408
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
409
+
.flags = CLK_SET_RATE_PARENT,
410
+
.ops = &clk_rcg2_shared_no_init_park_ops,
411
+
};
412
+
413
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s0_clk_src = {
414
+
.cmd_rcgr = 0x2616c,
415
+
.mnd_width = 16,
416
+
.hid_width = 5,
417
+
.parent_map = se_gcc_parent_map_1,
418
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
419
+
.hw_clk_ctrl = true,
420
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s0_clk_src_init,
421
+
};
422
+
423
+
static struct clk_init_data se_gcc_qupv3_wrap0_s1_clk_src_init = {
424
+
.name = "se_gcc_qupv3_wrap0_s1_clk_src",
425
+
.parent_data = se_gcc_parent_data_1,
426
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
427
+
.flags = CLK_SET_RATE_PARENT,
428
+
.ops = &clk_rcg2_shared_no_init_park_ops,
429
+
};
430
+
431
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s1_clk_src = {
432
+
.cmd_rcgr = 0x262a8,
433
+
.mnd_width = 16,
434
+
.hid_width = 5,
435
+
.parent_map = se_gcc_parent_map_1,
436
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
437
+
.hw_clk_ctrl = true,
438
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s1_clk_src_init,
439
+
};
440
+
441
+
static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s2_clk_src[] = {
442
+
F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625),
443
+
F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625),
444
+
F(19200000, P_BI_TCXO, 1, 0, 0),
445
+
F(29491200, P_SE_GCC_GPLL0_OUT_MAIN, 1, 768, 15625),
446
+
F(32000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 75),
447
+
F(48000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 25),
448
+
F(51200000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 32, 375),
449
+
F(64000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 8, 75),
450
+
F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0),
451
+
F(75000000, P_SE_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
452
+
F(80000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 2, 15),
453
+
F(96000000, P_SE_GCC_GPLL0_OUT_MAIN, 1, 4, 25),
454
+
F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
455
+
{ }
456
+
};
457
+
458
+
static struct clk_init_data se_gcc_qupv3_wrap0_s2_clk_src_init = {
459
+
.name = "se_gcc_qupv3_wrap0_s2_clk_src",
460
+
.parent_data = se_gcc_parent_data_1,
461
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
462
+
.flags = CLK_SET_RATE_PARENT,
463
+
.ops = &clk_rcg2_shared_no_init_park_ops,
464
+
};
465
+
466
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s2_clk_src = {
467
+
.cmd_rcgr = 0x263e4,
468
+
.mnd_width = 16,
469
+
.hid_width = 5,
470
+
.parent_map = se_gcc_parent_map_1,
471
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
472
+
.hw_clk_ctrl = true,
473
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s2_clk_src_init,
474
+
};
475
+
476
+
static struct clk_init_data se_gcc_qupv3_wrap0_s3_clk_src_init = {
477
+
.name = "se_gcc_qupv3_wrap0_s3_clk_src",
478
+
.parent_data = se_gcc_parent_data_1,
479
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
480
+
.flags = CLK_SET_RATE_PARENT,
481
+
.ops = &clk_rcg2_shared_no_init_park_ops,
482
+
};
483
+
484
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s3_clk_src = {
485
+
.cmd_rcgr = 0x26520,
486
+
.mnd_width = 16,
487
+
.hid_width = 5,
488
+
.parent_map = se_gcc_parent_map_1,
489
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
490
+
.hw_clk_ctrl = true,
491
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s3_clk_src_init,
492
+
};
493
+
494
+
static struct clk_init_data se_gcc_qupv3_wrap0_s4_clk_src_init = {
495
+
.name = "se_gcc_qupv3_wrap0_s4_clk_src",
496
+
.parent_data = se_gcc_parent_data_1,
497
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
498
+
.flags = CLK_SET_RATE_PARENT,
499
+
.ops = &clk_rcg2_shared_no_init_park_ops,
500
+
};
501
+
502
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s4_clk_src = {
503
+
.cmd_rcgr = 0x2665c,
504
+
.mnd_width = 16,
505
+
.hid_width = 5,
506
+
.parent_map = se_gcc_parent_map_1,
507
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
508
+
.hw_clk_ctrl = true,
509
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s4_clk_src_init,
510
+
};
511
+
512
+
static struct clk_init_data se_gcc_qupv3_wrap0_s5_clk_src_init = {
513
+
.name = "se_gcc_qupv3_wrap0_s5_clk_src",
514
+
.parent_data = se_gcc_parent_data_1,
515
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
516
+
.flags = CLK_SET_RATE_PARENT,
517
+
.ops = &clk_rcg2_shared_no_init_park_ops,
518
+
};
519
+
520
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s5_clk_src = {
521
+
.cmd_rcgr = 0x26798,
522
+
.mnd_width = 16,
523
+
.hid_width = 5,
524
+
.parent_map = se_gcc_parent_map_1,
525
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
526
+
.hw_clk_ctrl = true,
527
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s5_clk_src_init,
528
+
};
529
+
530
+
static struct clk_init_data se_gcc_qupv3_wrap0_s6_clk_src_init = {
531
+
.name = "se_gcc_qupv3_wrap0_s6_clk_src",
532
+
.parent_data = se_gcc_parent_data_1,
533
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_1),
534
+
.flags = CLK_SET_RATE_PARENT,
535
+
.ops = &clk_rcg2_shared_no_init_park_ops,
536
+
};
537
+
538
+
static struct clk_rcg2 se_gcc_qupv3_wrap0_s6_clk_src = {
539
+
.cmd_rcgr = 0x268d4,
540
+
.mnd_width = 16,
541
+
.hid_width = 5,
542
+
.parent_map = se_gcc_parent_map_1,
543
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
544
+
.hw_clk_ctrl = true,
545
+
.clkr.hw.init = &se_gcc_qupv3_wrap0_s6_clk_src_init,
546
+
};
547
+
548
+
static struct clk_init_data se_gcc_qupv3_wrap1_s0_clk_src_init = {
549
+
.name = "se_gcc_qupv3_wrap1_s0_clk_src",
550
+
.parent_data = se_gcc_parent_data_0,
551
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
552
+
.flags = CLK_SET_RATE_PARENT,
553
+
.ops = &clk_rcg2_shared_no_init_park_ops,
554
+
};
555
+
556
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s0_clk_src = {
557
+
.cmd_rcgr = 0x2716c,
558
+
.mnd_width = 16,
559
+
.hid_width = 5,
560
+
.parent_map = se_gcc_parent_map_0,
561
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
562
+
.hw_clk_ctrl = true,
563
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s0_clk_src_init,
564
+
};
565
+
566
+
static struct clk_init_data se_gcc_qupv3_wrap1_s1_clk_src_init = {
567
+
.name = "se_gcc_qupv3_wrap1_s1_clk_src",
568
+
.parent_data = se_gcc_parent_data_0,
569
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
570
+
.flags = CLK_SET_RATE_PARENT,
571
+
.ops = &clk_rcg2_shared_no_init_park_ops,
572
+
};
573
+
574
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s1_clk_src = {
575
+
.cmd_rcgr = 0x272a8,
576
+
.mnd_width = 16,
577
+
.hid_width = 5,
578
+
.parent_map = se_gcc_parent_map_0,
579
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s0_clk_src,
580
+
.hw_clk_ctrl = true,
581
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s1_clk_src_init,
582
+
};
583
+
584
+
static struct clk_init_data se_gcc_qupv3_wrap1_s2_clk_src_init = {
585
+
.name = "se_gcc_qupv3_wrap1_s2_clk_src",
586
+
.parent_data = se_gcc_parent_data_0,
587
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
588
+
.flags = CLK_SET_RATE_PARENT,
589
+
.ops = &clk_rcg2_shared_no_init_park_ops,
590
+
};
591
+
592
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s2_clk_src = {
593
+
.cmd_rcgr = 0x273e4,
594
+
.mnd_width = 16,
595
+
.hid_width = 5,
596
+
.parent_map = se_gcc_parent_map_0,
597
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
598
+
.hw_clk_ctrl = true,
599
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s2_clk_src_init,
600
+
};
601
+
602
+
static struct clk_init_data se_gcc_qupv3_wrap1_s3_clk_src_init = {
603
+
.name = "se_gcc_qupv3_wrap1_s3_clk_src",
604
+
.parent_data = se_gcc_parent_data_0,
605
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
606
+
.flags = CLK_SET_RATE_PARENT,
607
+
.ops = &clk_rcg2_shared_no_init_park_ops,
608
+
};
609
+
610
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s3_clk_src = {
611
+
.cmd_rcgr = 0x27520,
612
+
.mnd_width = 16,
613
+
.hid_width = 5,
614
+
.parent_map = se_gcc_parent_map_0,
615
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
616
+
.hw_clk_ctrl = true,
617
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s3_clk_src_init,
618
+
};
619
+
620
+
static struct clk_init_data se_gcc_qupv3_wrap1_s4_clk_src_init = {
621
+
.name = "se_gcc_qupv3_wrap1_s4_clk_src",
622
+
.parent_data = se_gcc_parent_data_0,
623
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
624
+
.flags = CLK_SET_RATE_PARENT,
625
+
.ops = &clk_rcg2_shared_no_init_park_ops,
626
+
};
627
+
628
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s4_clk_src = {
629
+
.cmd_rcgr = 0x2765c,
630
+
.mnd_width = 16,
631
+
.hid_width = 5,
632
+
.parent_map = se_gcc_parent_map_0,
633
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
634
+
.hw_clk_ctrl = true,
635
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s4_clk_src_init,
636
+
};
637
+
638
+
static struct clk_init_data se_gcc_qupv3_wrap1_s5_clk_src_init = {
639
+
.name = "se_gcc_qupv3_wrap1_s5_clk_src",
640
+
.parent_data = se_gcc_parent_data_0,
641
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
642
+
.flags = CLK_SET_RATE_PARENT,
643
+
.ops = &clk_rcg2_shared_no_init_park_ops,
644
+
};
645
+
646
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s5_clk_src = {
647
+
.cmd_rcgr = 0x27798,
648
+
.mnd_width = 16,
649
+
.hid_width = 5,
650
+
.parent_map = se_gcc_parent_map_0,
651
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
652
+
.hw_clk_ctrl = true,
653
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s5_clk_src_init,
654
+
};
655
+
656
+
static struct clk_init_data se_gcc_qupv3_wrap1_s6_clk_src_init = {
657
+
.name = "se_gcc_qupv3_wrap1_s6_clk_src",
658
+
.parent_data = se_gcc_parent_data_0,
659
+
.num_parents = ARRAY_SIZE(se_gcc_parent_data_0),
660
+
.flags = CLK_SET_RATE_PARENT,
661
+
.ops = &clk_rcg2_shared_no_init_park_ops,
662
+
};
663
+
664
+
static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src = {
665
+
.cmd_rcgr = 0x278d4,
666
+
.mnd_width = 16,
667
+
.hid_width = 5,
668
+
.parent_map = se_gcc_parent_map_0,
669
+
.freq_tbl = ftbl_se_gcc_qupv3_wrap0_s2_clk_src,
670
+
.hw_clk_ctrl = true,
671
+
.clkr.hw.init = &se_gcc_qupv3_wrap1_s6_clk_src_init,
672
+
};
673
+
674
+
static struct clk_branch se_gcc_eee_emac0_clk = {
675
+
.halt_reg = 0x240b4,
676
+
.halt_check = BRANCH_HALT,
677
+
.clkr = {
678
+
.enable_reg = 0x240b4,
679
+
.enable_mask = BIT(0),
680
+
.hw.init = &(const struct clk_init_data) {
681
+
.name = "se_gcc_eee_emac0_clk",
682
+
.parent_hws = (const struct clk_hw*[]) {
683
+
&se_gcc_eee_emac0_clk_src.clkr.hw,
684
+
},
685
+
.num_parents = 1,
686
+
.flags = CLK_SET_RATE_PARENT,
687
+
.ops = &clk_branch2_ops,
688
+
},
689
+
},
690
+
};
691
+
692
+
static struct clk_branch se_gcc_eee_emac1_clk = {
693
+
.halt_reg = 0x250b4,
694
+
.halt_check = BRANCH_HALT,
695
+
.clkr = {
696
+
.enable_reg = 0x250b4,
697
+
.enable_mask = BIT(0),
698
+
.hw.init = &(const struct clk_init_data) {
699
+
.name = "se_gcc_eee_emac1_clk",
700
+
.parent_hws = (const struct clk_hw*[]) {
701
+
&se_gcc_eee_emac1_clk_src.clkr.hw,
702
+
},
703
+
.num_parents = 1,
704
+
.flags = CLK_SET_RATE_PARENT,
705
+
.ops = &clk_branch2_ops,
706
+
},
707
+
},
708
+
};
709
+
710
+
static struct clk_branch se_gcc_emac0_axi_clk = {
711
+
.halt_reg = 0x2401c,
712
+
.halt_check = BRANCH_HALT_VOTED,
713
+
.hwcg_reg = 0x2401c,
714
+
.hwcg_bit = 1,
715
+
.clkr = {
716
+
.enable_reg = 0x2401c,
717
+
.enable_mask = BIT(0),
718
+
.hw.init = &(const struct clk_init_data) {
719
+
.name = "se_gcc_emac0_axi_clk",
720
+
.ops = &clk_branch2_ops,
721
+
},
722
+
},
723
+
};
724
+
725
+
static struct clk_branch se_gcc_emac0_cc_sgmiiphy_rx_clk = {
726
+
.halt_reg = 0x24064,
727
+
.halt_check = BRANCH_HALT,
728
+
.clkr = {
729
+
.enable_reg = 0x24064,
730
+
.enable_mask = BIT(0),
731
+
.hw.init = &(const struct clk_init_data) {
732
+
.name = "se_gcc_emac0_cc_sgmiiphy_rx_clk",
733
+
.ops = &clk_branch2_ops,
734
+
},
735
+
},
736
+
};
737
+
738
+
static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = {
739
+
.halt_reg = 0x2405c,
740
+
.halt_check = BRANCH_HALT,
741
+
.clkr = {
742
+
.enable_reg = 0x2405c,
743
+
.enable_mask = BIT(0),
744
+
.hw.init = &(const struct clk_init_data) {
745
+
.name = "se_gcc_emac0_cc_sgmiiphy_tx_clk",
746
+
.ops = &clk_branch2_ops,
747
+
},
748
+
},
749
+
};
750
+
751
+
static struct clk_branch se_gcc_emac0_phy_aux_clk = {
752
+
.halt_reg = 0x2402c,
753
+
.halt_check = BRANCH_HALT,
754
+
.clkr = {
755
+
.enable_reg = 0x2402c,
756
+
.enable_mask = BIT(0),
757
+
.hw.init = &(const struct clk_init_data) {
758
+
.name = "se_gcc_emac0_phy_aux_clk",
759
+
.parent_hws = (const struct clk_hw*[]) {
760
+
&se_gcc_emac0_phy_aux_clk_src.clkr.hw,
761
+
},
762
+
.num_parents = 1,
763
+
.flags = CLK_SET_RATE_PARENT,
764
+
.ops = &clk_branch2_ops,
765
+
},
766
+
},
767
+
};
768
+
769
+
static struct clk_branch se_gcc_emac0_ptp_clk = {
770
+
.halt_reg = 0x24048,
771
+
.halt_check = BRANCH_HALT,
772
+
.clkr = {
773
+
.enable_reg = 0x24048,
774
+
.enable_mask = BIT(0),
775
+
.hw.init = &(const struct clk_init_data) {
776
+
.name = "se_gcc_emac0_ptp_clk",
777
+
.parent_hws = (const struct clk_hw*[]) {
778
+
&se_gcc_emac0_ptp_clk_src.clkr.hw,
779
+
},
780
+
.num_parents = 1,
781
+
.flags = CLK_SET_RATE_PARENT,
782
+
.ops = &clk_branch2_ops,
783
+
},
784
+
},
785
+
};
786
+
787
+
static struct clk_branch se_gcc_emac0_rgmii_clk = {
788
+
.halt_reg = 0x24058,
789
+
.halt_check = BRANCH_HALT,
790
+
.clkr = {
791
+
.enable_reg = 0x24058,
792
+
.enable_mask = BIT(0),
793
+
.hw.init = &(const struct clk_init_data) {
794
+
.name = "se_gcc_emac0_rgmii_clk",
795
+
.parent_hws = (const struct clk_hw*[]) {
796
+
&se_gcc_emac0_rgmii_clk_src.clkr.hw,
797
+
},
798
+
.num_parents = 1,
799
+
.flags = CLK_SET_RATE_PARENT,
800
+
.ops = &clk_branch2_ops,
801
+
},
802
+
},
803
+
};
804
+
805
+
static struct clk_branch se_gcc_emac0_rpcs_rx_clk = {
806
+
.halt_reg = 0x240a8,
807
+
.halt_check = BRANCH_HALT,
808
+
.clkr = {
809
+
.enable_reg = 0x240a8,
810
+
.enable_mask = BIT(0),
811
+
.hw.init = &(const struct clk_init_data) {
812
+
.name = "se_gcc_emac0_rpcs_rx_clk",
813
+
.ops = &clk_branch2_ops,
814
+
},
815
+
},
816
+
};
817
+
818
+
static struct clk_branch se_gcc_emac0_rpcs_tx_clk = {
819
+
.halt_reg = 0x240a4,
820
+
.halt_check = BRANCH_HALT,
821
+
.clkr = {
822
+
.enable_reg = 0x240a4,
823
+
.enable_mask = BIT(0),
824
+
.hw.init = &(const struct clk_init_data) {
825
+
.name = "se_gcc_emac0_rpcs_tx_clk",
826
+
.ops = &clk_branch2_ops,
827
+
},
828
+
},
829
+
};
830
+
831
+
static struct clk_branch se_gcc_emac0_xgxs_rx_clk = {
832
+
.halt_reg = 0x240b0,
833
+
.halt_check = BRANCH_HALT,
834
+
.clkr = {
835
+
.enable_reg = 0x240b0,
836
+
.enable_mask = BIT(0),
837
+
.hw.init = &(const struct clk_init_data) {
838
+
.name = "se_gcc_emac0_xgxs_rx_clk",
839
+
.ops = &clk_branch2_ops,
840
+
},
841
+
},
842
+
};
843
+
844
+
static struct clk_branch se_gcc_emac0_xgxs_tx_clk = {
845
+
.halt_reg = 0x240ac,
846
+
.halt_check = BRANCH_HALT,
847
+
.clkr = {
848
+
.enable_reg = 0x240ac,
849
+
.enable_mask = BIT(0),
850
+
.hw.init = &(const struct clk_init_data) {
851
+
.name = "se_gcc_emac0_xgxs_tx_clk",
852
+
.ops = &clk_branch2_ops,
853
+
},
854
+
},
855
+
};
856
+
857
+
static struct clk_branch se_gcc_emac1_axi_clk = {
858
+
.halt_reg = 0x2501c,
859
+
.halt_check = BRANCH_HALT_VOTED,
860
+
.hwcg_reg = 0x2501c,
861
+
.hwcg_bit = 1,
862
+
.clkr = {
863
+
.enable_reg = 0x2501c,
864
+
.enable_mask = BIT(0),
865
+
.hw.init = &(const struct clk_init_data) {
866
+
.name = "se_gcc_emac1_axi_clk",
867
+
.ops = &clk_branch2_ops,
868
+
},
869
+
},
870
+
};
871
+
872
+
static struct clk_branch se_gcc_emac1_cc_sgmiiphy_rx_clk = {
873
+
.halt_reg = 0x25064,
874
+
.halt_check = BRANCH_HALT,
875
+
.clkr = {
876
+
.enable_reg = 0x25064,
877
+
.enable_mask = BIT(0),
878
+
.hw.init = &(const struct clk_init_data) {
879
+
.name = "se_gcc_emac1_cc_sgmiiphy_rx_clk",
880
+
.ops = &clk_branch2_ops,
881
+
},
882
+
},
883
+
};
884
+
885
+
static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = {
886
+
.halt_reg = 0x2505c,
887
+
.halt_check = BRANCH_HALT,
888
+
.clkr = {
889
+
.enable_reg = 0x2505c,
890
+
.enable_mask = BIT(0),
891
+
.hw.init = &(const struct clk_init_data) {
892
+
.name = "se_gcc_emac1_cc_sgmiiphy_tx_clk",
893
+
.ops = &clk_branch2_ops,
894
+
},
895
+
},
896
+
};
897
+
898
+
static struct clk_branch se_gcc_emac1_phy_aux_clk = {
899
+
.halt_reg = 0x2502c,
900
+
.halt_check = BRANCH_HALT,
901
+
.clkr = {
902
+
.enable_reg = 0x2502c,
903
+
.enable_mask = BIT(0),
904
+
.hw.init = &(const struct clk_init_data) {
905
+
.name = "se_gcc_emac1_phy_aux_clk",
906
+
.parent_hws = (const struct clk_hw*[]) {
907
+
&se_gcc_emac1_phy_aux_clk_src.clkr.hw,
908
+
},
909
+
.num_parents = 1,
910
+
.flags = CLK_SET_RATE_PARENT,
911
+
.ops = &clk_branch2_ops,
912
+
},
913
+
},
914
+
};
915
+
916
+
static struct clk_branch se_gcc_emac1_ptp_clk = {
917
+
.halt_reg = 0x25048,
918
+
.halt_check = BRANCH_HALT,
919
+
.clkr = {
920
+
.enable_reg = 0x25048,
921
+
.enable_mask = BIT(0),
922
+
.hw.init = &(const struct clk_init_data) {
923
+
.name = "se_gcc_emac1_ptp_clk",
924
+
.parent_hws = (const struct clk_hw*[]) {
925
+
&se_gcc_emac1_ptp_clk_src.clkr.hw,
926
+
},
927
+
.num_parents = 1,
928
+
.flags = CLK_SET_RATE_PARENT,
929
+
.ops = &clk_branch2_ops,
930
+
},
931
+
},
932
+
};
933
+
934
+
static struct clk_branch se_gcc_emac1_rgmii_clk = {
935
+
.halt_reg = 0x25058,
936
+
.halt_check = BRANCH_HALT,
937
+
.clkr = {
938
+
.enable_reg = 0x25058,
939
+
.enable_mask = BIT(0),
940
+
.hw.init = &(const struct clk_init_data) {
941
+
.name = "se_gcc_emac1_rgmii_clk",
942
+
.parent_hws = (const struct clk_hw*[]) {
943
+
&se_gcc_emac1_rgmii_clk_src.clkr.hw,
944
+
},
945
+
.num_parents = 1,
946
+
.flags = CLK_SET_RATE_PARENT,
947
+
.ops = &clk_branch2_ops,
948
+
},
949
+
},
950
+
};
951
+
952
+
static struct clk_branch se_gcc_emac1_rpcs_rx_clk = {
953
+
.halt_reg = 0x250a8,
954
+
.halt_check = BRANCH_HALT,
955
+
.clkr = {
956
+
.enable_reg = 0x250a8,
957
+
.enable_mask = BIT(0),
958
+
.hw.init = &(const struct clk_init_data) {
959
+
.name = "se_gcc_emac1_rpcs_rx_clk",
960
+
.ops = &clk_branch2_ops,
961
+
},
962
+
},
963
+
};
964
+
965
+
static struct clk_branch se_gcc_emac1_rpcs_tx_clk = {
966
+
.halt_reg = 0x250a4,
967
+
.halt_check = BRANCH_HALT,
968
+
.clkr = {
969
+
.enable_reg = 0x250a4,
970
+
.enable_mask = BIT(0),
971
+
.hw.init = &(const struct clk_init_data) {
972
+
.name = "se_gcc_emac1_rpcs_tx_clk",
973
+
.ops = &clk_branch2_ops,
974
+
},
975
+
},
976
+
};
977
+
978
+
static struct clk_branch se_gcc_emac1_xgxs_rx_clk = {
979
+
.halt_reg = 0x250b0,
980
+
.halt_check = BRANCH_HALT,
981
+
.clkr = {
982
+
.enable_reg = 0x250b0,
983
+
.enable_mask = BIT(0),
984
+
.hw.init = &(const struct clk_init_data) {
985
+
.name = "se_gcc_emac1_xgxs_rx_clk",
986
+
.ops = &clk_branch2_ops,
987
+
},
988
+
},
989
+
};
990
+
991
+
static struct clk_branch se_gcc_emac1_xgxs_tx_clk = {
992
+
.halt_reg = 0x250ac,
993
+
.halt_check = BRANCH_HALT,
994
+
.clkr = {
995
+
.enable_reg = 0x250ac,
996
+
.enable_mask = BIT(0),
997
+
.hw.init = &(const struct clk_init_data) {
998
+
.name = "se_gcc_emac1_xgxs_tx_clk",
999
+
.ops = &clk_branch2_ops,
1000
+
},
1001
+
},
1002
+
};
1003
+
1004
+
static struct clk_branch se_gcc_frq_measure_ref_clk = {
1005
+
.halt_reg = 0x18008,
1006
+
.halt_check = BRANCH_HALT,
1007
+
.clkr = {
1008
+
.enable_reg = 0x18008,
1009
+
.enable_mask = BIT(0),
1010
+
.hw.init = &(const struct clk_init_data) {
1011
+
.name = "se_gcc_frq_measure_ref_clk",
1012
+
.ops = &clk_branch2_ops,
1013
+
},
1014
+
},
1015
+
};
1016
+
1017
+
static struct clk_branch se_gcc_gp1_clk = {
1018
+
.halt_reg = 0x19000,
1019
+
.halt_check = BRANCH_HALT,
1020
+
.clkr = {
1021
+
.enable_reg = 0x19000,
1022
+
.enable_mask = BIT(0),
1023
+
.hw.init = &(const struct clk_init_data) {
1024
+
.name = "se_gcc_gp1_clk",
1025
+
.parent_hws = (const struct clk_hw*[]) {
1026
+
&se_gcc_gp1_clk_src.clkr.hw,
1027
+
},
1028
+
.num_parents = 1,
1029
+
.flags = CLK_SET_RATE_PARENT,
1030
+
.ops = &clk_branch2_ops,
1031
+
},
1032
+
},
1033
+
};
1034
+
1035
+
static struct clk_branch se_gcc_gp2_clk = {
1036
+
.halt_reg = 0x1a000,
1037
+
.halt_check = BRANCH_HALT,
1038
+
.clkr = {
1039
+
.enable_reg = 0x1a000,
1040
+
.enable_mask = BIT(0),
1041
+
.hw.init = &(const struct clk_init_data) {
1042
+
.name = "se_gcc_gp2_clk",
1043
+
.parent_hws = (const struct clk_hw*[]) {
1044
+
&se_gcc_gp2_clk_src.clkr.hw,
1045
+
},
1046
+
.num_parents = 1,
1047
+
.flags = CLK_SET_RATE_PARENT,
1048
+
.ops = &clk_branch2_ops,
1049
+
},
1050
+
},
1051
+
};
1052
+
1053
+
static struct clk_branch se_gcc_mmu_2_tcu_vote_clk = {
1054
+
.halt_reg = 0x57040,
1055
+
.halt_check = BRANCH_HALT_VOTED,
1056
+
.clkr = {
1057
+
.enable_reg = 0x57040,
1058
+
.enable_mask = BIT(0),
1059
+
.hw.init = &(const struct clk_init_data) {
1060
+
.name = "se_gcc_mmu_2_tcu_vote_clk",
1061
+
.ops = &clk_branch2_ops,
1062
+
},
1063
+
},
1064
+
};
1065
+
1066
+
static struct clk_branch se_gcc_qupv3_wrap0_core_2x_clk = {
1067
+
.halt_reg = 0x26020,
1068
+
.halt_check = BRANCH_HALT_VOTED,
1069
+
.clkr = {
1070
+
.enable_reg = 0x57000,
1071
+
.enable_mask = BIT(15),
1072
+
.hw.init = &(const struct clk_init_data) {
1073
+
.name = "se_gcc_qupv3_wrap0_core_2x_clk",
1074
+
.ops = &clk_branch2_ops,
1075
+
},
1076
+
},
1077
+
};
1078
+
1079
+
static struct clk_branch se_gcc_qupv3_wrap0_core_clk = {
1080
+
.halt_reg = 0x2600c,
1081
+
.halt_check = BRANCH_HALT_VOTED,
1082
+
.clkr = {
1083
+
.enable_reg = 0x57000,
1084
+
.enable_mask = BIT(14),
1085
+
.hw.init = &(const struct clk_init_data) {
1086
+
.name = "se_gcc_qupv3_wrap0_core_clk",
1087
+
.ops = &clk_branch2_ops,
1088
+
},
1089
+
},
1090
+
};
1091
+
1092
+
static struct clk_branch se_gcc_qupv3_wrap0_m_ahb_clk = {
1093
+
.halt_reg = 0x26004,
1094
+
.halt_check = BRANCH_HALT_VOTED,
1095
+
.hwcg_reg = 0x26004,
1096
+
.hwcg_bit = 1,
1097
+
.clkr = {
1098
+
.enable_reg = 0x57000,
1099
+
.enable_mask = BIT(12),
1100
+
.hw.init = &(const struct clk_init_data) {
1101
+
.name = "se_gcc_qupv3_wrap0_m_ahb_clk",
1102
+
.ops = &clk_branch2_ops,
1103
+
},
1104
+
},
1105
+
};
1106
+
1107
+
static struct clk_branch se_gcc_qupv3_wrap0_s0_clk = {
1108
+
.halt_reg = 0x2615c,
1109
+
.halt_check = BRANCH_HALT_VOTED,
1110
+
.clkr = {
1111
+
.enable_reg = 0x57000,
1112
+
.enable_mask = BIT(16),
1113
+
.hw.init = &(const struct clk_init_data) {
1114
+
.name = "se_gcc_qupv3_wrap0_s0_clk",
1115
+
.parent_hws = (const struct clk_hw*[]) {
1116
+
&se_gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1117
+
},
1118
+
.num_parents = 1,
1119
+
.flags = CLK_SET_RATE_PARENT,
1120
+
.ops = &clk_branch2_ops,
1121
+
},
1122
+
},
1123
+
};
1124
+
1125
+
static struct clk_branch se_gcc_qupv3_wrap0_s1_clk = {
1126
+
.halt_reg = 0x26298,
1127
+
.halt_check = BRANCH_HALT_VOTED,
1128
+
.clkr = {
1129
+
.enable_reg = 0x57000,
1130
+
.enable_mask = BIT(17),
1131
+
.hw.init = &(const struct clk_init_data) {
1132
+
.name = "se_gcc_qupv3_wrap0_s1_clk",
1133
+
.parent_hws = (const struct clk_hw*[]) {
1134
+
&se_gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1135
+
},
1136
+
.num_parents = 1,
1137
+
.flags = CLK_SET_RATE_PARENT,
1138
+
.ops = &clk_branch2_ops,
1139
+
},
1140
+
},
1141
+
};
1142
+
1143
+
static struct clk_branch se_gcc_qupv3_wrap0_s2_clk = {
1144
+
.halt_reg = 0x263d4,
1145
+
.halt_check = BRANCH_HALT_VOTED,
1146
+
.clkr = {
1147
+
.enable_reg = 0x57000,
1148
+
.enable_mask = BIT(18),
1149
+
.hw.init = &(const struct clk_init_data) {
1150
+
.name = "se_gcc_qupv3_wrap0_s2_clk",
1151
+
.parent_hws = (const struct clk_hw*[]) {
1152
+
&se_gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1153
+
},
1154
+
.num_parents = 1,
1155
+
.flags = CLK_SET_RATE_PARENT,
1156
+
.ops = &clk_branch2_ops,
1157
+
},
1158
+
},
1159
+
};
1160
+
1161
+
static struct clk_branch se_gcc_qupv3_wrap0_s3_clk = {
1162
+
.halt_reg = 0x26510,
1163
+
.halt_check = BRANCH_HALT_VOTED,
1164
+
.clkr = {
1165
+
.enable_reg = 0x57000,
1166
+
.enable_mask = BIT(19),
1167
+
.hw.init = &(const struct clk_init_data) {
1168
+
.name = "se_gcc_qupv3_wrap0_s3_clk",
1169
+
.parent_hws = (const struct clk_hw*[]) {
1170
+
&se_gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1171
+
},
1172
+
.num_parents = 1,
1173
+
.flags = CLK_SET_RATE_PARENT,
1174
+
.ops = &clk_branch2_ops,
1175
+
},
1176
+
},
1177
+
};
1178
+
1179
+
static struct clk_branch se_gcc_qupv3_wrap0_s4_clk = {
1180
+
.halt_reg = 0x2664c,
1181
+
.halt_check = BRANCH_HALT_VOTED,
1182
+
.clkr = {
1183
+
.enable_reg = 0x57000,
1184
+
.enable_mask = BIT(20),
1185
+
.hw.init = &(const struct clk_init_data) {
1186
+
.name = "se_gcc_qupv3_wrap0_s4_clk",
1187
+
.parent_hws = (const struct clk_hw*[]) {
1188
+
&se_gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1189
+
},
1190
+
.num_parents = 1,
1191
+
.flags = CLK_SET_RATE_PARENT,
1192
+
.ops = &clk_branch2_ops,
1193
+
},
1194
+
},
1195
+
};
1196
+
1197
+
static struct clk_branch se_gcc_qupv3_wrap0_s5_clk = {
1198
+
.halt_reg = 0x26788,
1199
+
.halt_check = BRANCH_HALT_VOTED,
1200
+
.clkr = {
1201
+
.enable_reg = 0x57000,
1202
+
.enable_mask = BIT(21),
1203
+
.hw.init = &(const struct clk_init_data) {
1204
+
.name = "se_gcc_qupv3_wrap0_s5_clk",
1205
+
.parent_hws = (const struct clk_hw*[]) {
1206
+
&se_gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1207
+
},
1208
+
.num_parents = 1,
1209
+
.flags = CLK_SET_RATE_PARENT,
1210
+
.ops = &clk_branch2_ops,
1211
+
},
1212
+
},
1213
+
};
1214
+
1215
+
static struct clk_branch se_gcc_qupv3_wrap0_s6_clk = {
1216
+
.halt_reg = 0x268c4,
1217
+
.halt_check = BRANCH_HALT_VOTED,
1218
+
.clkr = {
1219
+
.enable_reg = 0x57000,
1220
+
.enable_mask = BIT(22),
1221
+
.hw.init = &(const struct clk_init_data) {
1222
+
.name = "se_gcc_qupv3_wrap0_s6_clk",
1223
+
.parent_hws = (const struct clk_hw*[]) {
1224
+
&se_gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
1225
+
},
1226
+
.num_parents = 1,
1227
+
.flags = CLK_SET_RATE_PARENT,
1228
+
.ops = &clk_branch2_ops,
1229
+
},
1230
+
},
1231
+
};
1232
+
1233
+
static struct clk_branch se_gcc_qupv3_wrap0_s_ahb_clk = {
1234
+
.halt_reg = 0x26008,
1235
+
.halt_check = BRANCH_HALT_VOTED,
1236
+
.hwcg_reg = 0x26008,
1237
+
.hwcg_bit = 1,
1238
+
.clkr = {
1239
+
.enable_reg = 0x57000,
1240
+
.enable_mask = BIT(13),
1241
+
.hw.init = &(const struct clk_init_data) {
1242
+
.name = "se_gcc_qupv3_wrap0_s_ahb_clk",
1243
+
.ops = &clk_branch2_ops,
1244
+
},
1245
+
},
1246
+
};
1247
+
1248
+
static struct clk_branch se_gcc_qupv3_wrap1_core_2x_clk = {
1249
+
.halt_reg = 0x27020,
1250
+
.halt_check = BRANCH_HALT_VOTED,
1251
+
.clkr = {
1252
+
.enable_reg = 0x57000,
1253
+
.enable_mask = BIT(26),
1254
+
.hw.init = &(const struct clk_init_data) {
1255
+
.name = "se_gcc_qupv3_wrap1_core_2x_clk",
1256
+
.ops = &clk_branch2_ops,
1257
+
},
1258
+
},
1259
+
};
1260
+
1261
+
static struct clk_branch se_gcc_qupv3_wrap1_core_clk = {
1262
+
.halt_reg = 0x2700c,
1263
+
.halt_check = BRANCH_HALT_VOTED,
1264
+
.clkr = {
1265
+
.enable_reg = 0x57000,
1266
+
.enable_mask = BIT(25),
1267
+
.hw.init = &(const struct clk_init_data) {
1268
+
.name = "se_gcc_qupv3_wrap1_core_clk",
1269
+
.ops = &clk_branch2_ops,
1270
+
},
1271
+
},
1272
+
};
1273
+
1274
+
static struct clk_branch se_gcc_qupv3_wrap1_m_ahb_clk = {
1275
+
.halt_reg = 0x27004,
1276
+
.halt_check = BRANCH_HALT_VOTED,
1277
+
.hwcg_reg = 0x27004,
1278
+
.hwcg_bit = 1,
1279
+
.clkr = {
1280
+
.enable_reg = 0x57000,
1281
+
.enable_mask = BIT(23),
1282
+
.hw.init = &(const struct clk_init_data) {
1283
+
.name = "se_gcc_qupv3_wrap1_m_ahb_clk",
1284
+
.ops = &clk_branch2_ops,
1285
+
},
1286
+
},
1287
+
};
1288
+
1289
+
static struct clk_branch se_gcc_qupv3_wrap1_s0_clk = {
1290
+
.halt_reg = 0x2715c,
1291
+
.halt_check = BRANCH_HALT_VOTED,
1292
+
.clkr = {
1293
+
.enable_reg = 0x57000,
1294
+
.enable_mask = BIT(27),
1295
+
.hw.init = &(const struct clk_init_data) {
1296
+
.name = "se_gcc_qupv3_wrap1_s0_clk",
1297
+
.parent_hws = (const struct clk_hw*[]) {
1298
+
&se_gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1299
+
},
1300
+
.num_parents = 1,
1301
+
.flags = CLK_SET_RATE_PARENT,
1302
+
.ops = &clk_branch2_ops,
1303
+
},
1304
+
},
1305
+
};
1306
+
1307
+
static struct clk_branch se_gcc_qupv3_wrap1_s1_clk = {
1308
+
.halt_reg = 0x27298,
1309
+
.halt_check = BRANCH_HALT_VOTED,
1310
+
.clkr = {
1311
+
.enable_reg = 0x57000,
1312
+
.enable_mask = BIT(28),
1313
+
.hw.init = &(const struct clk_init_data) {
1314
+
.name = "se_gcc_qupv3_wrap1_s1_clk",
1315
+
.parent_hws = (const struct clk_hw*[]) {
1316
+
&se_gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1317
+
},
1318
+
.num_parents = 1,
1319
+
.flags = CLK_SET_RATE_PARENT,
1320
+
.ops = &clk_branch2_ops,
1321
+
},
1322
+
},
1323
+
};
1324
+
1325
+
static struct clk_branch se_gcc_qupv3_wrap1_s2_clk = {
1326
+
.halt_reg = 0x273d4,
1327
+
.halt_check = BRANCH_HALT_VOTED,
1328
+
.clkr = {
1329
+
.enable_reg = 0x57000,
1330
+
.enable_mask = BIT(29),
1331
+
.hw.init = &(const struct clk_init_data) {
1332
+
.name = "se_gcc_qupv3_wrap1_s2_clk",
1333
+
.parent_hws = (const struct clk_hw*[]) {
1334
+
&se_gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1335
+
},
1336
+
.num_parents = 1,
1337
+
.flags = CLK_SET_RATE_PARENT,
1338
+
.ops = &clk_branch2_ops,
1339
+
},
1340
+
},
1341
+
};
1342
+
1343
+
static struct clk_branch se_gcc_qupv3_wrap1_s3_clk = {
1344
+
.halt_reg = 0x27510,
1345
+
.halt_check = BRANCH_HALT_VOTED,
1346
+
.clkr = {
1347
+
.enable_reg = 0x57000,
1348
+
.enable_mask = BIT(30),
1349
+
.hw.init = &(const struct clk_init_data) {
1350
+
.name = "se_gcc_qupv3_wrap1_s3_clk",
1351
+
.parent_hws = (const struct clk_hw*[]) {
1352
+
&se_gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1353
+
},
1354
+
.num_parents = 1,
1355
+
.flags = CLK_SET_RATE_PARENT,
1356
+
.ops = &clk_branch2_ops,
1357
+
},
1358
+
},
1359
+
};
1360
+
1361
+
static struct clk_branch se_gcc_qupv3_wrap1_s4_clk = {
1362
+
.halt_reg = 0x2764c,
1363
+
.halt_check = BRANCH_HALT_VOTED,
1364
+
.clkr = {
1365
+
.enable_reg = 0x57000,
1366
+
.enable_mask = BIT(31),
1367
+
.hw.init = &(const struct clk_init_data) {
1368
+
.name = "se_gcc_qupv3_wrap1_s4_clk",
1369
+
.parent_hws = (const struct clk_hw*[]) {
1370
+
&se_gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1371
+
},
1372
+
.num_parents = 1,
1373
+
.flags = CLK_SET_RATE_PARENT,
1374
+
.ops = &clk_branch2_ops,
1375
+
},
1376
+
},
1377
+
};
1378
+
1379
+
static struct clk_branch se_gcc_qupv3_wrap1_s5_clk = {
1380
+
.halt_reg = 0x27788,
1381
+
.halt_check = BRANCH_HALT_VOTED,
1382
+
.clkr = {
1383
+
.enable_reg = 0x57008,
1384
+
.enable_mask = BIT(0),
1385
+
.hw.init = &(const struct clk_init_data) {
1386
+
.name = "se_gcc_qupv3_wrap1_s5_clk",
1387
+
.parent_hws = (const struct clk_hw*[]) {
1388
+
&se_gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1389
+
},
1390
+
.num_parents = 1,
1391
+
.flags = CLK_SET_RATE_PARENT,
1392
+
.ops = &clk_branch2_ops,
1393
+
},
1394
+
},
1395
+
};
1396
+
1397
+
static struct clk_branch se_gcc_qupv3_wrap1_s6_clk = {
1398
+
.halt_reg = 0x278c4,
1399
+
.halt_check = BRANCH_HALT_VOTED,
1400
+
.clkr = {
1401
+
.enable_reg = 0x57008,
1402
+
.enable_mask = BIT(1),
1403
+
.hw.init = &(const struct clk_init_data) {
1404
+
.name = "se_gcc_qupv3_wrap1_s6_clk",
1405
+
.parent_hws = (const struct clk_hw*[]) {
1406
+
&se_gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
1407
+
},
1408
+
.num_parents = 1,
1409
+
.flags = CLK_SET_RATE_PARENT,
1410
+
.ops = &clk_branch2_ops,
1411
+
},
1412
+
},
1413
+
};
1414
+
1415
+
static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk = {
1416
+
.halt_reg = 0x27008,
1417
+
.halt_check = BRANCH_HALT_VOTED,
1418
+
.hwcg_reg = 0x27008,
1419
+
.hwcg_bit = 1,
1420
+
.clkr = {
1421
+
.enable_reg = 0x57000,
1422
+
.enable_mask = BIT(24),
1423
+
.hw.init = &(const struct clk_init_data) {
1424
+
.name = "se_gcc_qupv3_wrap1_s_ahb_clk",
1425
+
.ops = &clk_branch2_ops,
1426
+
},
1427
+
},
1428
+
};
1429
+
1430
+
static struct gdsc se_gcc_emac0_gdsc = {
1431
+
.gdscr = 0x24004,
1432
+
.en_rest_wait_val = 0x2,
1433
+
.en_few_wait_val = 0x2,
1434
+
.clk_dis_wait_val = 0xf,
1435
+
.pd = {
1436
+
.name = "se_gcc_emac0_gdsc",
1437
+
},
1438
+
.pwrsts = PWRSTS_OFF_ON,
1439
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1440
+
};
1441
+
1442
+
static struct gdsc se_gcc_emac1_gdsc = {
1443
+
.gdscr = 0x25004,
1444
+
.en_rest_wait_val = 0x2,
1445
+
.en_few_wait_val = 0x2,
1446
+
.clk_dis_wait_val = 0xf,
1447
+
.pd = {
1448
+
.name = "se_gcc_emac1_gdsc",
1449
+
},
1450
+
.pwrsts = PWRSTS_OFF_ON,
1451
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
1452
+
};
1453
+
1454
+
static struct clk_regmap *se_gcc_nord_clocks[] = {
1455
+
[SE_GCC_EEE_EMAC0_CLK] = &se_gcc_eee_emac0_clk.clkr,
1456
+
[SE_GCC_EEE_EMAC0_CLK_SRC] = &se_gcc_eee_emac0_clk_src.clkr,
1457
+
[SE_GCC_EEE_EMAC1_CLK] = &se_gcc_eee_emac1_clk.clkr,
1458
+
[SE_GCC_EEE_EMAC1_CLK_SRC] = &se_gcc_eee_emac1_clk_src.clkr,
1459
+
[SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr,
1460
+
[SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr,
1461
+
[SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr,
1462
+
[SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr,
1463
+
[SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr,
1464
+
[SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr,
1465
+
[SE_GCC_EMAC0_PTP_CLK_SRC] = &se_gcc_emac0_ptp_clk_src.clkr,
1466
+
[SE_GCC_EMAC0_RGMII_CLK] = &se_gcc_emac0_rgmii_clk.clkr,
1467
+
[SE_GCC_EMAC0_RGMII_CLK_SRC] = &se_gcc_emac0_rgmii_clk_src.clkr,
1468
+
[SE_GCC_EMAC0_RPCS_RX_CLK] = &se_gcc_emac0_rpcs_rx_clk.clkr,
1469
+
[SE_GCC_EMAC0_RPCS_TX_CLK] = &se_gcc_emac0_rpcs_tx_clk.clkr,
1470
+
[SE_GCC_EMAC0_XGXS_RX_CLK] = &se_gcc_emac0_xgxs_rx_clk.clkr,
1471
+
[SE_GCC_EMAC0_XGXS_TX_CLK] = &se_gcc_emac0_xgxs_tx_clk.clkr,
1472
+
[SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr,
1473
+
[SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr,
1474
+
[SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr,
1475
+
[SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr,
1476
+
[SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr,
1477
+
[SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr,
1478
+
[SE_GCC_EMAC1_PTP_CLK_SRC] = &se_gcc_emac1_ptp_clk_src.clkr,
1479
+
[SE_GCC_EMAC1_RGMII_CLK] = &se_gcc_emac1_rgmii_clk.clkr,
1480
+
[SE_GCC_EMAC1_RGMII_CLK_SRC] = &se_gcc_emac1_rgmii_clk_src.clkr,
1481
+
[SE_GCC_EMAC1_RPCS_RX_CLK] = &se_gcc_emac1_rpcs_rx_clk.clkr,
1482
+
[SE_GCC_EMAC1_RPCS_TX_CLK] = &se_gcc_emac1_rpcs_tx_clk.clkr,
1483
+
[SE_GCC_EMAC1_XGXS_RX_CLK] = &se_gcc_emac1_xgxs_rx_clk.clkr,
1484
+
[SE_GCC_EMAC1_XGXS_TX_CLK] = &se_gcc_emac1_xgxs_tx_clk.clkr,
1485
+
[SE_GCC_FRQ_MEASURE_REF_CLK] = &se_gcc_frq_measure_ref_clk.clkr,
1486
+
[SE_GCC_GP1_CLK] = &se_gcc_gp1_clk.clkr,
1487
+
[SE_GCC_GP1_CLK_SRC] = &se_gcc_gp1_clk_src.clkr,
1488
+
[SE_GCC_GP2_CLK] = &se_gcc_gp2_clk.clkr,
1489
+
[SE_GCC_GP2_CLK_SRC] = &se_gcc_gp2_clk_src.clkr,
1490
+
[SE_GCC_GPLL0] = &se_gcc_gpll0.clkr,
1491
+
[SE_GCC_GPLL0_OUT_EVEN] = &se_gcc_gpll0_out_even.clkr,
1492
+
[SE_GCC_GPLL2] = &se_gcc_gpll2.clkr,
1493
+
[SE_GCC_GPLL4] = &se_gcc_gpll4.clkr,
1494
+
[SE_GCC_GPLL5] = &se_gcc_gpll5.clkr,
1495
+
[SE_GCC_MMU_2_TCU_VOTE_CLK] = &se_gcc_mmu_2_tcu_vote_clk.clkr,
1496
+
[SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] = &se_gcc_qupv3_wrap0_core_2x_clk.clkr,
1497
+
[SE_GCC_QUPV3_WRAP0_CORE_CLK] = &se_gcc_qupv3_wrap0_core_clk.clkr,
1498
+
[SE_GCC_QUPV3_WRAP0_M_AHB_CLK] = &se_gcc_qupv3_wrap0_m_ahb_clk.clkr,
1499
+
[SE_GCC_QUPV3_WRAP0_S0_CLK] = &se_gcc_qupv3_wrap0_s0_clk.clkr,
1500
+
[SE_GCC_QUPV3_WRAP0_S0_CLK_SRC] = &se_gcc_qupv3_wrap0_s0_clk_src.clkr,
1501
+
[SE_GCC_QUPV3_WRAP0_S1_CLK] = &se_gcc_qupv3_wrap0_s1_clk.clkr,
1502
+
[SE_GCC_QUPV3_WRAP0_S1_CLK_SRC] = &se_gcc_qupv3_wrap0_s1_clk_src.clkr,
1503
+
[SE_GCC_QUPV3_WRAP0_S2_CLK] = &se_gcc_qupv3_wrap0_s2_clk.clkr,
1504
+
[SE_GCC_QUPV3_WRAP0_S2_CLK_SRC] = &se_gcc_qupv3_wrap0_s2_clk_src.clkr,
1505
+
[SE_GCC_QUPV3_WRAP0_S3_CLK] = &se_gcc_qupv3_wrap0_s3_clk.clkr,
1506
+
[SE_GCC_QUPV3_WRAP0_S3_CLK_SRC] = &se_gcc_qupv3_wrap0_s3_clk_src.clkr,
1507
+
[SE_GCC_QUPV3_WRAP0_S4_CLK] = &se_gcc_qupv3_wrap0_s4_clk.clkr,
1508
+
[SE_GCC_QUPV3_WRAP0_S4_CLK_SRC] = &se_gcc_qupv3_wrap0_s4_clk_src.clkr,
1509
+
[SE_GCC_QUPV3_WRAP0_S5_CLK] = &se_gcc_qupv3_wrap0_s5_clk.clkr,
1510
+
[SE_GCC_QUPV3_WRAP0_S5_CLK_SRC] = &se_gcc_qupv3_wrap0_s5_clk_src.clkr,
1511
+
[SE_GCC_QUPV3_WRAP0_S6_CLK] = &se_gcc_qupv3_wrap0_s6_clk.clkr,
1512
+
[SE_GCC_QUPV3_WRAP0_S6_CLK_SRC] = &se_gcc_qupv3_wrap0_s6_clk_src.clkr,
1513
+
[SE_GCC_QUPV3_WRAP0_S_AHB_CLK] = &se_gcc_qupv3_wrap0_s_ahb_clk.clkr,
1514
+
[SE_GCC_QUPV3_WRAP1_CORE_2X_CLK] = &se_gcc_qupv3_wrap1_core_2x_clk.clkr,
1515
+
[SE_GCC_QUPV3_WRAP1_CORE_CLK] = &se_gcc_qupv3_wrap1_core_clk.clkr,
1516
+
[SE_GCC_QUPV3_WRAP1_M_AHB_CLK] = &se_gcc_qupv3_wrap1_m_ahb_clk.clkr,
1517
+
[SE_GCC_QUPV3_WRAP1_S0_CLK] = &se_gcc_qupv3_wrap1_s0_clk.clkr,
1518
+
[SE_GCC_QUPV3_WRAP1_S0_CLK_SRC] = &se_gcc_qupv3_wrap1_s0_clk_src.clkr,
1519
+
[SE_GCC_QUPV3_WRAP1_S1_CLK] = &se_gcc_qupv3_wrap1_s1_clk.clkr,
1520
+
[SE_GCC_QUPV3_WRAP1_S1_CLK_SRC] = &se_gcc_qupv3_wrap1_s1_clk_src.clkr,
1521
+
[SE_GCC_QUPV3_WRAP1_S2_CLK] = &se_gcc_qupv3_wrap1_s2_clk.clkr,
1522
+
[SE_GCC_QUPV3_WRAP1_S2_CLK_SRC] = &se_gcc_qupv3_wrap1_s2_clk_src.clkr,
1523
+
[SE_GCC_QUPV3_WRAP1_S3_CLK] = &se_gcc_qupv3_wrap1_s3_clk.clkr,
1524
+
[SE_GCC_QUPV3_WRAP1_S3_CLK_SRC] = &se_gcc_qupv3_wrap1_s3_clk_src.clkr,
1525
+
[SE_GCC_QUPV3_WRAP1_S4_CLK] = &se_gcc_qupv3_wrap1_s4_clk.clkr,
1526
+
[SE_GCC_QUPV3_WRAP1_S4_CLK_SRC] = &se_gcc_qupv3_wrap1_s4_clk_src.clkr,
1527
+
[SE_GCC_QUPV3_WRAP1_S5_CLK] = &se_gcc_qupv3_wrap1_s5_clk.clkr,
1528
+
[SE_GCC_QUPV3_WRAP1_S5_CLK_SRC] = &se_gcc_qupv3_wrap1_s5_clk_src.clkr,
1529
+
[SE_GCC_QUPV3_WRAP1_S6_CLK] = &se_gcc_qupv3_wrap1_s6_clk.clkr,
1530
+
[SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] = &se_gcc_qupv3_wrap1_s6_clk_src.clkr,
1531
+
[SE_GCC_QUPV3_WRAP1_S_AHB_CLK] = &se_gcc_qupv3_wrap1_s_ahb_clk.clkr,
1532
+
};
1533
+
1534
+
static struct gdsc *se_gcc_nord_gdscs[] = {
1535
+
[SE_GCC_EMAC0_GDSC] = &se_gcc_emac0_gdsc,
1536
+
[SE_GCC_EMAC1_GDSC] = &se_gcc_emac1_gdsc,
1537
+
};
1538
+
1539
+
static const struct qcom_reset_map se_gcc_nord_resets[] = {
1540
+
[SE_GCC_EMAC0_BCR] = { 0x24000 },
1541
+
[SE_GCC_EMAC1_BCR] = { 0x25000 },
1542
+
[SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 },
1543
+
[SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 },
1544
+
};
1545
+
1546
+
static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] = {
1547
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src),
1548
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src),
1549
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src),
1550
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s3_clk_src),
1551
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s4_clk_src),
1552
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s5_clk_src),
1553
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s6_clk_src),
1554
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s0_clk_src),
1555
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s1_clk_src),
1556
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s2_clk_src),
1557
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s3_clk_src),
1558
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s4_clk_src),
1559
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s5_clk_src),
1560
+
DEFINE_RCG_DFS(se_gcc_qupv3_wrap1_s6_clk_src),
1561
+
};
1562
+
1563
+
static const struct regmap_config se_gcc_nord_regmap_config = {
1564
+
.reg_bits = 32,
1565
+
.reg_stride = 4,
1566
+
.val_bits = 32,
1567
+
.max_register = 0xf41f0,
1568
+
.fast_io = true,
1569
+
};
1570
+
1571
+
static struct qcom_cc_driver_data se_gcc_nord_driver_data = {
1572
+
.dfs_rcgs = se_gcc_nord_dfs_clocks,
1573
+
.num_dfs_rcgs = ARRAY_SIZE(se_gcc_nord_dfs_clocks),
1574
+
};
1575
+
1576
+
static const struct qcom_cc_desc se_gcc_nord_desc = {
1577
+
.config = &se_gcc_nord_regmap_config,
1578
+
.clks = se_gcc_nord_clocks,
1579
+
.num_clks = ARRAY_SIZE(se_gcc_nord_clocks),
1580
+
.resets = se_gcc_nord_resets,
1581
+
.num_resets = ARRAY_SIZE(se_gcc_nord_resets),
1582
+
.gdscs = se_gcc_nord_gdscs,
1583
+
.num_gdscs = ARRAY_SIZE(se_gcc_nord_gdscs),
1584
+
.driver_data = &se_gcc_nord_driver_data,
1585
+
};
1586
+
1587
+
static const struct of_device_id se_gcc_nord_match_table[] = {
1588
+
{ .compatible = "qcom,nord-segcc" },
1589
+
{ }
1590
+
};
1591
+
MODULE_DEVICE_TABLE(of, se_gcc_nord_match_table);
1592
+
1593
+
static int se_gcc_nord_probe(struct platform_device *pdev)
1594
+
{
1595
+
return qcom_cc_probe(pdev, &se_gcc_nord_desc);
1596
+
}
1597
+
1598
+
static struct platform_driver se_gcc_nord_driver = {
1599
+
.probe = se_gcc_nord_probe,
1600
+
.driver = {
1601
+
.name = "segcc-nord",
1602
+
.of_match_table = se_gcc_nord_match_table,
1603
+
},
1604
+
};
1605
+
1606
+
module_platform_driver(se_gcc_nord_driver);
1607
+
1608
+
MODULE_DESCRIPTION("QTI SEGCC NORD Driver");
1609
+
MODULE_LICENSE("GPL");