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drm/amd/ras: adapt sync info func for pmfw eeprom

adapt sync info func for pmfw eeprom

Signed-off-by: Gangliang Xie <ganglxie@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Gangliang Xie and committed by
Alex Deucher a4f87a1c e82f9aac

+19 -1
+4 -1
drivers/gpu/drm/amd/ras/rascore/ras_core.c
··· 258 258 return ret; 259 259 } 260 260 261 - ras_eeprom_sync_info(ras_core); 261 + if (ras_fw_eeprom_supported(ras_core)) 262 + ras_fw_eeprom_sync_info(ras_core); 263 + else 264 + ras_eeprom_sync_info(ras_core); 262 265 263 266 return ret; 264 267 }
+14
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c
··· 504 504 505 505 return RAS_GPU_HEALTH_USABLE; 506 506 } 507 + 508 + void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core) 509 + { 510 + struct ras_fw_eeprom_control *control; 511 + 512 + if (!ras_core) 513 + return; 514 + 515 + control = &ras_core->ras_fw_eeprom; 516 + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, 517 + &control->ras_num_recs); 518 + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, 519 + &control->bad_channel_bitmap); 520 + }
+1
drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h
··· 82 82 int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core); 83 83 enum ras_gpu_health_status 84 84 ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core); 85 + void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core); 85 86 86 87 #endif