iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage

STE in a nested case requires both S1 and S2 fields. And this makes the use
case different from the existing one.

Add coverage for previously failed cases shifting between S2-only and S1+S2
STEs.

Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Pranjal Shrivastava <praan@google.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>

authored by

Nicolin Chen and committed by

Will Deacon 3 months ago a4f976ed 7cad8004

+47

1 changed file

expand all

drivers

iommu

arm

arm-smmu-v3

arm-smmu-v3-test.c

+47

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c

··· 33 33 enum arm_smmu_test_master_feat { 34 34 ARM_SMMU_MASTER_TEST_ATS = BIT(0), 35 35 ARM_SMMU_MASTER_TEST_STALL = BIT(1), 36 + ARM_SMMU_MASTER_TEST_NESTED = BIT(2), 36 37 }; 38 + 39 + static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, 40 + enum arm_smmu_test_master_feat feat); 37 41 38 42 static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, 39 43 const __le64 *used_bits, ··· 214 210 }; 215 211 216 212 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); 213 + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { 214 + struct arm_smmu_ste s2ste; 215 + int i; 216 + 217 + arm_smmu_test_make_s2_ste(&s2ste, 218 + feat & ~ARM_SMMU_MASTER_TEST_NESTED); 219 + ste->data[0] |= cpu_to_le64( 220 + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); 221 + ste->data[1] |= cpu_to_le64(STRTAB_STE_1_MEV); 222 + for (i = 2; i < NUM_ENTRY_QWORDS; i++) 223 + ste->data[i] = s2ste.data[i]; 224 + } 217 225 } 218 226 219 227 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) ··· 583 567 NUM_EXPECTED_SYNCS(3)); 584 568 } 585 569 570 + static void 571 + arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *test) 572 + { 573 + struct arm_smmu_ste s1_ste; 574 + struct arm_smmu_ste s2_ste; 575 + 576 + arm_smmu_test_make_cdtable_ste( 577 + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, 578 + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); 579 + arm_smmu_test_make_s2_ste(&s2_ste, 0); 580 + /* Expect an additional sync to unset ignored bits: EATS and MEV */ 581 + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, 582 + NUM_EXPECTED_SYNCS(3)); 583 + } 584 + 585 + static void 586 + arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *test) 587 + { 588 + struct arm_smmu_ste s1_ste; 589 + struct arm_smmu_ste s2_ste; 590 + 591 + arm_smmu_test_make_cdtable_ste( 592 + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, 593 + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); 594 + arm_smmu_test_make_s2_ste(&s2_ste, 0); 595 + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, 596 + NUM_EXPECTED_SYNCS(2)); 597 + } 598 + 586 599 static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) 587 600 { 588 601 struct arm_smmu_cd cd = {}; ··· 658 613 KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), 659 614 KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), 660 615 KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), 616 + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), 617 + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), 661 618 KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), 662 619 KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), 663 620 {},

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