Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Update the compat layer to allow single-byte watchpoints on all
addresses (similar to the native support)
- arm_pmu: fix the restoration of the counters on the
CPU_PM_ENTER_FAILED path
- Fix build regression with vDSO and Makefile not stripping
CROSS_COMPILE_COMPAT
- Fix the CTR_EL0 (cache type register) sanitisation on heterogeneous
machines (e.g. big.LITTLE)
- Fix the interrupt controller priority mask value when pseudo-NMIs are
enabled
- arm64 kprobes fixes: recovering of the PSTATE.D flag in the
single-step exception handler, NOKPROBE annotations for
unwind_frame() and walk_stackframe(), remove unneeded
rcu_read_lock/unlock from debug handlers
- Several gcc fall-through warnings
- Unused variable warnings
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Make debug exception handlers visible from RCU
arm64: kprobes: Recover pstate.D in single-step exception handler
arm64/mm: fix variable 'tag' set but not used
arm64/mm: fix variable 'pud' set but not used
arm64: Remove unneeded rcu_read_lock from debug handlers
arm64: unwind: Prohibit probing on return_address()
arm64: Lower priority mask for GIC_PRIO_IRQON
arm64/efi: fix variable 'si' set but not used
arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
arm64: vdso: Fix Makefile regression
arm64: module: Mark expected switch fall-through
arm64: smp: Mark expected switch fall-through
arm64: hw_breakpoint: Fix warnings about implicit fallthrough
drivers/perf: arm_pmu: Fix failure path in PM notifier
arm64: compat: Allow single-byte watchpoints on all addresses
+117
-66
+1
-1
arch/arm64/Makefile
+1
-1
arch/arm64/Makefile
···
52
52
53
53
ifeq ($(CONFIG_CC_IS_CLANG), y)
54
54
$(warning CROSS_COMPILE_COMPAT is clang, the compat vDSO will not be built)
55
-
else ifeq ($(CROSS_COMPILE_COMPAT),)
55
+
else ifeq ($(strip $(CROSS_COMPILE_COMPAT)),)
56
56
$(warning CROSS_COMPILE_COMPAT not defined or empty, the compat vDSO will not be built)
57
57
else ifeq ($(shell which $(CROSS_COMPILE_COMPAT)gcc 2> /dev/null),)
58
58
$(error $(CROSS_COMPILE_COMPAT)gcc not found, check CROSS_COMPILE_COMPAT)
+6
arch/arm64/include/asm/arch_gicv3.h
+6
arch/arm64/include/asm/arch_gicv3.h
···
155
155
BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
156
156
GIC_PRIO_PSR_I_SET));
157
157
BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
158
+
/*
159
+
* Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
160
+
* and non-secure PMR accesses are not subject to the shifts that
161
+
* are applied to IRQ priorities
162
+
*/
163
+
BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
158
164
gic_write_pmr(GIC_PRIO_IRQOFF);
159
165
}
160
166
+4
-3
arch/arm64/include/asm/cpufeature.h
+4
-3
arch/arm64/include/asm/cpufeature.h
···
35
35
*/
36
36
37
37
enum ftr_type {
38
-
FTR_EXACT, /* Use a predefined safe value */
39
-
FTR_LOWER_SAFE, /* Smaller value is safe */
40
-
FTR_HIGHER_SAFE,/* Bigger value is safe */
38
+
FTR_EXACT, /* Use a predefined safe value */
39
+
FTR_LOWER_SAFE, /* Smaller value is safe */
40
+
FTR_HIGHER_SAFE, /* Bigger value is safe */
41
+
FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
41
42
};
42
43
43
44
#define FTR_STRICT true /* SANITY check strict matching required */
+2
arch/arm64/include/asm/daifflags.h
+2
arch/arm64/include/asm/daifflags.h
···
13
13
#define DAIF_PROCCTX 0
14
14
#define DAIF_PROCCTX_NOIRQ PSR_I_BIT
15
15
#define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT)
16
+
#define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
17
+
16
18
17
19
/* mask/save/unmask/restore all exceptions, including interrupts. */
18
20
static inline void local_daif_mask(void)
+5
-1
arch/arm64/include/asm/efi.h
+5
-1
arch/arm64/include/asm/efi.h
···
105
105
((protocol##_t *)instance)->f(instance, ##__VA_ARGS__)
106
106
107
107
#define alloc_screen_info(x...) &screen_info
108
-
#define free_screen_info(x...)
108
+
109
+
static inline void free_screen_info(efi_system_table_t *sys_table_arg,
110
+
struct screen_info *si)
111
+
{
112
+
}
109
113
110
114
/* redeclare as 'hidden' so the compiler will generate relative references */
111
115
extern struct screen_info screen_info __attribute__((__visibility__("hidden")));
+7
-3
arch/arm64/include/asm/memory.h
+7
-3
arch/arm64/include/asm/memory.h
···
210
210
#define __tag_reset(addr) untagged_addr(addr)
211
211
#define __tag_get(addr) (__u8)((u64)(addr) >> 56)
212
212
#else
213
-
#define __tag_set(addr, tag) (addr)
213
+
static inline const void *__tag_set(const void *addr, u8 tag)
214
+
{
215
+
return addr;
216
+
}
217
+
214
218
#define __tag_reset(addr) (addr)
215
219
#define __tag_get(addr) 0
216
220
#endif
···
305
301
#define page_to_virt(page) ({ \
306
302
unsigned long __addr = \
307
303
((__page_to_voff(page)) | PAGE_OFFSET); \
308
-
unsigned long __addr_tag = \
309
-
__tag_set(__addr, page_kasan_tag(page)); \
304
+
const void *__addr_tag = \
305
+
__tag_set((void *)__addr, page_kasan_tag(page)); \
310
306
((void *)__addr_tag); \
311
307
})
312
308
+2
-2
arch/arm64/include/asm/pgtable.h
+2
-2
arch/arm64/include/asm/pgtable.h
···
447
447
PMD_TYPE_SECT)
448
448
449
449
#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
450
-
#define pud_sect(pud) (0)
451
-
#define pud_table(pud) (1)
450
+
static inline bool pud_sect(pud_t pud) { return false; }
451
+
static inline bool pud_table(pud_t pud) { return true; }
452
452
#else
453
453
#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
454
454
PUD_TYPE_SECT)
+1
-1
arch/arm64/include/asm/ptrace.h
+1
-1
arch/arm64/include/asm/ptrace.h
···
30
30
* in the the priority mask, it indicates that PSR.I should be set and
31
31
* interrupt disabling temporarily does not rely on IRQ priorities.
32
32
*/
33
-
#define GIC_PRIO_IRQON 0xc0
33
+
#define GIC_PRIO_IRQON 0xe0
34
34
#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
35
35
#define GIC_PRIO_PSR_I_SET (1 << 4)
36
36
+6
-2
arch/arm64/kernel/cpufeature.c
+6
-2
arch/arm64/kernel/cpufeature.c
···
225
225
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
226
226
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
227
227
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
228
-
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
229
-
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
228
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
229
+
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
230
230
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
231
231
/*
232
232
* Linux can handle differing I-cache policies. Userspace JITs will
···
468
468
case FTR_LOWER_SAFE:
469
469
ret = new < cur ? new : cur;
470
470
break;
471
+
case FTR_HIGHER_OR_ZERO_SAFE:
472
+
if (!cur || !new)
473
+
break;
474
+
/* Fallthrough */
471
475
case FTR_HIGHER_SAFE:
472
476
ret = new > cur ? new : cur;
473
477
break;
+8
-6
arch/arm64/kernel/debug-monitors.c
+8
-6
arch/arm64/kernel/debug-monitors.c
···
207
207
208
208
list = user_mode(regs) ? &user_step_hook : &kernel_step_hook;
209
209
210
-
rcu_read_lock();
211
-
210
+
/*
211
+
* Since single-step exception disables interrupt, this function is
212
+
* entirely not preemptible, and we can use rcu list safely here.
213
+
*/
212
214
list_for_each_entry_rcu(hook, list, node) {
213
215
retval = hook->fn(regs, esr);
214
216
if (retval == DBG_HOOK_HANDLED)
215
217
break;
216
218
}
217
-
218
-
rcu_read_unlock();
219
219
220
220
return retval;
221
221
}
···
305
305
306
306
list = user_mode(regs) ? &user_break_hook : &kernel_break_hook;
307
307
308
-
rcu_read_lock();
308
+
/*
309
+
* Since brk exception disables interrupt, this function is
310
+
* entirely not preemptible, and we can use rcu list safely here.
311
+
*/
309
312
list_for_each_entry_rcu(hook, list, node) {
310
313
unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
311
314
312
315
if ((comment & ~hook->mask) == hook->imm)
313
316
fn = hook->fn;
314
317
}
315
-
rcu_read_unlock();
316
318
317
319
return fn ? fn(regs, esr) : DBG_HOOK_ERROR;
318
320
}
+8
-3
arch/arm64/kernel/hw_breakpoint.c
+8
-3
arch/arm64/kernel/hw_breakpoint.c
···
536
536
/* Aligned */
537
537
break;
538
538
case 1:
539
-
/* Allow single byte watchpoint. */
540
-
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
541
-
break;
542
539
case 2:
543
540
/* Allow halfword watchpoints and breakpoints. */
544
541
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
545
542
break;
543
+
544
+
/* Fallthrough */
545
+
case 3:
546
+
/* Allow single byte watchpoint. */
547
+
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
548
+
break;
549
+
550
+
/* Fallthrough */
546
551
default:
547
552
return -EINVAL;
548
553
}
+4
arch/arm64/kernel/module.c
+4
arch/arm64/kernel/module.c
···
314
314
/* MOVW instruction relocations. */
315
315
case R_AARCH64_MOVW_UABS_G0_NC:
316
316
overflow_check = false;
317
+
/* Fall through */
317
318
case R_AARCH64_MOVW_UABS_G0:
318
319
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
319
320
AARCH64_INSN_IMM_MOVKZ);
320
321
break;
321
322
case R_AARCH64_MOVW_UABS_G1_NC:
322
323
overflow_check = false;
324
+
/* Fall through */
323
325
case R_AARCH64_MOVW_UABS_G1:
324
326
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
325
327
AARCH64_INSN_IMM_MOVKZ);
326
328
break;
327
329
case R_AARCH64_MOVW_UABS_G2_NC:
328
330
overflow_check = false;
331
+
/* Fall through */
329
332
case R_AARCH64_MOVW_UABS_G2:
330
333
ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
331
334
AARCH64_INSN_IMM_MOVKZ);
···
396
393
break;
397
394
case R_AARCH64_ADR_PREL_PG_HI21_NC:
398
395
overflow_check = false;
396
+
/* Fall through */
399
397
case R_AARCH64_ADR_PREL_PG_HI21:
400
398
ovf = reloc_insn_adrp(me, sechdrs, loc, val);
401
399
if (ovf && ovf != -ERANGE)
+6
-34
arch/arm64/kernel/probes/kprobes.c
+6
-34
arch/arm64/kernel/probes/kprobes.c
···
21
21
#include <asm/ptrace.h>
22
22
#include <asm/cacheflush.h>
23
23
#include <asm/debug-monitors.h>
24
+
#include <asm/daifflags.h>
24
25
#include <asm/system_misc.h>
25
26
#include <asm/insn.h>
26
27
#include <linux/uaccess.h>
···
169
168
}
170
169
171
170
/*
172
-
* When PSTATE.D is set (masked), then software step exceptions can not be
173
-
* generated.
174
-
* SPSR's D bit shows the value of PSTATE.D immediately before the
175
-
* exception was taken. PSTATE.D is set while entering into any exception
176
-
* mode, however software clears it for any normal (none-debug-exception)
177
-
* mode in the exception entry. Therefore, when we are entering into kprobe
178
-
* breakpoint handler from any normal mode then SPSR.D bit is already
179
-
* cleared, however it is set when we are entering from any debug exception
180
-
* mode.
181
-
* Since we always need to generate single step exception after a kprobe
182
-
* breakpoint exception therefore we need to clear it unconditionally, when
183
-
* we become sure that the current breakpoint exception is for kprobe.
184
-
*/
185
-
static void __kprobes
186
-
spsr_set_debug_flag(struct pt_regs *regs, int mask)
187
-
{
188
-
unsigned long spsr = regs->pstate;
189
-
190
-
if (mask)
191
-
spsr |= PSR_D_BIT;
192
-
else
193
-
spsr &= ~PSR_D_BIT;
194
-
195
-
regs->pstate = spsr;
196
-
}
197
-
198
-
/*
199
171
* Interrupts need to be disabled before single-step mode is set, and not
200
172
* reenabled until after single-step mode ends.
201
173
* Without disabling interrupt on local CPU, there is a chance of
···
179
205
static void __kprobes kprobes_save_local_irqflag(struct kprobe_ctlblk *kcb,
180
206
struct pt_regs *regs)
181
207
{
182
-
kcb->saved_irqflag = regs->pstate;
208
+
kcb->saved_irqflag = regs->pstate & DAIF_MASK;
183
209
regs->pstate |= PSR_I_BIT;
210
+
/* Unmask PSTATE.D for enabling software step exceptions. */
211
+
regs->pstate &= ~PSR_D_BIT;
184
212
}
185
213
186
214
static void __kprobes kprobes_restore_local_irqflag(struct kprobe_ctlblk *kcb,
187
215
struct pt_regs *regs)
188
216
{
189
-
if (kcb->saved_irqflag & PSR_I_BIT)
190
-
regs->pstate |= PSR_I_BIT;
191
-
else
192
-
regs->pstate &= ~PSR_I_BIT;
217
+
regs->pstate &= ~DAIF_MASK;
218
+
regs->pstate |= kcb->saved_irqflag;
193
219
}
194
220
195
221
static void __kprobes
···
225
251
slot = (unsigned long)p->ainsn.api.insn;
226
252
227
253
set_ss_context(kcb, slot); /* mark pending ss */
228
-
229
-
spsr_set_debug_flag(regs, 0);
230
254
231
255
/* IRQs and single stepping do not mix well. */
232
256
kprobes_save_local_irqflag(kcb, regs);
+3
arch/arm64/kernel/return_address.c
+3
arch/arm64/kernel/return_address.c
···
8
8
9
9
#include <linux/export.h>
10
10
#include <linux/ftrace.h>
11
+
#include <linux/kprobes.h>
11
12
12
13
#include <asm/stack_pointer.h>
13
14
#include <asm/stacktrace.h>
···
30
29
return 0;
31
30
}
32
31
}
32
+
NOKPROBE_SYMBOL(save_return_addr);
33
33
34
34
void *return_address(unsigned int level)
35
35
{
···
51
49
return NULL;
52
50
}
53
51
EXPORT_SYMBOL_GPL(return_address);
52
+
NOKPROBE_SYMBOL(return_address);
+1
-1
arch/arm64/kernel/smp.c
+1
-1
arch/arm64/kernel/smp.c
···
152
152
pr_crit("CPU%u: died during early boot\n", cpu);
153
153
break;
154
154
}
155
-
/* Fall through */
156
155
pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
156
+
/* Fall through */
157
157
case CPU_STUCK_IN_KERNEL:
158
158
pr_crit("CPU%u: is stuck in kernel\n", cpu);
159
159
if (status & CPU_STUCK_REASON_52_BIT_VA)
+3
arch/arm64/kernel/stacktrace.c
+3
arch/arm64/kernel/stacktrace.c
···
7
7
#include <linux/kernel.h>
8
8
#include <linux/export.h>
9
9
#include <linux/ftrace.h>
10
+
#include <linux/kprobes.h>
10
11
#include <linux/sched.h>
11
12
#include <linux/sched/debug.h>
12
13
#include <linux/sched/task_stack.h>
···
112
111
113
112
return 0;
114
113
}
114
+
NOKPROBE_SYMBOL(unwind_frame);
115
115
116
116
void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame,
117
117
int (*fn)(struct stackframe *, void *), void *data)
···
127
125
break;
128
126
}
129
127
}
128
+
NOKPROBE_SYMBOL(walk_stackframe);
130
129
131
130
#ifdef CONFIG_STACKTRACE
132
131
struct stack_trace_data {
+49
-8
arch/arm64/mm/fault.c
+49
-8
arch/arm64/mm/fault.c
···
777
777
debug_fault_info[nr].name = name;
778
778
}
779
779
780
+
/*
781
+
* In debug exception context, we explicitly disable preemption despite
782
+
* having interrupts disabled.
783
+
* This serves two purposes: it makes it much less likely that we would
784
+
* accidentally schedule in exception context and it will force a warning
785
+
* if we somehow manage to schedule by accident.
786
+
*/
787
+
static void debug_exception_enter(struct pt_regs *regs)
788
+
{
789
+
/*
790
+
* Tell lockdep we disabled irqs in entry.S. Do nothing if they were
791
+
* already disabled to preserve the last enabled/disabled addresses.
792
+
*/
793
+
if (interrupts_enabled(regs))
794
+
trace_hardirqs_off();
795
+
796
+
if (user_mode(regs)) {
797
+
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
798
+
} else {
799
+
/*
800
+
* We might have interrupted pretty much anything. In
801
+
* fact, if we're a debug exception, we can even interrupt
802
+
* NMI processing. We don't want this code makes in_nmi()
803
+
* to return true, but we need to notify RCU.
804
+
*/
805
+
rcu_nmi_enter();
806
+
}
807
+
808
+
preempt_disable();
809
+
810
+
/* This code is a bit fragile. Test it. */
811
+
RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work");
812
+
}
813
+
NOKPROBE_SYMBOL(debug_exception_enter);
814
+
815
+
static void debug_exception_exit(struct pt_regs *regs)
816
+
{
817
+
preempt_enable_no_resched();
818
+
819
+
if (!user_mode(regs))
820
+
rcu_nmi_exit();
821
+
822
+
if (interrupts_enabled(regs))
823
+
trace_hardirqs_on();
824
+
}
825
+
NOKPROBE_SYMBOL(debug_exception_exit);
826
+
780
827
#ifdef CONFIG_ARM64_ERRATUM_1463225
781
828
DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
782
829
···
864
817
if (cortex_a76_erratum_1463225_debug_handler(regs))
865
818
return;
866
819
867
-
/*
868
-
* Tell lockdep we disabled irqs in entry.S. Do nothing if they were
869
-
* already disabled to preserve the last enabled/disabled addresses.
870
-
*/
871
-
if (interrupts_enabled(regs))
872
-
trace_hardirqs_off();
820
+
debug_exception_enter(regs);
873
821
874
822
if (user_mode(regs) && !is_ttbr0_addr(pc))
875
823
arm64_apply_bp_hardening();
···
874
832
inf->sig, inf->code, (void __user *)pc, esr);
875
833
}
876
834
877
-
if (interrupts_enabled(regs))
878
-
trace_hardirqs_on();
835
+
debug_exception_exit(regs);
879
836
}
880
837
NOKPROBE_SYMBOL(do_debug_exception);