Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Some late pin control fixes, the most generally annoying will probably
be the AMD IRQ storm fix affecting the Microsoft surface.
Summary:
- Three fixes pertaining to Broadcom DT bindings. Some stuff didn't
work out as inteded, we need to back out
- A resume bug fix in the STM32 driver
- Disable and mask the interrupts on probe in the AMD pinctrl driver,
affecting Microsoft surface"
* tag 'pinctrl-v5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: amd: disable and mask interrupts on probe
pinctrl: stm32: use valid pin identifier in stm32_pinctrl_resume()
Revert "pinctrl: bcm: ns: support updated DT binding as syscon subnode"
dt-bindings: pinctrl: brcm,ns-pinmux: drop unneeded CRU from example
Revert "dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon"
+62
-44
+6
-5
Documentation/devicetree/bindings/mfd/brcm,cru.yaml
+6
-5
Documentation/devicetree/bindings/mfd/brcm,cru.yaml
···
32
32
"#size-cells":
33
33
const: 1
34
34
35
-
pinctrl:
36
-
$ref: ../pinctrl/brcm,ns-pinmux.yaml
37
-
38
35
patternProperties:
39
36
'^clock-controller@[a-f0-9]+$':
40
37
$ref: ../clock/brcm,iproc-clocks.yaml
38
+
39
+
'^pin-controller@[a-f0-9]+$':
40
+
$ref: ../pinctrl/brcm,ns-pinmux.yaml
41
41
42
42
'^thermal@[a-f0-9]+$':
43
43
$ref: ../thermal/brcm,ns-thermal.yaml
···
73
73
"iprocfast", "sata1", "sata2";
74
74
};
75
75
76
-
pinctrl {
76
+
pin-controller@1c0 {
77
77
compatible = "brcm,bcm4708-pinmux";
78
-
offset = <0x1c0>;
78
+
reg = <0x1c0 0x24>;
79
+
reg-names = "cru_gpio_control";
79
80
};
80
81
81
82
thermal@2c0 {
+13
-18
Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml
+13
-18
Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml
···
17
17
18
18
A list of pins varies across chipsets so few bindings are available.
19
19
20
-
Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
21
-
node.
22
-
23
20
properties:
24
21
compatible:
25
22
enum:
···
24
27
- brcm,bcm4709-pinmux
25
28
- brcm,bcm53012-pinmux
26
29
27
-
offset:
28
-
description: offset of pin registers in the CRU block
30
+
reg:
29
31
maxItems: 1
30
-
$ref: /schemas/types.yaml#/definitions/uint32-array
32
+
33
+
reg-names:
34
+
const: cru_gpio_control
31
35
32
36
patternProperties:
33
37
'-pins$':
···
70
72
uart1_grp ]
71
73
72
74
required:
73
-
- offset
75
+
- reg
76
+
- reg-names
74
77
75
78
additionalProperties: false
76
79
77
80
examples:
78
81
- |
79
-
cru@1800c100 {
80
-
compatible = "syscon", "simple-mfd";
81
-
reg = <0x1800c100 0x1a4>;
82
+
pin-controller@1800c1c0 {
83
+
compatible = "brcm,bcm4708-pinmux";
84
+
reg = <0x1800c1c0 0x24>;
85
+
reg-names = "cru_gpio_control";
82
86
83
-
pinctrl {
84
-
compatible = "brcm,bcm4708-pinmux";
85
-
offset = <0xc0>;
86
-
87
-
spi-pins {
88
-
function = "spi";
89
-
groups = "spi_grp";
90
-
};
87
+
spi-pins {
88
+
function = "spi";
89
+
groups = "spi_grp";
91
90
};
92
91
};
+10
-19
drivers/pinctrl/bcm/pinctrl-ns.c
+10
-19
drivers/pinctrl/bcm/pinctrl-ns.c
···
5
5
6
6
#include <linux/err.h>
7
7
#include <linux/io.h>
8
-
#include <linux/mfd/syscon.h>
9
8
#include <linux/module.h>
10
9
#include <linux/of.h>
11
10
#include <linux/of_device.h>
···
12
13
#include <linux/pinctrl/pinctrl.h>
13
14
#include <linux/pinctrl/pinmux.h>
14
15
#include <linux/platform_device.h>
15
-
#include <linux/regmap.h>
16
16
#include <linux/slab.h>
17
17
18
18
#define FLAG_BCM4708 BIT(1)
···
22
24
struct device *dev;
23
25
unsigned int chipset_flag;
24
26
struct pinctrl_dev *pctldev;
25
-
struct regmap *regmap;
26
-
u32 offset;
27
+
void __iomem *base;
27
28
28
29
struct pinctrl_desc pctldesc;
29
30
struct ns_pinctrl_group *groups;
···
229
232
unset |= BIT(pin_number);
230
233
}
231
234
232
-
regmap_read(ns_pinctrl->regmap, ns_pinctrl->offset, &tmp);
235
+
tmp = readl(ns_pinctrl->base);
233
236
tmp &= ~unset;
234
-
regmap_write(ns_pinctrl->regmap, ns_pinctrl->offset, tmp);
237
+
writel(tmp, ns_pinctrl->base);
235
238
236
239
return 0;
237
240
}
···
263
266
static int ns_pinctrl_probe(struct platform_device *pdev)
264
267
{
265
268
struct device *dev = &pdev->dev;
266
-
struct device_node *np = dev->of_node;
267
269
const struct of_device_id *of_id;
268
270
struct ns_pinctrl *ns_pinctrl;
269
271
struct pinctrl_desc *pctldesc;
270
272
struct pinctrl_pin_desc *pin;
271
273
struct ns_pinctrl_group *group;
272
274
struct ns_pinctrl_function *function;
275
+
struct resource *res;
273
276
int i;
274
277
275
278
ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
···
287
290
return -EINVAL;
288
291
ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
289
292
290
-
ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np));
291
-
if (IS_ERR(ns_pinctrl->regmap)) {
292
-
int err = PTR_ERR(ns_pinctrl->regmap);
293
-
294
-
dev_err(dev, "Failed to map pinctrl regs: %d\n", err);
295
-
296
-
return err;
297
-
}
298
-
299
-
if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) {
300
-
dev_err(dev, "Failed to get register offset\n");
301
-
return -ENOENT;
293
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
294
+
"cru_gpio_control");
295
+
ns_pinctrl->base = devm_ioremap_resource(dev, res);
296
+
if (IS_ERR(ns_pinctrl->base)) {
297
+
dev_err(dev, "Failed to map pinctrl regs\n");
298
+
return PTR_ERR(ns_pinctrl->base);
302
299
}
303
300
304
301
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
+31
drivers/pinctrl/pinctrl-amd.c
+31
drivers/pinctrl/pinctrl-amd.c
···
840
840
.pin_config_group_set = amd_pinconf_group_set,
841
841
};
842
842
843
+
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
844
+
{
845
+
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
846
+
unsigned long flags;
847
+
u32 pin_reg, mask;
848
+
int i;
849
+
850
+
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
851
+
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
852
+
BIT(WAKE_CNTRL_OFF_S4);
853
+
854
+
for (i = 0; i < desc->npins; i++) {
855
+
int pin = desc->pins[i].number;
856
+
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
857
+
858
+
if (!pd)
859
+
continue;
860
+
861
+
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
862
+
863
+
pin_reg = readl(gpio_dev->base + i * 4);
864
+
pin_reg &= ~mask;
865
+
writel(pin_reg, gpio_dev->base + i * 4);
866
+
867
+
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
868
+
}
869
+
}
870
+
843
871
#ifdef CONFIG_PM_SLEEP
844
872
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
845
873
{
···
1003
975
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1004
976
return PTR_ERR(gpio_dev->pctrl);
1005
977
}
978
+
979
+
/* Disable and mask interrupts */
980
+
amd_gpio_irq_init(gpio_dev);
1006
981
1007
982
girq = &gpio_dev->gc.irq;
1008
983
girq->chip = &amd_gpio_irqchip;
+2
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
+2
-2
drivers/pinctrl/stm32/pinctrl-stm32.c
···
1644
1644
struct stm32_pinctrl_group *g = pctl->groups;
1645
1645
int i;
1646
1646
1647
-
for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1648
-
stm32_pinctrl_restore_gpio_regs(pctl, i);
1647
+
for (i = 0; i < pctl->ngroups; i++, g++)
1648
+
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1649
1649
1650
1650
return 0;
1651
1651
}