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Merge tag 'ntb-6.15' of https://github.com/jonmason/ntb

Pull ntb fixes from Jon Mason:
"Bug fixes for NTB Switchtec driver mw negative shift, Intel NTB link
status db, ntb_perf double unmap (in error case), and MSI 64bit
arithmetic.

Also, add new AMD NTB PCI IDs, update AMD NTB maintainer, and pull in
patch to reduce the stack usage in IDT driver"

* tag 'ntb-6.15' of https://github.com/jonmason/ntb:
ntb_hw_amd: Add NTB PCI ID for new gen CPU
ntb: reduce stack usage in idt_scan_mws
ntb: use 64-bit arithmetic for the MSI doorbell mask
MAINTAINERS: Update AMD NTB maintainers
ntb_perf: Delete duplicate dmaengine_unmap_put() call in perf_copy_chunk()
ntb: intel: Fix using link status DB's
ntb_hw_switchtec: Fix shift-out-of-bounds in switchtec_ntb_mw_set_trans

+14 -17
-1
MAINTAINERS
··· 17244 17244 F: scripts/nsdeps 17245 17245 17246 17246 NTB AMD DRIVER 17247 - M: Sanjay R Mehta <sanju.mehta@amd.com> 17248 17247 M: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 17249 17248 L: ntb@lists.linux.dev 17250 17249 S: Supported
+1
drivers/ntb/hw/amd/ntb_hw_amd.c
··· 1318 1318 { PCI_VDEVICE(AMD, 0x148b), (kernel_ulong_t)&dev_data[1] }, 1319 1319 { PCI_VDEVICE(AMD, 0x14c0), (kernel_ulong_t)&dev_data[1] }, 1320 1320 { PCI_VDEVICE(AMD, 0x14c3), (kernel_ulong_t)&dev_data[1] }, 1321 + { PCI_VDEVICE(AMD, 0x155a), (kernel_ulong_t)&dev_data[1] }, 1321 1322 { PCI_VDEVICE(HYGON, 0x145b), (kernel_ulong_t)&dev_data[0] }, 1322 1323 { 0, } 1323 1324 };
+7 -11
drivers/ntb/hw/idt/ntb_hw_idt.c
··· 1041 1041 static struct idt_mw_cfg *idt_scan_mws(struct idt_ntb_dev *ndev, int port, 1042 1042 unsigned char *mw_cnt) 1043 1043 { 1044 - struct idt_mw_cfg mws[IDT_MAX_NR_MWS], *ret_mws; 1044 + struct idt_mw_cfg *mws; 1045 1045 const struct idt_ntb_bar *bars; 1046 1046 enum idt_mw_type mw_type; 1047 1047 unsigned char widx, bidx, en_cnt; 1048 1048 bool bar_64bit = false; 1049 1049 int aprt_size; 1050 1050 u32 data; 1051 + 1052 + mws = devm_kcalloc(&ndev->ntb.pdev->dev, IDT_MAX_NR_MWS, 1053 + sizeof(*mws), GFP_KERNEL); 1054 + if (!mws) 1055 + return ERR_PTR(-ENOMEM); 1051 1056 1052 1057 /* Retrieve the array of the BARs registers */ 1053 1058 bars = portdata_tbl[port].bars; ··· 1108 1103 } 1109 1104 } 1110 1105 1111 - /* Allocate memory for memory window descriptors */ 1112 - ret_mws = devm_kcalloc(&ndev->ntb.pdev->dev, *mw_cnt, sizeof(*ret_mws), 1113 - GFP_KERNEL); 1114 - if (!ret_mws) 1115 - return ERR_PTR(-ENOMEM); 1116 - 1117 - /* Copy the info of detected memory windows */ 1118 - memcpy(ret_mws, mws, (*mw_cnt)*sizeof(*ret_mws)); 1119 - 1120 - return ret_mws; 1106 + return mws; 1121 1107 } 1122 1108 1123 1109 /*
+3
drivers/ntb/hw/intel/ntb_hw_gen3.c
··· 215 215 } 216 216 217 217 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; 218 + /* Make sure we are not using DB's used for link status */ 219 + if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) 220 + ndev->db_valid_mask &= ~ndev->db_link_mask; 218 221 219 222 ndev->reg->db_iowrite(ndev->db_valid_mask, 220 223 ndev->self_mmio +
+1 -1
drivers/ntb/hw/mscc/ntb_hw_switchtec.c
··· 288 288 if (size != 0 && xlate_pos < 12) 289 289 return -EINVAL; 290 290 291 - if (!IS_ALIGNED(addr, BIT_ULL(xlate_pos))) { 291 + if (xlate_pos >= 0 && !IS_ALIGNED(addr, BIT_ULL(xlate_pos))) { 292 292 /* 293 293 * In certain circumstances we can get a buffer that is 294 294 * not aligned to its size. (Most of the time
+1 -1
drivers/ntb/ntb_transport.c
··· 1353 1353 qp_count = ilog2(qp_bitmap); 1354 1354 if (nt->use_msi) { 1355 1355 qp_count -= 1; 1356 - nt->msi_db_mask = 1 << qp_count; 1356 + nt->msi_db_mask = BIT_ULL(qp_count); 1357 1357 ntb_db_clear_mask(ndev, nt->msi_db_mask); 1358 1358 } 1359 1359
+1 -3
drivers/ntb/test/ntb_perf.c
··· 839 839 dma_set_unmap(tx, unmap); 840 840 841 841 ret = dma_submit_error(dmaengine_submit(tx)); 842 - if (ret) { 843 - dmaengine_unmap_put(unmap); 842 + if (ret) 844 843 goto err_free_resource; 845 - } 846 844 847 845 dmaengine_unmap_put(unmap); 848 846