Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: fpga: Convert lattice,ice40-fpga-mgr to DT schema
Convert the lattice,ice40-fpga-mgr binding to DT schema format. It's a
straight-forward conversion.
Link: https://patch.msgid.link/20251029185503.2124434-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+59
-21
+59
Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml
+59
Documentation/devicetree/bindings/fpga/lattice,ice40-fpga-mgr.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/lattice,ice40-fpga-mgr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lattice iCE40 FPGA Manager
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maintainers:
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- Joel Holdsworth <joel@airwebreathe.org.uk>
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properties:
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compatible:
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const: lattice,ice40-fpga-mgr
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reg:
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maxItems: 1
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spi-max-frequency:
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minimum: 1000000
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maximum: 25000000
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cdone-gpios:
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maxItems: 1
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description: GPIO input connected to CDONE pin
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reset-gpios:
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maxItems: 1
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description:
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Active-low GPIO output connected to CRESET_B pin. Note that unless the
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GPIO is held low during startup, the FPGA will enter Master SPI mode and
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drive SCK with a clock signal potentially jamming other devices on the bus
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until the firmware is loaded.
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required:
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- compatible
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- reg
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- spi-max-frequency
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- cdone-gpios
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- reset-gpios
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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fpga@0 {
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compatible = "lattice,ice40-fpga-mgr";
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reg = <0>;
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spi-max-frequency = <1000000>;
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cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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};
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};
-21
Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
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Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
···
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Lattice iCE40 FPGA Manager
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Required properties:
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- compatible: Should contain "lattice,ice40-fpga-mgr"
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- reg: SPI chip select
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- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
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- cdone-gpios: GPIO input connected to CDONE pin
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- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
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that unless the GPIO is held low during startup, the
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FPGA will enter Master SPI mode and drive SCK with a
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clock signal potentially jamming other devices on the
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bus until the firmware is loaded.
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Example:
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fpga: fpga@0 {
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compatible = "lattice,ice40-fpga-mgr";
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reg = <0>;
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spi-max-frequency = <1000000>;
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cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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};