tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon/kms: Silent spurious error message
drm/radeon/kms: fix bad cast/shift in evergreen.c
drm/radeon/kms: make TV/DFP table info less verbose
drm/radeon/kms: leave certain CP int bits enabled
drm/radeon/kms: avoid corner case issue with unmappable vram V2

Linus Torvalds a56f31a0 509d4486

+40 -30
+3 -2
drivers/gpu/drm/radeon/evergreen.c
··· 1137 1137 1138 1138 WREG32(RCU_IND_INDEX, 0x203); 1139 1139 efuse_straps_3 = RREG32(RCU_IND_DATA); 1140 - efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28; 1140 + efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); 1141 1141 1142 1142 switch(efuse_box_bit_127_124) { 1143 1143 case 0x0: ··· 1407 1407 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1408 1408 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 1409 1409 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1410 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1410 1411 r600_vram_gtt_location(rdev, &rdev->mc); 1411 1412 radeon_update_bandwidth_info(rdev); 1412 1413 ··· 1521 1520 { 1522 1521 u32 tmp; 1523 1522 1524 - WREG32(CP_INT_CNTL, 0); 1523 + WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 1525 1524 WREG32(GRBM_INT_CNTL, 0); 1526 1525 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1527 1526 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+3
drivers/gpu/drm/radeon/r100.c
··· 1030 1030 return r; 1031 1031 } 1032 1032 rdev->cp.ready = true; 1033 + rdev->mc.active_vram_size = rdev->mc.real_vram_size; 1033 1034 return 0; 1034 1035 } 1035 1036 ··· 1048 1047 void r100_cp_disable(struct radeon_device *rdev) 1049 1048 { 1050 1049 /* Disable ring */ 1050 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1051 1051 rdev->cp.ready = false; 1052 1052 WREG32(RADEON_CP_CSQ_MODE, 0); 1053 1053 WREG32(RADEON_CP_CSQ_CNTL, 0); ··· 2297 2295 /* FIXME we don't use the second aperture yet when we could use it */ 2298 2296 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2299 2297 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2298 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2300 2299 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2301 2300 if (rdev->flags & RADEON_IS_IGP) { 2302 2301 uint32_t tom;
+3 -1
drivers/gpu/drm/radeon/r600.c
··· 1248 1248 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1249 1249 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1250 1250 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1251 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1251 1252 r600_vram_gtt_location(rdev, &rdev->mc); 1252 1253 1253 1254 if (rdev->flags & RADEON_IS_IGP) { ··· 1918 1917 */ 1919 1918 void r600_cp_stop(struct radeon_device *rdev) 1920 1919 { 1920 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1921 1921 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1922 1922 } 1923 1923 ··· 2912 2910 { 2913 2911 u32 tmp; 2914 2912 2915 - WREG32(CP_INT_CNTL, 0); 2913 + WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2916 2914 WREG32(GRBM_INT_CNTL, 0); 2917 2915 WREG32(DxMODE_INT_MASK, 0); 2918 2916 if (ASIC_IS_DCE3(rdev)) {
+2
drivers/gpu/drm/radeon/r600_blit_kms.c
··· 532 532 memcpy(ptr + rdev->r600_blit.ps_offset, r6xx_ps, r6xx_ps_size * 4); 533 533 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 534 534 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 535 + rdev->mc.active_vram_size = rdev->mc.real_vram_size; 535 536 return 0; 536 537 } 537 538 ··· 540 539 { 541 540 int r; 542 541 542 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 543 543 if (rdev->r600_blit.shader_obj == NULL) 544 544 return; 545 545 /* If we can't reserve the bo, unref should be enough to destroy
+1
drivers/gpu/drm/radeon/radeon.h
··· 344 344 * about vram size near mc fb location */ 345 345 u64 mc_vram_size; 346 346 u64 visible_vram_size; 347 + u64 active_vram_size; 347 348 u64 gtt_size; 348 349 u64 gtt_start; 349 350 u64 gtt_end;
+9 -9
drivers/gpu/drm/radeon/radeon_atombios.c
··· 1558 1558 switch (tv_info->ucTV_BootUpDefaultStandard) { 1559 1559 case ATOM_TV_NTSC: 1560 1560 tv_std = TV_STD_NTSC; 1561 - DRM_INFO("Default TV standard: NTSC\n"); 1561 + DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1562 1562 break; 1563 1563 case ATOM_TV_NTSCJ: 1564 1564 tv_std = TV_STD_NTSC_J; 1565 - DRM_INFO("Default TV standard: NTSC-J\n"); 1565 + DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1566 1566 break; 1567 1567 case ATOM_TV_PAL: 1568 1568 tv_std = TV_STD_PAL; 1569 - DRM_INFO("Default TV standard: PAL\n"); 1569 + DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1570 1570 break; 1571 1571 case ATOM_TV_PALM: 1572 1572 tv_std = TV_STD_PAL_M; 1573 - DRM_INFO("Default TV standard: PAL-M\n"); 1573 + DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1574 1574 break; 1575 1575 case ATOM_TV_PALN: 1576 1576 tv_std = TV_STD_PAL_N; 1577 - DRM_INFO("Default TV standard: PAL-N\n"); 1577 + DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1578 1578 break; 1579 1579 case ATOM_TV_PALCN: 1580 1580 tv_std = TV_STD_PAL_CN; 1581 - DRM_INFO("Default TV standard: PAL-CN\n"); 1581 + DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1582 1582 break; 1583 1583 case ATOM_TV_PAL60: 1584 1584 tv_std = TV_STD_PAL_60; 1585 - DRM_INFO("Default TV standard: PAL-60\n"); 1585 + DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1586 1586 break; 1587 1587 case ATOM_TV_SECAM: 1588 1588 tv_std = TV_STD_SECAM; 1589 - DRM_INFO("Default TV standard: SECAM\n"); 1589 + DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1590 1590 break; 1591 1591 default: 1592 1592 tv_std = TV_STD_NTSC; 1593 - DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); 1593 + DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1594 1594 break; 1595 1595 } 1596 1596 }
+13 -13
drivers/gpu/drm/radeon/radeon_combios.c
··· 913 913 switch (RBIOS8(tv_info + 7) & 0xf) { 914 914 case 1: 915 915 tv_std = TV_STD_NTSC; 916 - DRM_INFO("Default TV standard: NTSC\n"); 916 + DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 917 917 break; 918 918 case 2: 919 919 tv_std = TV_STD_PAL; 920 - DRM_INFO("Default TV standard: PAL\n"); 920 + DRM_DEBUG_KMS("Default TV standard: PAL\n"); 921 921 break; 922 922 case 3: 923 923 tv_std = TV_STD_PAL_M; 924 - DRM_INFO("Default TV standard: PAL-M\n"); 924 + DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 925 925 break; 926 926 case 4: 927 927 tv_std = TV_STD_PAL_60; 928 - DRM_INFO("Default TV standard: PAL-60\n"); 928 + DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 929 929 break; 930 930 case 5: 931 931 tv_std = TV_STD_NTSC_J; 932 - DRM_INFO("Default TV standard: NTSC-J\n"); 932 + DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 933 933 break; 934 934 case 6: 935 935 tv_std = TV_STD_SCART_PAL; 936 - DRM_INFO("Default TV standard: SCART-PAL\n"); 936 + DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 937 937 break; 938 938 default: 939 939 tv_std = TV_STD_NTSC; 940 - DRM_INFO 940 + DRM_DEBUG_KMS 941 941 ("Unknown TV standard; defaulting to NTSC\n"); 942 942 break; 943 943 } 944 944 945 945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 946 946 case 0: 947 - DRM_INFO("29.498928713 MHz TV ref clk\n"); 947 + DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 948 948 break; 949 949 case 1: 950 - DRM_INFO("28.636360000 MHz TV ref clk\n"); 950 + DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 951 951 break; 952 952 case 2: 953 - DRM_INFO("14.318180000 MHz TV ref clk\n"); 953 + DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 954 954 break; 955 955 case 3: 956 - DRM_INFO("27.000000000 MHz TV ref clk\n"); 956 + DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 957 957 break; 958 958 default: 959 959 break; ··· 1324 1324 1325 1325 if (tmds_info) { 1326 1326 ver = RBIOS8(tmds_info); 1327 - DRM_INFO("DFP table revision: %d\n", ver); 1327 + DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1328 1328 if (ver == 3) { 1329 1329 n = RBIOS8(tmds_info + 5) + 1; 1330 1330 if (n > 4) ··· 1408 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1409 1409 if (offset) { 1410 1410 ver = RBIOS8(offset); 1411 - DRM_INFO("External TMDS Table revision: %d\n", ver); 1411 + DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1412 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1413 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1414 1414 gpio = RBIOS8(offset + 4 + 3);
+1 -1
drivers/gpu/drm/radeon/radeon_object.c
··· 69 69 u32 c = 0; 70 70 71 71 rbo->placement.fpfn = 0; 72 - rbo->placement.lpfn = 0; 72 + rbo->placement.lpfn = rbo->rdev->mc.active_vram_size >> PAGE_SHIFT; 73 73 rbo->placement.placement = rbo->placements; 74 74 rbo->placement.busy_placement = rbo->placements; 75 75 if (domain & RADEON_GEM_DOMAIN_VRAM)
+1 -4
drivers/gpu/drm/radeon/radeon_object.h
··· 124 124 int r; 125 125 126 126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 127 - if (unlikely(r != 0)) { 128 - if (r != -ERESTARTSYS) 129 - dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo); 127 + if (unlikely(r != 0)) 130 128 return r; 131 - } 132 129 spin_lock(&bo->tbo.lock); 133 130 if (mem_type) 134 131 *mem_type = bo->tbo.mem.mem_type;
+1
drivers/gpu/drm/radeon/rs600.c
··· 693 693 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 694 694 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 695 695 rdev->mc.visible_vram_size = rdev->mc.aper_size; 696 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 696 697 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 697 698 base = RREG32_MC(R_000004_MC_FB_LOCATION); 698 699 base = G_000004_MC_FB_START(base) << 16;
+1
drivers/gpu/drm/radeon/rs690.c
··· 157 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 158 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 159 159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 160 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 160 161 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 161 162 base = G_000100_MC_FB_START(base) << 16; 162 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+2
drivers/gpu/drm/radeon/rv770.c
··· 267 267 */ 268 268 void r700_cp_stop(struct radeon_device *rdev) 269 269 { 270 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 270 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 271 272 } 272 273 ··· 993 992 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 994 993 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 995 994 rdev->mc.visible_vram_size = rdev->mc.aper_size; 995 + rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 996 996 r600_vram_gtt_location(rdev, &rdev->mc); 997 997 radeon_update_bandwidth_info(rdev); 998 998